Secrets of level-translation revealed | EE Times

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Secrets of level-translation revealed

Prasad Dhond, Applications Specialist, Texas Instruments
10/27/2004 10:00 PM EDT Post a comment
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The need for logic voltage level translation is prevalent on most electronic systems today. For example, an ASIC might be operating with supply-voltage VCCA, while an I/O device operates with a different supply-voltage VCCB. To enable these devices to communicate with each other, a level-translation solution is needed. Input-voltage thresholds and output-voltage levels of electronic devices vary, depending on the device technology and supply voltage used. Figure 1 shows the logic threshold levels for different supply voltages and device technologies. To interface two devices successfully, certain requirements must be met: 1. The VOH (Output High Voltage) of the driver must be greater than the VIH (Input High Voltage) of the receiver. 2. The V OL (Output Low Voltage) of the driver must be less than the VIL (Input Low Voltage) of the receiver. 3. The output voltage from the driver must not exceed the I/O voltage tolerance of the receiver. There are several methods of achieving level translation and each method has its own merits and demerits. Figure 1. Digital Switching Levels

Click to Enlarge Dual-supply level translators These are unidirectional or bidirectional devices with two supply voltage pins: one to interface with the low-voltage side and another to interface with the high-voltage side. Figure 2 shows one implementation of how a logic signal referenced to VCCA is levelshifted to a signal referenced to VCCB. If logic high is applied to the input, transistor T9 in the level translating block turns on, and the output is pulled to VCCB through T10. If logic Low is applied at the input, transistors T6, T7 and T8 are turned on, and the output is pulled low through T11. Figure 2. How a push-pull level translator works

Click to Enlarge This design ensures that there is never a constant path from VCCA or VCCB to ground, which enables very low quiescent current consumption. Transistors T10 and T11 in the output block can be sized to offer the current drive required for the application. Figure 2 shows a uni-directional buffer. For bi-directional level shifting, a similar return path is required. Figure 3 shows an implementation of a dual-supply level-translator that uses a control signal to control the data flow direction. The advantage of this configuration is that the output drivers can be as strong as needed and maximum frequency is restricted only by the output load and switching speed of the output transistors. Consequently, these devices are typically designed to sink/source currents of up to several tens of mA and they support frequencies of up to several hundreds of Mbps. Figure 3. Fully Buffered Voltage Translation

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