NOORUL ISLAM COLLEGE OF ENGINEERING, KUMARACOIL, FIFTH SEMESTER COMPUTER SCIENCE AND ENGINEERING CS 1304-MICROPROCESSORS 1. What is Micro roc!

ssor" Gi#! th! o$!r s% &' ( c&oc) *r!+%!,c' o* -.-/ A microprocessor is a multipurpose, programmable logic de ice t!at reads bi"ar# i"structio"s $rom a storage de ice called memor# accepts bi"ar# data as i"put a"d processes data accordi"g to t!ose i"structio"s a"d pro ides result as output% &!e po'er suppl# o$ (0() is *)+ a"d cloc, $re-ue"c# i" 3M./% 0. List *!$ a &icatio,s o* 1icro roc!ssor23as!4 s'st!1. It is used0 i% 1or measureme"ts, displa# a"d co"trol o$ curre"t, oltage, temperature, pressure, etc% ii% 1or tra$$ic co"trol a"d i"dustrial tool co"trol% iii% 1or speed co"trol o$ mac!i"es% 5. What ar! th! *%,ctio,s o* a, acc%1%&ator" &!e accumulator is t!e register associated 'it! t!e A23 operatio"s a"d sometimes I4O operatio"s% It is a" i"tegral part o$ A23% It !olds o"e o$ data to be processed b# A23% It also temporaril# stores t!e result o$ t!e operatio" per$ormed b# t!e A23% 6. List th! 17 8 3it r!9ist!rs o* -.-/ 1icro roc!ssor. Stac, poi"ter 5SP6 a"d Program cou"ter 5PC6% /. List th! a&&o$!4 r!9ist!r airs o* -.-/. 7-C register pair 8-E register pair .-2 register pair 7. M!,tio, th! %r os! o* SID a,4 SOD &i,!s SI8 5Serial i"put data li"e60 It is a" i"put li"e t!roug! '!ic! t!e microprocessor accepts serial data% SO8 5Serial output data li"e60 It is a" output li"e t!roug! '!ic! t!e microprocessor se"ds output serial data% :. What is a, O co4!" &!e part o$ t!e i"structio" t!at speci$ies t!e operatio" to be per$ormed is called t!e operatio" code or opcode% -. What is th! *%,ctio, o* IO;M si9,a& i, th! -.-/"

It is a status sig"al% It is used to di$$ere"tiate bet'ee" memor# locatio"s a"d I4O operatio"s% 9!e" t!is sig"al is lo' 5IO4M : 06 it de"otes t!e memor# related operatio"s% 9!e" t!is sig"al is !ig! 5IO4M : 16 it de"otes a" I4O operatio"% <. What is a, O !ra,4" &!e data o" '!ic! t!e operatio" is to be per$ormed is called as a" Opera"d% 1.. Ho$ 1a,' o !ratio,s ar! th!r! i, th! i,str%ctio, s!t o* -.-/ 1icro roc!ssor" &!ere are ;4 operatio"s i" t!e (0() microprocessor% 11. List o%t th! *i#! cat!9ori!s o* th! -.-/ i,str%ctio,s. Gi#! !=a1 &!s o* th! i,str%ctio,s *or !ach 9ro% . 8ata tra"s$er group < MO+, M+I, 2=I% Arit!metic group < A88, S37, I>R% 2ogical group <A>A, =RA, CMP% 7ra"c! group < ?MP, ?>@, CA22% Stac, I4O a"d Mac!i"e co"trol group < P3S., POP, I>, .2&% 10. E= &ai, th! 4i**!r!,c! 3!t$!!, a >MP i,str%ctio, a,4 CALL i,str%ctio,. A ?MP i"structio" perma"e"tl# c!a"ges t!e program cou"ter% A CA22 i"structio" lea es i"$ormatio" o" t!e stac, so t!at t!e origi"al program eAecutio" se-ue"ce ca" be resumed% 15. E= &ai, th! %r os! o* th! I;O i,str%ctio,s IN a,4 OUT. &!e I> i"structio" is used to mo e data $rom a" I4O port i"to t!e accumulator% &!e O3& i"structio" is used to mo e data $rom t!e accumulator to a" I4O port% &!e I> B O3& i"structio"s are used o"l# o" microprocessor, '!ic! use a separate address space $or i"ter$aci"g% 16. What is th! 4i**!r!,c! 3!t$!!, th! shi*t a,4 rotat! i,str%ctio,s" A rotate i"structio" is a closed loop i"structio"% &!at is, t!e data mo ed out at o"e e"d is put bac, i" at t!e ot!er e"d% &!e s!i$t i"structio" loses t!e data t!at is mo ed out o$ t!e last bit locatio"s% 1/. Ho$ 1a,' a44r!ss &i,!s i, a 6.<7 = - EPROM CHIP" 1C address li"es% 17. Co,tro& si9,a&s %s!4 *or DMA o !ratio, ar! ????????????

.O28 B .28A% 1:. What is 1!a,t 3' Wait Stat!" &!is state is used b# slo' perip!eral de ices% &!e perip!eral de ices ca" tra"s$er t!e data to or $rom t!e microprocessor b# usi"g REA8D i"put li"e% &!e microprocessor remai"s i" 'ait state as lo"g as REA8D li"e is lo'% 8uri"g t!e 'ait state, t!e co"te"ts o$ t!e address, address4data a"d co"trol buses are !eld co"sta"t% 1-. List th! *o%r i,str%ctio,s $hich co,tro& th! i,t!rr% t str%ct%r! o* th! -.-/ 1icro roc!ssor. 8I 5 8isable I"terrupts 6 EI 5 E"able I"terrupts 6 RIM 5 Read I"terrupt Mas,s 6 SIM 5 Set I"terrupt Mas,s 6 1<. What is 1!a,t 3' o&&i,9" Polli"g or de ice polli"g is a process '!ic! ide"ti$ies t!e de ice t!at !as i"terrupted t!e microprocessor% 0.. What is 1!a,t 3' i,t!rr% t" I"terrupt is a" eAter"al sig"al t!at causes a microprocessor to Eump to a speci$ic subrouti"e% 01. E= &ai, riorit' i,t!rr% ts o* -.-/. &!e (0() microprocessor !as $i e i"terrupt i"puts% &!e# are &RAP, RS& ;%), RS& F%), RS& )%), a"d I>&R% &!ese i"terrupts !a e a $iAed priorit# o$ i"terrupt ser ice% I$ t'o or more i"terrupts go !ig! at t!e same time, t!e (0() 'ill ser ice t!em o" priorit# basis% &!e &RAP !as t!e !ig!est priorit# $ollo'ed b#e RS& ;%), RS& F%), RS& )%)% &!e priorit# o$ i"terrupts i" (0() is s!o'" i" t!e table% I"terrupts Priorit# &RAP RS& ;%) RS& F%) RS& )%) I>&R 1 C

3 4 ) 00. What is a 1icroco1 %t!r" A computer t!at is desig"ed usi"g a microprocessor as its CP3 is called microcomputer% 05. What is th! si9,a& c&assi*icatio, o* -.-/ All t!e sig"als o$ (0() ca" be classi$ied i"to F groups Address bus 8ata bus Co"trol a"d status sig"als Po'er suppl# a"d $re-ue"c# sig"als EAter"all# i"itiated sig"als Serial I4O ports 06. What ar! o !ratio,s !r*or1!4 o, 4ata i, -.-/ &!e arious operatio"s per$ormed are Store (-bit data Per$orm arit!metic a"d logical operatio"s &est $or co"ditio"s Se-ue"ce t!e eAecutio" o$ i"structio"s Store data temporaril# duri"g eAecutio" i" t!e de$i"ed R49 memor# locatio"s called t!e stac, 0/. St! s i,#o&#!4 to *!tch a 3't! i, -.-/ i% &!e PC places t!e 1F-bit memor# address o" t!e address bus ii% &!e co"trol u"it se"ds t!e co"trol sig"al R8 to e"able t!e memor# c!ip iii% &!e b#te $rom t!e memor# locatio" is placed o" t!e data bus i % &!e b#te is placed i" t!e i"structio" decoder o$ t!e microprocessor a"d t!e tas, is carried out accordi"g to t!e i"structio" 07. Ho$ 1a,' i,t!rr% ts 4o!s -.-/ ha#!, 1!,tio, th!1 &!e (0() !as ) i"terrupt sig"alsG t!e# are I>&R, RS&;%), RS&F%), RS&)%) a"d &RAP 0:. @asic co,c! ts i, 1!1or' i,t!r*aci,9 &!e primar# $u"ctio" o$ memor# i"ter$aci"g is t!at t!e microprocessor s!ould be able to read $rom a"d 'rite i"to a gi e" register o$ a memor# c!ip% &o per$orm t!ese operatio"s t!e microprocessor s!ould 7e able to select t!e c!ip Ide"ti$# t!e register E"able t!e appropriate bu$$er 0-. D!*i,! i,str%ctio, c'c&!, 1achi,! c'c&! a,4 T2stat!

I"structio" c#cle is de$i"ed, as t!e time re-uired completi"g t!e eAecutio" o$ a" i"structio"% Mac!i"e c#cle is de$i"ed as t!e time re-uired completi"g o"e operatio" o$ accessi"g memor#, I4O or ac,"o'ledgi"g a" eAter"al re-uest% &c#cle is de$i"ed as o"e subdi isio" o$ t!e operatio" per$ormed i" o"e cloc, period 0<. What is a, i,str%ctio," A" i"structio" is a bi"ar# patter" e"tered t!roug! a" i"put de ice to comma"d t!e microprocessor to per$orm t!at speci$ic $u"ctio" 5.. What is th! %s! o* ALE &!e A2E is used to latc! t!e lo'er order address so t!at it ca" be a ailable i" &C a"d &3 a"d used $or ide"ti$#i"g t!e memor# address% 8uri"g &1 t!e A2E goes !ig!, t!e latc! is tra"spare"t ie, t!e output c!a"ges accordi"g to t!e i"put data, so t!e output o$ t!e latc! is t!e lo'er order address% 9!e" A2E goes lo' t!e lo'er order address is latc!ed u"til t!e "eAt A2E% 51. Ho$ 1a,' 1achi,! c'c&!s 4o!s -.-/ ha#!, 1!,tio, th!1 &!e (0() !a e se e" mac!i"e c#cles% &!e# are Opcode $etc! Memor# read Memor# 'rite I4O read I4O 'rite I"terrupt ac,"o'ledge 7us idle 50. E= &ai, th! si9,a&s HOLD, READA a,4 SID .O28 i"dicates t!at a perip!eral suc! as 8MA co"troller is re-uesti"g t!e use o$ address bus, data bus a"d co"trol bus% REA8D is used to dela# t!e microprocessor read or 'rite c#cles u"til a slo' respo"di"g perip!eral is read# to se"d or accept data% SI8 is used to accept serial data bit b# bit 55. M!,tio, th! cat!9ori!s o* i,str%ctio, a,4 9i#! t$o !=a1 &!s *or !ach cat!9or' &!e i"structio"s o$ (0() ca" be categori/ed i"to t!e $ollo'i"g $i e 8ata tra"s$er MO+ Rd,Rs S&A 1F-bit Arit!metic A88 R 8CR M 2ogical =RI (-bit RAR

7ra"c!i"g ?>@ CA22 1F-bit Mac!i"e co"trol .2& >OP 56. E= &ai, LDA, STA a,4 DAA i,str%ctio,s 28A copies t!e data b#te i"to accumulator $rom t!e memor# locatio" speci$ied b# t!e 1F-bit address% S&A copies t!e data b#te $rom t!e accumulator i" t!e memor# locatio" speci$ied b# 1F-bit address% 8AA c!a"ges t!e co"te"ts o$ t!e accumulator $rom bi"ar# to 4-bit 7C8 digits% 5/. E= &ai, th! 4i**!r!,t i,str%ctio, *or1ats $ith !=a1 &!s &!e i"structio" set is grouped i"to t!e $ollo'i"g $ormats O"e b#te i"structio" MO+ C,A &'o b#te i"structio" M+I A,3H. &!ree b#te i"structio" ?MP C34). 57. What is th! %s! o* a44r!ssi,9 1o4!s, 1!,tio, th! 4i**!r!,t t' !s &!e arious $ormats o$ speci$#i"g t!e opera"ds are called addressi"g modes, it is used to access t!e opera"ds or data% &!e di$$ere"t t#pes are as $ollo's Immediate addressi"g Register addressi"g 8irect addressi"g I"direct addressi"g Implicit addressi"g 5:. What is th! %s! o* 3i24ir!ctio,a& 3%**!rs" It is used to i"crease t!e dri i"g capacit# o$ t!e data bus% &!e data bus o$ a microcomputer s#stem is bi-directio"al, so it re-uires a bu$$er t!at allo's t!e data to $lo' i" bot! directio"s% 5-. Gi#! th! r!9ist!r or9a,iBatio, o* -.-/ 5<. D!*i,! stac) a,4 != &ai, stac) r!&at!4 i,str%ctio,s &!e stac, is a group o$ memor# locatio"s i" t!e R49 memor# t!at is used $or t!e temporar# storage o$ bi"ar# i"$ormatio" duri"g t!e eAecutio" o$ t!e program% &!e stac, related i"structio"s are P3S. B POP 6.. Wh' 4o $! %s! CRA A i,str%ctio, &!e =RA A i"structio" is used to clear t!e co"te"ts o$ t!e Accumulator a"d store t!e alue 00.% 61. Co1 ar! CALL a,4 PUSH i,str%ctio,s CALL PUSH 9!e" CA22 is eAecuted t!e microprocessor automaticall# stores t!e 1F-bit address o$ t!e i"structio" "eAt to

CA22 o" t!e stac, &!e programmer uses t!e i"structio" P3S. to sa e t!e co"te"ts o$ t!e register pair o" t!e stac, 9!e" CA22 is eAecuted t!e stac, poi"ter is decreme"ted b# t'o 9!e" P3S. is eAecuted t!e stac, poi"ter register is decreme"ted b# t'o 95(6 &emp% Reg @5(6 &emp% Reg 75(6 Register C5(6 Register 85(6 Register E5(6 Register .5(6 Register 25(6 Register Stac, Poi"ter51F6 Program Cou"ter51F6 60. What is Microco,tro&&!r a,4 Microco1 %t!r Microco"troller is a de ice t!at i"cludes microprocessorG memor# a"d I4O sig"al li"es o" a si"gle c!ip, $abricated usi"g +2SI tec!"olog#% Microcomputer is a computer t!at is desig"ed usi"g microprocessor as its CP3% It i"cludes microprocessor, memor# a"d I4O% 65. D!*i,! F&a9s &!e $lags are used to re$lect t!e data co"ditio"s i" t!e accumulator% &!e (0() $lags are S-Sig" $lag, @-@ero $lag, AC-AuAiliar# carr# $lag, P-Parit# $lag, CDCarr# $lag 8; 8F 8) 84 83 8C 81 80 S D AC P CA 66. Ho$ 4o!s th! 1icro roc!ssor 4i**!r!,tiat! 3!t$!!, 4ata a,4 i,str%ctio, 9!e" t!e $irst m4c code o$ a" i"structio" is $etc!ed a"d decoded i" t!e

i"structio" register, t!e microprocessor recog"i/es t!e "umber o$ b#tes re-uired to $etc! t!e e"tire i"structio"% 1or eAample M+I A, 8ata, t!e seco"d b#te is al'a#s co"sidered as data% I$ t!e data b#te is omitted b# mista,e '!ate er is i" t!at memor# locatio" 'ill be co"sidered as data B t!e b#te a$ter t!e IdataJ 'ill be treated as t!e "eAt i"structio"% 6/. Co1 ar! RET a,4 POP

RET POP RE& tra"s$ers t!e co"te"ts o$ t!e top t'o locatio"s o$ t!e stac, to t!e PC POP tra"s$ers t!e co"te"ts o$ t!e top t'o locatio"s o$ t!e stac, to t!e speci$ied register pair 9!e" RE& is eAecuted t!e SP is i"creme"ted b# t'o 9!e" POP is eAecuted t!e SP is i"creme"ted b# t'o .as ( co"ditio"al RE&3R> i"structio"s >o co"ditio"al POP i"structio"s 67. What is ass!13&!r &!e assembler tra"slates t!e assembl# la"guage program teAt '!ic! is gi e" as i"put to t!e assembler to t!eir bi"ar# e-ui ale"ts ,"o'" as obEect code% &!e time re-uired to tra"slate t!e assembl# code to obEect code is called access time% &!e assembler c!ec,s $or s#"taA errors B displa#s t!em be$ore gi i"g t!e obEect code% 6:. What is &oa4!r

&!e loader copies t!e program i"to t!e computerKs mai" memor# at load time a"d begi"s t!e program eAecutio" at eAecutio" time%

6-. What is &i,)!r A li",er is a program used to Eoi" toget!er se eral obEect $iles i"to o"e large obEect $ile% 1or large programs it is more e$$icie"t to di ide t!e large program modules i"to smaller modules% Eac! module is i"di iduall# 'ritte", tested B debugged% 9!e" all t!e modules 'or, t!e# are li",ed toget!er to $orm a large $u"ctio"i"g program% 6<. E= &ai, ALIGN ( ASSUME &!e A2IL> directi e $orces t!e assembler to alig" t!e "eAt segme"t at a" address di isible b# speci$ied di isor% &!e $ormat is A2IL> "umber '!ere "umber ca" be C, 4, ( or 1F% EAample A2IL> (% &!e ASS3ME directi e assig"s a logical segme"t to a p!#sical segme"t at a"# gi e"

time% It tells t!e assembler '!at address 'ill be i" t!e segme"t registers at eAecutio" time% EAample ASS3ME CS0 code, 8S0 data, SS0 stac, /.. E= &ai, PTR ( GROUP A program ma# co"tai" se eral segme"ts o$ t!e same t#pe% &!e LRO3P directi e collects t!em u"der a si"gle "ame so t!e# ca" reside i" a si"gle segme"t, usuall# a data segme"t% &!e $ormat is >ame LRO3P Seg-"ame,M%%Seg-"ame P&R is used to assig" a speci$ic t#pe to a ariable or a label% It is also used to o erride t!e declared t#pe o$ a ariable% /1. E= &ai, a3o%t MODEL &!is directi e pro ides s!ort cuts i" de$i"i"g segme"ts% It i"itiali/es memor# model be$ore de$i"i"g a"# segme"t% &!e memor# model ca" be SMA22, ME8I3M, COMPAC& or 2ARLE% Mo4!& Co4! s!91!,ts Data s!91!,ts Small O"e O"e Medium Multiple O"e Compact O"e Multiple 2arge Multiple Multiple /0. E= &ai, PROC ( ENDP PROC directi e de$i"es t!e procedures i" t!e program% &!e procedure "ame must be u"i-ue% A$ter PROC t!e term >EAR or 1AR are used to speci$# t!e t#pe o$ procedure% EAample 1AC& PROC 1AR% E>8P is used alo"g 'it! PROC a"d de$i"es t!e e"d o$ t!e procedure% /5. E= &ai, SEGMENT ( ENDS A" assembl# program i" %E=E $ormat co"sists o$ o"e or more segme"ts% &!e starts o$ t!ese segme"ts are de$i"ed b# SELME>& a"d t!e e"d o$ t!e segme"t is i"dicated b# E>8S directi e% 1ormat >ame SELME>& >ame E>8S /6. E= &ai, TITLE ( TAPE &!e &I&2E directi e !elps to co"trol t!e $ormat o$ a listi"g o$ a" assembled program% It causes a title $or t!e program to pri"t o" li"e C o$ eac! page o$ t!e program listi"g% MaAimum F0 c!aracters are allo'ed% 1ormat &I&2E teAt% &DPE operator tells t!e assembler to determi"e t!e t#pe o$ speci$ied ariable i" b#tes% 1or b#tes t!e assembler gi es a alue 1, $or 'ord C B double 'ord 4% //. D!*i,! SOP &!e segme"t o erride pre$iA allo's t!e programmer to de iate $rom t!e de$ault segme"t Eg 0 MO+ CS 0 N7=O , A2

/7. D!*i,! #aria3&! A ariable is a" ide"ti$ier t!at is associated 'it! t!e $irst b#te o$ data item% I" assembl# la"guage stateme"t0 CO3>& 87 C0., CO3>& is t!e ariable% /:. What ar! roc!4%r!s Procedures are a group o$ i"structio"s stored as a separate program i" memor# a"d it is called $rom t!e mai" program '!e"e er re-uired% &!e t#pe o$ procedure depe"ds o" '!ere t!e procedures are stored i" memor#% I$ it is i" t!e same code segme"t as t!at o$ t!e mai" program t!e" it is a "ear procedure ot!er'ise it is a $ar procedure% /-. E= &ai, th! &i,)i,9 roc!ss A li",er is a program used to Eoi" toget!er se eral obEect $iles i"to o"e large obEect $ile% &!e li",er produces a li", $ile '!ic! co"tai"s t!e bi"ar# codes $or all t!e combi"ed modules% It also produces a li", map '!ic! co"tai"s t!e address i"$ormatio" about t!e li", $iles% &!e li",er does "ot assig" absolute addresses but o"l# relati e address starti"g $rom /ero, so t!e programs are relocatable B ca" be put a"#'!ere i" memor# to be ru"% /<. E= &ai, a3o%t assi,9 ara1!t!rs %si,9 r!9ist!rs $ith !=a1 &! Procedures process some data or address ariable $rom t!e mai" program, $or processi"g it is "ecessar# to pass t!e address ariables or data% &!is is called passi"g parameters to procedures% I" passi"g parameters usi"g registers t!e data to be passed is stored i" registers B t!ese registers are accessed i" t!e procedure to process t!e data% CO8E SELME>& MO+ A2, 8A&A CA22 PRO1 PRO1 PROC >EAR MO+ I>P3&, A2 RE& PRO1 E>8P CO8E E>8S 7.. What is r!c%rsi#! roc!4%r!s A recursi e procedure is a procedure, '!ic! calls itsel$% Recursi e procedures are used to 'or, 'it! compleA data structures called trees% I$ t!e procedure is called 'it! >:3, t!e" t!e > is decreme"ted b# 1 a$ter eac! procedure CA22 a"d t!e procedure is called u"til >:0% 71. What ar! &i3rari!s 2ibrar# $iles are collectio" o$ procedures t!at ca" be used i" ot!er programs% &!ese

procedures are assembled a"d compiled i"to a librar# $ile b# t!e 2I7 program% &!e librar# $ile is i" o,ed '!e" a program is li",ed 'it! li",er program% '!e" a librar# $ile is li",ed o"l# t!e re-uired procedures are copied i"to t!e program% 3se o$ librar# $iles i"crease s4' reusabilit# B reduce s4' de elopme"t time% 70. What ar! Macros Macro is a group o$ i"structio"% &!e macro assembler ge"erates t!e code i" t!e program eac! time '!ere t!e macro is called% Macros are de$i"ed b# MACRO B E>8M directi es% Creati"g macro is similar to creati"g "e' opcodes t!at ca" be used i" t!e program I>I& MACRO MO+ A=, data MO+ 8S MO+ ES, A= E>8M 75. Ho$ 4o -.-7 i,t!rr% ts occ%r A" (0(F i"terrupt ca" come $rom a"# o$ t!e $ollo'i"g t!ree sources EAter"al sig"als Special i"structio"s i" t!e program Co"ditio" produced b# i"structio" 76. What ar! th! -.-7 i,t!rr% t t' !s 8edicated i"terrupts &#pe 00 8i ide b# /ero i"terrupt &#pe 10 Si"gle step i"terrupt &#pe C0>o" mas,able i"terrupt &#pe 30 7rea,poi"t &#pe 40 O er$lo' i"terrupt So$t'are i"terrupts &#pe 0-C)) 7/. What is i,t!rr% t s!r#ic! ro%ti,! I"terrupt mea"s to brea, t!e se-ue"ce o$ operatio"% 9!ile t!e CP3 is eAecuti"g a program a" i"terrupt brea,s t!e "ormal se-ue"ce o$ eAecutio" o$ i"structio"s B di erts its eAecutio" to some ot!er program% &!is program to '!ic! t!e co"trol is tra"s$erred is called t!e i"terrupt ser ice routi"e% 77. D!*i,! @IOS &!e I7M PC !as i" its ROM a collectio" o$ routi"es, eac! o$ '!ic! per$orms some speci$ic $u"ctio" suc! as readi"g a c!aracter $rom ,e#board, 'riti"g c!aracter to CR&% &!is collectio" o$ routi"es is re$erred to as 7asic I"put Output S#stem or 7IOS% 7:. E= &ai, PU@LIC

1or large programs se eral small modules are li",ed toget!er% I" order t!at t!e modules li", toget!er correctl# a"# ariable "ame or label re$erred to i" ot!er modules must be declared public i" t!e module '!ere it is de$i"ed% &!e P372IC directi e is used to tell t!e assembler t!at a speci$ied "ame or label 'ill be accessed $rom ot!er modules% 1ormat P372IC S#mbol% 7-. E= &ai, DUP &!e 83P directi e ca" be used to i"itiali/e se eral locatio"s B to assig" alues to t!ese locatio"s% 1ormat >ame 8ataP&#pe >um 83P 5 alue6 EAample &A72E 89 10 83P 506% Reser es a" arra# o$ 10 'ords o$ memor# a"d i"itiali/es all 10 'ords 'it! 0% arra# "ame is &A72E% 7<. Co1 ar! Proc!4%r! ( Macro Proc!4%r! Macro Accessed b# CA22 B RE& i"structio" Accessed duri"g assembl# 'it! "ame gi e" duri"g program eAecutio" to macro '!e" de$i"ed Mac!i"e code $or i"structio" is put o"l# o"ce i" t!e memor# Mac!i"e code is ge"erated $or i"structio" eac! time '!e" macro is called 9it! procedures less memor# is re-uired 9it! macro more memor# is re-uired Parameters ca" be passed i" registers, memor# locatio"s or stac, Parameters passed as part o$ stateme"t '!ic! calls macro

:.. What is th! %r os! o* s!91!,t r!9ist!rs i, -.-7" &!ere are 4 segme"t registers prese"t i" (0(F% &!e# are 1% Code Segme"t 5CS 6 register C% 8ata Segme"t 5DS E register 3% Stac, Segme"t 5SS 6 register 4% EAtra Segme"t 5ES 6 register &!e co4! s!91!,t register gi es t!e address o$ t!e curre"t code segme"t% ie% It 'ill poi"ts out '!ere t!e i"structio"s, to be eAecuted, are stored i" t!e memor#% &!e 4ata s!91!,t register poi"ts out '!ere t!e opera"ds are stored i" t!e memor#% &!e stac) s!91!,t registers poi"ts out t!e address o$ t!e curre"t stac,, '!ic! is used to store t!e temporar# results%

I$ t!e amou"t o$ data used is more t!e E=tra s!91!,t register poi"ts out '!ere t!e large amou"t o$ data is stored i" t!e memor#% :1. D!*i,! i !&i,i,9" I" (0(F, to speedup t!e eAecutio" o$ program, t!e i"structio"s $etc!i"g a"d eAecutio" o$ i"structio"s are o erlapped eac! ot!er% &!is tec!"i-ue is ,"o'" as pipeli"i"g% I" pipeli"i"g, '!e" t!e " t! i"structio" is eAecuted, t!e "*1 t! i"structio" is $etc!ed a"d t!us t!e processi"g speed is i"creased% :0. Disc%ss th! *%,ctio, o* i,str%ctio, +%!%! i, -.-7" I" (0(F, a F-b#te i"structio" -ueue is prese"ted at t!e 7us I"ter$ace 3"it 57I36% It is used to pre$etc! a"d store at t!e maAimum o$ F b#tes o$ i"structio" code $rom t!e memor#% 8ue to t!is, o erlappi"g i"structio" $etc! 'it! i"structio" eAecutio" i"creases t!e processi"g speed% :5. What is th! 1a=i1%1 1!1or' siB! that ca, 3! a44r!ss!4 3' -.-7" I" (0(F, a" memor# locatio" is addressed b# C0 bit address a"d t!e address bus is C0 bit address a"d t!e address bus is C0 bits% So it ca" address up to o"e mega b#te 5CQC06 o$ memor# space% :6. What is th! *%,ctio, o* th! si9,a& i, -.-7" 7.E sig"al mea"s 7us .ig! E"able sig"al% &!e 7.E sig"al is made lo' '!e" t!ere is some read or 'rite operatio" is carried out% ie % 9!e" e er t!e data bus o$ t!e s#stem is bus# i%e% '!e"e er t!ere is some data tra"s$er t!e" t!e 7.E sig"al is made lo'% :/.What ar! th! r!4!*i,!4 i,t!rr% ts i, -.-7" &!e arious prede$i"ed i"terrupts are, 8I+ISIO> 7D @ERO 5t#pe 06 I"terrupt% SI>L2E S&EP 5t#pe 16 I"terrupt% >O>MASRA72E 5t#peC6 I"terrupt% 7REAR POI>& 5t#pe 36 I"terrupt% O+ER 12O9 5t#pe 46 I"terrupt% :7. What ar! th! 4i**!r!,t *&a9 a#ai&a3&! i, stat%s r!9ist!r o* -.-7" &!ere are F o"e bit $lags are prese"t% &!e# are, A1 - AuAiliar# Carr# 1lag

C1 - Carr# 1lag O1 - O er$lo' 1lag S1 - Sig" 1lag P1 - Parit# 1lag @1 - @ero 1lag ::. List th! #ario%s a44r!ssi,9 1o4!s r!s!,t i, -.-7" &!ere are 1C addressi"g modes prese"t i" (0(F% &!e# are, 5a6 Register a"d immediate addressi"g modes P Register addressi"g modes P Immediate addressi"g mode 5b6 Memor# addressi"g modes% P 8irect addressi"g modes P Register i"direct addressi"g modes P 7ased addressi"g modes P I"deAed addressi"g modes P 7ased I"deAed addressi"g modes P Stri"g addressi"g modes 5c6 I4O addressi"g modes P 8irect addressi"g mode P I"direct addressi"g mode 5d6 Relati e addressi"g mode 5e6 Implied addressi"g mode :-. Ho$ si,9&! st! i,9 ca, 3! 4o,! i, -.-7" 7# setti"g t!e &race 1lag 5&16 t!e (0(F goes to si"gle-step mode% I" t!is mode, a$ter t!e eAecutio" o$ eac! i"structio" s (0(F ge"erates a" i"ter"al i"terrupt a"d b# 'riti"g some i"terrupt ser ice routi"e 'e ca" displa# t!e co"te"t o$ desired registers a"d memor# locatio"s% So it is use$ul $or debuggi"g t!e program% :<. Stat! th! si9,i*ica,c! o* LOCK si9,a& i, -.-7" I$ (0(F is 'or,i"g at maAimum mode, t!ere are multiprocessors are prese"t% I$ t!e s#stem bus is gi e" to a processor t!e" t!e 2OCR sig"al is made lo'% &!at mea"s t!e s#stem bus is bus# a"d it ca""ot be gi e" o$ a"# ot!er processors% A$ter t!e use o$ t!e s#stem bus agai" t!e 2OCR sig"al is made !ig!% &!at mea"s it is read# to gi e t!e s#stem bus to a"# processor% -.. What ar! th! *%,ctio,s o* 3%s i,t!r*ac! %,it F@IUE i, -.-7" 5a6 1etc! i"structio"s $rom memor#% 5b6 1etc! data $rom memor# a"d I4O ports% 5c6 9rite data to memor# a"d I4O ports% 5d6 &o commu"icate 'it! outside 'orld% 5e6 Pro ide eAter"al bus operatio"s a"d bus co"trol sig"als% -1. What is th! c&oc) *r!+%!,c' o* -.-7"

-.-7 -.-720 -.-726 I"ter"al cloc, 1re-ue"c# ) M./ (M./ 4M./ EAter"al Cloc, 1re-ue"c# 1)M.@ C4M.@ 1CM.@ -0. What ar! th! t$o 1o4!s o* o !ratio,s r!s!,t i, -.-7" i% Mi"imum mode 5or6 3"iprocessor s#stem ii% MaAimum mode 5or6 Multiprocessor s#stem

-6. E= &ai, th! roc!ss co,tro& i,str%ctio,s S&C < It sets t!e carr# $lag B does "ot a$$ect a"# ot!er $lag C2C < it resets t!e carr# $lag to /ero Bdoes "ot a$$ect a"# ot!er $lag CMC < It compleme"ts t!e carr# $lag B does "ot a$$ect a"# ot!er $lag S&8 < It sets t!e directio" $lag to 1 so t!at SI a"d4or 8I ca" be decreme"ted automaticall# a$ter eAecutio" o$ stri"g i"structio" B does "ot a$$ect ot!er $lags C28 < It resets t!e directio" $lag to 0 so t!at SI a"d4or 8I ca" be i"creme"ted automaticall# a$ter eAecutio" o$ stri"g i"structio" B does "ot a$$ect ot!er $lags S&I < Sets t!e i"terrupt $lag to 1% E"ables I>&R o$ (0(F% C2I < Resets t!e i"terrupt $lagto0% (0(F 'ill "ot respo"d to I>&R% -/. E= &ai, REPEAT2UNTIL stat!1!,ts REPEA&-3>&I2 stateme"ts allo' eAecuti"g a series o$ i"structio"s repeatedl# u"til some co"ditio" occurs% &!e REPEA& de$i"es t!e start o$ t!e loop B 3>&I2 t!e e"d o$ t!e loop% 3>&I2 !as a co"ditio" '!e" t!e co"ditio" is true t!e loop is termi"ated

-7. What is 1%&ti ro9ra11i,9S I$ more t!a" o"e process is carried out at t!e same time, t!e" it is ,"o' as multiprogrammi"g% A"ot!er de$i"itio" is t!e i"terlea i"g o$ CP3 a"d I4O operatio"s amo"g se eral programs is called multiprogrammi"g% &o impro e t!e utili/atio" o$ CP3 a"d I4O de ices, 'e are desig"i"g to process a set o$ i"depe"de"t programs co"curre"tl# b# a si"gle CP3% &!is tec!"i-ue is ,"o'" as multiprogrammi"g -:. Di**!r!,tiat! 3!t$!!, a3so&%t! a,4 &i,!ar s!&!ct 4!co4i,9" A3so&%t! 4!co4i,9 Li,!ar 4!co4i,9 All !ig!er address li"es are de$i"ed to select t!e memor# or I4O de ice 1e' !ig!er address li"es are decoded to select t!e memor# or I4O de ice More !4' is re-uired to desig" decodi"g logic .ard'are re-uired to desig" decodi"g logic is less .ig!er cost $or decodi"g circuit 2ess cost $or decodi"g circuit >o multiple address .as a disad a"tage o$ multiple

addressi"g 3sed i" large s#stems 3sed i" small s#stems --. What ar! th! thr!! c&assi*icatio,s o* -.-7 i,t!rr% ts" 516 Prede$i"ed i"terrupts 5C6 3ser de$i"ed .ard'are i"terrupts 536 3ser de$i"ed so$t'are i"terrupts% -<. What ar! th! *%,ctio,s o* stat%s i,s i, -.-7" SC S1 S0 0 0 0 ---- I"terrupt ac,"o'ledge 0 0 1 ---- Read I4O 0 1 0 ---- 9rite I4O 0 1 1 ---- .alt 1 0 0 ---- Code access 1 0 1 ---- Read memor# 1 1 0 ---- 9rite memor# 1 1 1 ---- i"acti e S4 S3 0 0 --I4O $rom eAtra segme"t 0 1 --I4O $rom Stac, Segme"t 1 0 --I4O $rom Code segme"t 1 1 --I4O $rom 8ata segme"t S) --Status o$ i"terrupt e"able $lag SF --.old ac,"o'ledge $or s#stem bus S; --Address tra"s$er% <.. What ar! th! sch!1!s *or !sta3&ishi,9 riorit' i, or4!r to r!so&#! 3%s ar3itratio, ro3&!1"
&!ere are t!ree basic bus access co"trol a"d arbitratio" sc!emes 1% 8ais# C!ai"i"g C% I"depe"de"t Re-uest 3% Polli"g

<1. What is th! %s! o* -0/1 chi " I"telKs (C)1A is a u"i ersal s#"c!ro"ous as#"c!ro"ous recei er a"d tra"smitter compatible 'it! I"telKs Processors% &!is ma# be programmed to operate i" a"# o$ t!e serial commu"icatio" modes built i"to it% &!is c!ip co" erts t!e parallel data i"to a serial stream o$ bits suitable $or serial tra"smissio"% It is also able to recei e a serial stream o$ bits a"d co" erts it i"to parallel data b#tes to be read b# a microprocessor%
<0.What ar! th! 4i**!r!,t t' !s o* 1!tho4s %s!4 *or 4ata tra,s1issio," &!e data tra"smissio" bet'ee" t'o poi"ts i" ol es u"idirectio"al or

bi-directio"al tra"smissio" o$ mea"i"g$ul digital data t!roug! a medium% &!ere are basicall# t!ere modes o$ data tra"smissio" 5a6 SimpleA 5b6 8upleA 5c6 .al$ 8upleA I" simpleA mode, data is tra"smitted o"l# i" o"e directio" o er a si"gle commu"icatio" c!a""el%1or eAample, a computer 5CP36 ma# tra"smit data $or a CR& displa# u"it i" t!is mode% I" dupleA mode, data ma# be tra"s$erred bet'ee" t'o tra"srecei ers i" bot! directio"s simulta"eousl#% I" !al$ dupleA mode, o" t!e ot!er !a"d, data tra"smissio" ma# ta,e pace i" eit!er directio", but at a time data ma# be tra"smitted o"l# i" o"e directio"% 1or eAample, a computer ma# commu"icate 'it! a termi"al i" t!is mode% 9!e" t!e termi"al se"ds data 5i%e% termi"al is se"der6% &!e message is recei ed b# t!e computer 5i%e t!e computer is recei er6% .o'e er, it is "ot possible to tra"smit data $rom t!e computer to termi"al a"d $rom termi"al to t!e computer simulta"eousl#%

<5.What ar! th! #ario%s ro9ra11!4 4ata tra,s*!r 1!tho4s" ii6 S#"c!ro"ous data tra"s$er iii6 As#"c!ro"ous data tra"s$er i 6 I"terrupt dri e" data tra"s$er <6. What is s',chro,o%s 4ata tra,s*!r" It is a data met!od '!ic! is used '!e" t!e I4O de ice a"d t!e microprocessor matc! i" speed% &o tra"s$er a data to or $rom t!e de ice, t!e user program issues a suitable i"structio" addressi"g t!e de ice% &!e data tra"s$er is completed at t!e e"d o$ t!e eAecutio" o$ t!is i"structio"% </. What is as',chro,o%s 4ata tra,s*!r" It is a data tra"s$er met!od '!ic! is used '!e" t!e speed o$ a" I4O de ice does "ot matc! 'it! t!e speed o$ t!e microprocessor% As#"c!ro"ous data tra"s$er is also called as .a"ds!a,i"g%
<7. What ar! th! *%,ctio,a& t' !s %s!4 i, co,tro& $or4s o* -0/1aS &!e co"trol 'ords o$ (C)1A are di ided i"to t'o $u"ctio"al t#pes% 1% Mode I"structio" co"trol 'ord C% Comma"d I"structio" co"trol 'ord Mode I"structio" co"trol 'ord 0-&!is de$i"es t!e ge"eral operatio"al

c!aracteristics o$ (C)1A% Comma"d I"structio" co"trol 'ord0-&!e comma"d i"structio" co"trols t!e actual operatio"s o$ t!e selected $ormat li,e e"able tra"smit4recei e, error reset a"d modem co"trol% <:. What ar! th! 3asic 1o4!s o* o !ratio, o* -0//" &!ere are t'o basic modes o$ operatio" o$ (C)), i/% 1% I4O mode% 3% 7SR mode% I" I4O mode, t!e (C)) ports 'or, as programmable I4O ports, '!ile I" 7SR mode o"l# port C 5PC0-PC;6 ca" be used to set or reset its i"di idual port bits% 3"der t!e IO mode o$ operatio", $urt!er t!ere are t!ree modes o$ operatio" o$ ( C)), So as to support di$$ere"t t#pes o$ applicatio"s, i/% mode 0, mode 1 a"d mode C% Mode 0 - 7asic I4O mode Mode 1 - Strobed I4O mode Mode C - Strobed bi-directio"al I4O <-. Writ! th! *!at%r!s o* 1o4! . i, -0//" 1% &'o (-bit ports 5port A a"d port 76 a"d t'o 4-bit ports 5port C upper a"d lo'er6 are a ailable% &!e t'o 4-bit ports ca" be combi"ed used as a t!ird (-bit port% C% A"# port ca" be used as a" i"put or output port% 3%Output ports are latc!ed% I"put ports are "ot latc!ed% 4% A maAimum o$ $our ports are a ailable so t!at o erall 1F I4O co"$iguratio"s are possible% <<. What ar! th! *!at%r!s %s!4 1o4! 1 i, -0//" &'o groups < group A a"d group 7 are a ailable $or strobed data tra"s$er% 1% Eac! group co"tai"s o"e (-bit data I4O port a"d o"e 4-bit co"trol4data port% C% &!e (-bit data port ca" be eit!er used as i"put or output port% &!e i"puts a"d outputs bot! are latc!ed% 3% Out o$ (-bit port C, PC0-PCC is used to ge"erate co"trol sig"als $or port 7 a"d PC3:PC) are used to ge"erate co"trol sig"als $or port A% &!e li"es PCF, PC; ma# be used as i"depe"de"t data li"es% 1... What ar! th! si9,a&s %s!4 i, i, %t co,tro& si9,a& ( o%t %t co,tro& si9,a&" I"put co"trol sig"al S&7 5Strobe i"put6 I71 5I"put bu$$er $ull6 I>&R5I"terrupt re-uest6 Output co"trol sig"al O71 5Output bu$$er $ull6 ACR 5Ac,"o'ledge i"put6 I>&R5I"terrupt re-uest6 1.1. What ar! th! *!at%r!s %s!4 1o4! 0 i, -0//" &!e si"gle (-bit port i"-group A is a ailable%

1% &!e (-bit port is bi-directio"al a"d additio"all# a )-bit co"trol port is a ailable% C% &!ree I4O li"es are a ailable at port C, i/ PCC-PC0% 3% I"puts a"d outputs are bot! latc!ed% 4% &!e )-bit co"trol port C 5PC3:PC;6 is used $or ge"erati"g4accepti"g !a"ds!a,e sig"als $or t!e (-bit data tra"s$er o" port A% 1.0. What ar! th! 1o4!s o* o !ratio,s %s!4 i, -0/5"

Eac! o$ t!e t!ree cou"ters o$ (C)3 ca" be operated i" o"e o$ t!e $ollo'i"g siA modes o$ operatio"% 1% Mode 0 5I"terrupt o" termi"al cou"t6 C% Mode 1 5Programmable mo"os!ot6 3% Mode C 5Rate ge"erator6 4% Mode 3 5S-uare 'a e ge"erator6 )% Mode 4 5So$t'are triggered strobe6 F% Mode ) 5.ard'are triggered strobe6 1.5. What ar! th! 4i**!r!,t t' !s o* $rit! o !ratio,s %s!4 i, -0/5" &!ere are t'o t#pes o$ 'rite operatio"s i" (C)3 516 9riti"g a co"trol 'ord register 5C6 9riti"g a cou"t alue i"to a cou"t register &!e co"trol 'ord register accepts data $rom t!e data bu$$er a"d i"itiali/es t!e cou"ters, as re-uired% &!e co"trol 'ord register co"te"ts are used $or 5a6 I"itiali/i"g t!e operati"g modes 5mode 0-mode46 5b6 Selectio" o$ cou"ters 5cou"ter 0- cou"ter C6 5c6 C!oosi"g bi"ar# 47C8 cou"ters 5d6 2oadi"g o$ t!e cou"ter registers% &!e mode co"trol register is a 'rite o"l# register a"d t!e CP3 ca""ot read its co"te"ts% 1.6. Gi#! th! 4i**!r!,t t' !s o* co11a,4 $or4s %s!4 i, -0/<a" &!e comma"d 'ords o$ (C)HA are classi$ied i" t'o groups 1% I"itiali/atio" comma"d 'ords 5IC9s6 C% Operatio" comma"d 'ords 5OC9s6 1./. Gi#! th! o !rati,9 1o4!s o* -0/<a" 5a6 1ull# >ested Mode 5b6 E"d o$ I"terrupt 5EOI6 5c6 Automatic Rotatio" 5d6 Automatic EOI Mode 5e6 Speci$ic Rotatio" 5$6 Special Mas, Mode 5g6 Edge a"d le el &riggered Mode

5!6 Readi"g (C)H Status 5i6 Poll comma"d 5E6 Special 1ull# >ested Mode 5,6 7u$$ered mode 5l6 Cascade mode 1.7. D!*i,! sca, co%,t!r" &!e sca" cou"ter !as t'o modes to sca" t!e ,e# matriA a"d re$res! t!e displa#% I" t!e e"coded mode, t!e cou"ter pro ides bi"ar# cou"t t!at is to be eAter"all# decoded to pro ide t!e sca" li"es $or ,e#board a"d displa#% I" t!e decoded sca" mode, t!e cou"ter i"ter"all# decodes t!e least sig"i$ica"t C bits a"d pro ides a decoded 1 out o$ 4 sca" o" S20-S23%&!e ,e#board a"d displa# bot! are i" t!e same mode at a time% 1.:. What is th! o%t %t 1o4!s %s!4 i, -0:<" (C;H pro ides t'o output modes $or selecti"g t!e displa# optio"s% 1.Dis &a' Sca, I" t!is mode, (C;H pro ides ( or 1F c!aracter-multipleAed displa#s t!ose ca" be orga"i/ed as dual 4-bit or si"gle (-bit displa# u"its% 0.Dis &a' E,tr' (C;H allo's optio"s $or data e"tr# o" t!e displa#s% &!e displa# data is e"tered $or displa# $rom t!e rig!t side or $rom t!e le$t side% 1.-. What ar! th! 1o4!s %s!4 i, )!'3oar4 1o4!s" 1% Sca""ed Re#board mode 'it! C Re# 2oc,out% C% Sca""ed Re#board 'it! >-,e# Rollo er% 3% Sca""ed Re#board special Error Mode% 4% Se"sor MatriA Mode% 1.<. What ar! th! 1o4!s %s!4 i, 4is &a' 1o4!s" 1. L!*t E,tr' 1o4! I" t!e le$t e"tr# mode, t!e data is e"tered $rom t!e le$t side o$ t!e displa# u"it%% 0. Ri9ht E,tr' Mo4! I" t!e rig!t e"tr# mode, t!e $irst e"tr# to be displa#ed is e"tered o" t!e rig!tmost displa#% 11.. What is th! %s! o* 1o4!1 co,tro& %,it i, -0/1" &!e modem co"trol u"it !a"dles t!e modem !a"ds!a,e sig"als to coordi"ate t!e commu"icatio" bet'ee" t!e modem a"d t!e 3SAR&% 111. Gi#! th! r!9ist!r or9a,iBatio, o* -0/:"

&!e (C); per$orm t!e 8MA operatio" o er $our i"depe"de"t 8MA c!a""els% Eac! o$ t!e $our c!a""els o$ (C); !as a pair o$ t'o 1F-bit registers% 8MA address register a"d termi"al cou"t register% Also, t!ere are t'o commo" registers $or all t!e c!a""elsG "amel#, mode set registers a"d status register% &!us t!ere are a total o$ te" registers% &!e CP3 selects o"e o$ t!ese te" registers usi"g address li"es A0A3% 110. What is th! *%,ctio, o* DMA a44r!ss r!9ist!r" Eac! 8MA c!a""el !as o"e 8MA address register% &!e $u"ctio" o$ t!is register is to store t!e address o$ t!e starti"g memor# locatio", '!ic! 'ill be accessed b# t!e 8MA c!a""el% &!us t!e starti"g address o$ t!e memor# bloc, t!at 'ill be accessed b# t!e de ice is $irst loaded i" t!e 8MA address register o$ t!e c!a""el% >aturall#, t!e de ice t!at 'a"ts to tra"s$er data o er a 8MA c!a""el, 'ill access t!e bloc, o$ memor# 'it! t!e starti"g address stored i" t!e 8MA Address Register% 115. What is th! %s! o* t!r1i,a& co%,t r!9ist!r" Eac! o$ t!e $our 8MA c!a""els o$ (C); !as o"e termi"al cou"t register% &!is 1F-bit register is used $or ascertai"i"g t!at t!e data tra"s$er t!roug! a 8MA c!a""el ceases or stops a$ter t!e re-uired "umber o$ 8MA c#cles% 116. What is th! *%,ctio, o* 1o4! s!t r!9ist!r i, -0/:" &!e mode set register is used $or programmi"g t!e (C); as per t!e re-uireme"ts o$ t!e s#stem% &!e $u"ctio" o$ t!e mode set register is to e"able t!e 8MA c!a""els i"di iduall# a"d also to set t!e arious modes o$ operatio"% 11/. Disti,9%ish 3!t$!!, th! 1!1ori!s 1a !4 I;O !ri h!ra& I;O" S20 >O M!1or' Ma !4 I;O P!ri h!ra& I;O 1 1F-bit de ice address (-bit de ice address C 8ata tra"s$er bet'ee" a"# ge"eral-purpose register a"d I4O port% 8ata is tra"s$er o"l# bet'ee"

accumulator a"d I%O port 3 &!e memor# map 5F4R6 is s!ared bet'ee" I4O de ice a"d s#stem memor#% &!e I4O map is i"depe"de"t o$ t!e memor# mapG C)F i"put de ice a"d C)F output de ice ca" be co""ected 4 More !ard'are is re-uired to decode 1F-bit address 2ess !ard'are is re-uired to decode (-bit address ) Arit!metic or logic operatio" ca" be directl# per$ormed 'it! I4O data Arit!metic or logical operatio" ca""ot be directl# per$ormed 'it! I4O data 117. List th! o !ratio, 1o4!s o* -0// a6 I%O Mode i% Mode 0-Simple I"put4Output% ii% Mode 1-Strobed I"put4Output 5.a"ds!a,e mode6 iii% Mode C-Strobed bidirectio"al mode b6 7it Set4Reset Mode% 11;% What is a co,tro& $or4" It is a 'ord stored i" a register 5co"trol register6 used to co"trol t!e operatio" o$ a program digital de ice% 11(% What is th! %r os! o* co,tro& $or4 $ritt!, to co,tro& r!9ist!r i, -0//" &!e co"trol 'ords 'ritte" to co"trol register speci$# a" I4O $u"ctio" $or eac! I%O port% &!e bit 8; o$ t!e co"trol 'ord determi"es eit!er t!e I4O $u"ctio" o$ t!e 7SR $u"ctio"% 11<.What is th! siB! o* orts i, -0//" Port-A 0 (-bits Port-7 0 (-bits Port-C3 0 4-bits Port-C2 0 4-bits 10.. What is i,t!r*aci,9" A" i"ter$ace is a s!ared bou"dar# bet'ee" t!e de ices '!ic! i" ol es s!ari"g

i"$ormatio"% I"ter$aci"g is t!e process o$ ma,i"g t'o di$$ere"t s#stems commu"icate 'it! eac! ot!er% 101. What is 1!1or' 1a i,9" &!e assig"me"t o$ memor# addresses to arious registers i" a memor# c!ip is called as memor# mappi"g% 100. What is I;O 1a i,9" &!e assig"me"t o$ addresses to arious I4O de ices i" t!e memor# c!ip is called as I4O mappi"g% 105. What is a, USART" 3SAR& sta"ds $or u"i ersal s#"c!ro"ous4As#"c!ro"ous Recei er4 &ra"smitter% It is a programmable commu"icatio" i"ter$ace t!at ca" commu"icate b# usi"g eit!er s#"c!ro"ous or as#"c!ro"ous serial data% 105.What is th! %s! o* -0/1 chi " (C)1 c!ip is mai"l# used as t!e as#"c!ro"ous serial i"ter$ace bet'ee" t!e processor a"d t!e eAter"al e-uipme"t% 10/. Th! -0:< is a ro9ra11a3&! ?????????? i,t!r*ac!. Re#board48ispla# 107. List th! 1aGor co1 o,!,ts o* th! )!'3oar4;Dis &a' i,t!r*ac!. a% Re#board sectio" b% Sca" sectio" c% 8ispla# sectio" d% CP3 i"ter$ace sectio" 10:. What is K!' 3o%,ci,9" Mec!a"ical s'itc!es are used as ,e#s i" most o$ t!e ,e#boards% 9!e" a ,e# is pressed t!e co"tact bou"ce bac, a"d $ort! a"d settle do'" o"l# a$ter a small time dela# 5about C0ms6% E e" t!oug! a ,e# is actuated o"ce, it 'ill appear to !a e bee" actuated se eral times% &!is problem is called Re# 7ou"ci"g% 10-.D!*i,! HRH" &!e !old re-uest output re-uests t!e access o$ t!e s#stem bus% I" "o"- cascaded (C); s#stems, t!is is co""ected 'it! .O28 pi" o$ CP3% I" cascade mode, t!is pi" o$ a sla e is co""ected 'it! a 8RT i"put li"e o$ t!e master (C);, '!ile t!at o$ t!e master is co""ected 'it! .O28 i"put o$ t!e CP3%
10<. What is th! %s! o* st! !r 1otor"

A stepper motor is a de ice used to obtai" a" accurate positio" co"trol o$

rotati"g s!a$ts% A stepper motor emplo#s rotatio" o$ its s!a$t i" terms o$ steps, rat!er t!a" co"ti"uous rotatio" as i" case o$ AC or 8C motor% 15.. What is TCD" &=8- &ra"smitter 8ata Output &!is output pi" carries serial stream o$ t!e tra"smitted data bits alo"g 'it! ot!er i"$ormatio" li,e start bit, stop bits a"d priorit# bit% 151. What is RCD" R=8- Recei e 8ata I"put &!is i"put pi" o$ (C)1A recei es a composite stream o$ t!e data to be recei ed b# (C)1A% 150. Dra$ th! stat%s $or4 *or1at *or -0/6.
O3& >322 CO3>& R91 R90 MC M1 M0 7C8

155. What is 1!a,t 3' )!' 3o%,ci,9" Microprocessor must 'ait u"til t!e ,e# reac! to a stead# stateG t!is is ,"o'" as Re# bou"ce% 156. Writ! th! *%,ctio, o* cross3ar s$itch" &!e crossbar s'itc! pro ides t!e i"ter co""ectio" pat!s bet'ee" t!e memor# module a"d t!e processor% Eac! "ode o$ t!e crossbar represe"ts a bus s'itc!% All t!ese "odes ma# be co"trolled b# o"e o$ t!ese processors or b# a separate o"e altoget!er% 15/. What is a 4ata a1 &i*i!r" &ra"scei ers are t!e bi-directio"al bu$$ers are some times t!e# are called as data ampli$iers% &!e# are re-uired to separate t!e alid data $rom t!e time multipleAed address data sig"al% &!e# are co"trolled b# C sig"als i%e 8E> B 8&4R% 157.What ar! th! 4i**!r!,t i,t!r co,,!ctio, to o&o9i!s" S!ared bus Multiport Memor# 2i",ed I"put4Output 7us 'i"do' Crossbar S'itc!i"g% 15:. What ar! th! co,*i9%ratio,s %s!4 *or h'sica& i,t!rco,,!ctio,s"

Star Co"$iguratio" 2oop co"$iguratio" Complete i"terco""ectio" Regular topologies Irregular topologies 15-. Gi#! th! i,str%ctio, s!t o* -.-:" 1% 8ata &ra"s$er I"structio"s C% Arit!metic I"structio"s 3% Compariso" I"structio"s% 4% &ra"sce"de"tal Operatio"s% )% Co"sta"t Operatio"s% F% Coprocessor Co"trol Operatio"s% 15<. Writ! th! a4#a,ta9!s o* &oos!&' co% &!4 s'st!1 o#!r ti9ht&' co% &!4 s'st!1s" 1% More "umber o$ CP3s ca" be added i" a loosel# coupled s#stem to impro e t!e s#stem per$orma"ce C% &!e s#stem structure is modular a"d !e"ce eas# to mai"tai" a"d troubles!oot% 3% A $ault i" a si"gle module does "ot lead to a complete s#stem brea,do'"% 16.. What is th! 4i**!r!,t c&oc) *r!+%!,ci!s %s!4 i, -.0-7" +arious ersio"s o$ (0C(F are a ailable t!at ru" o" 1C%)M./, 10M./ a"d (M./ cloc, $re-ue"cies% 161. D!*i,! s$a i,9 i," &!e portio" o$ a program is re-uired $or eAecutio" b# t!e CP3, it is $etc!ed $rom t!e seco"dar# memor# a"d placed i" t!e p!#sical memor#% &!is is called Us'appi"g i"K o$ t!e program% 160. What ar! th! 4i**!r!,t o !rati,9 1o4!s %s!4 i, -.0-7" &!e (0C(F 'or,s i" t'o operati"g modes 1% Real addressi"g mode C% Protected irtual address mode% 143% What ar! th! CPU co,t!,ts %s!4 i, -.0-7" &!e (0C(F CP3 co"tai"s almost t!e same set o$ registers, as i" (0(F Eig!t 1F-bit ge"eral purpose register 1our 1F-bit segme"t registers Status a"d co"trol register I"structio" poi"ter% 166. What is stat%s *&a9 3it" &!e $lag register re$lects t!e results o$ logical a"d arit!metic i"structio"s% &!e

$lag register digits 80, 8C, 84, 8F, 8; a"d 811 are modi$ied accordi"g to t!e result o$ t!e eAecutio" o$ logical a"d arit!metic i"structio"% &!ese are called as status $lag bits% 14). What is a co,tro& *&a9" &!e bits 8( a"d 8H "amel#, trap $lag 5&16 a"d i"terrupt $lag 5I16 bits, are used $or co"trolli"g mac!i"e operatio" a"d t!us t!e# are called co"trol $lags% 167. What is i,str%ctio, i !&i,i,9" MaEor $u"ctio" o$ t!e bus u"it is to $etc! i"structio" b#tes $rom t!e memor#% I" $act, t!e i"structio"s are $etc!ed i" ad a"ce a"d stored i" a -ueue to e"able $aster eAecutio" o$ t!e i"structio"s% &!is co"cept is ,"o'" as i"structio" pipeli"i"g% 16:. What is s$a i,9" &!e procedure o$ $etc!i"g t!e c!ose" program segme"ts or data $rom t!e seco"dar# storage i"to t!e p!#sical memor# is called Us'appi"gK% 16-. What is 1!a, 3' 1icroco,tro&&!r" A de ice '!ic! co"tai"s t!e microprocessor 'it! i"tegrated perip!erals li,e memor#, serial ports, parallel ports, timer4cou"ter, i"terrupt co"troller, data ac-uisitio" i"ter$aces li,e A8C,8AC is called microco"troller% 16<. E= &ai, D>ND i,str%ctio,s o* i,t!& -./1 1icroco,tro&&!r" a6 8?>@ R", rel 8ecreme"t t!e co"te"t o$ t!e register R" a"d Eump i$ "ot /ero% b6 8?>@ direct , rel 8ecreme"t t!e co"te"t o$ direct (-bit address a"d Eump i$ "ot /ero% 1/.. Stat! th! *%,ctio, o* RS1 a,4 RS. 3its i, th! *&a9 r!9ist!r o* i,t!& -./1 1icroco,tro&&!r" RS1 , RS0 < Register ba", select bits RS1 RS0 7a", Selectio" 0 0 1 1 0 1 0 1

7a", 0 7a", 1 7a", C 7a", 3 1/1. Writ! a ro9ra1 %si,9 -./1 ass!13&' &a,9%a9! to cha,9! th! 4at! //H stor!4 i, th! &o$!r 3't! o* th! 4ata oi,t!r r!9ist!r to AAH %si,9 rotat! i,str%ctio,. MO+ 8P2,V)). MO+ A, 8P2 R2 A 2abel 0S?MP label 1/0. Gi#! th! a&t!r,at! *%,ctio,s *or th! ort i,s o* ort5" R8 9R &1 & 0 I>&1 I>&0 &=8 R=8 R8 < Read data co"trol output% 9R < 9rite data co"trol output% &1 < &imer 4 Cou"ter1 eAter"al i"put or test pi"% &0 < &imer 4 Cou"ter0 eAter"al i"put or test pi"% I>&1- I"terrupt 1 i"put pi"% I>& 0 < I"terrupt 0 i"put pi"% &=8 < &ra"smit data pi" $or serial port i" 3AR& mode% R=8 - Recei e data pi" $or serial port i" 3AR& mode% 1/5. S !ci*' th! si,9&! i,str%ctio,, $hich c&!ars th! 1ost si9,i*ica,t 3it o* @ r!9ist!r o* -./1, $itho%t a**!cti,9 th! r!1ai,i,9 3its. Si"gle i"structio", '!ic! clears t!e most sig"i$ica"t bit o$ 7 register o$ (0)1, 'it!out a$$ecti"g t!e remai"i"g bits is C2R 7%;% 1)4% E= &ai, th! *%,ctio, o* th! i,s PSEN a,4 EA o* -./1% PSE>0 PSE> sta"ds $or program store e"able% I" (0)1 based s#stem i" '!ic! a" eAter"al ROM !olds t!e program code, t!is pi" is co""ected to t!e OE pi" o$ t!e ROM% EA 0EA sta"ds $or eAter"al access% 9!e" t!e EA pi" is co""ected to +cc, program $etc!ed to addresses 0000. t!roug! 0111. are directed to t!e i"ter"al ROM a"d program $etc!es to addresses 1000. t!roug! 1111. are directed to eAter"al ROM4EPROM% 9!e" t!e EA pi" is grou"ded, all addresses $etc!ed b# program are directed to t!e eAter"al ROM4EPROM%

1//. E= &ai, th! 1723it r!9ist!rs DPTR a,4 SP o* -./1. 8P&R0 8P&R sta"ds $or data poi"ter% 8P&R co"sists o$ a !ig! b#te 58P.6 a"d a lo' b#te 58P26% Its $u"ctio" is to !old a 1F-bit address% It ma# be ma"ipulated as a 1F-bit data register or as t'o i"depe"de"t (-bit registers% It ser es as a base register i" i"direct Eumps, loo,up table i"structio"s a"d eAter"al data tra"s$er% SP0 SP sta"ds $or stac, poi"ter% SP is a (- bit 'ide register% It is i"creme"ted be$ore data is stored duri"g P3S. a"d CA22 i"structio"s% &!e stac, arra# ca" reside a"#'!ere i" o"-c!ip RAM% &!e stac, poi"ter is i"itialised to 0;. a$ter a reset% &!is causes t!e stac, to begi" at locatio" 0(.% 1/7. Na1! th! s !cia& *%,ctio,s r!9ist!rs a#ai&a3&! i, -./1. Accumulator 7 Register Program Status 9ord% Stac, Poi"ter% 8ata Poi"ter% Port 0 Port 1 Port C Port 3 I"terrupt priorit# co"trol register% I"terrupt e"able co"trol register% 1);%E= &ai, th! r!9ist!r IE *or1at o* -./1% E A E & C E S E&1 E=1 E&0 E=0 EA- E"able all co"trol bit% E&C- &imer C i"terrupt e"able bit% ES < E"able serial port co"trol bit% E&1 < E"able &imer1 co"trol bit%

E=1- E"able eAter"al i"terrupt1 co"trol bit% E&0 < E"able &imer0 co"trol bit% E=0- E"able eAter"al i"terrupt0 co"trol bit% 1/-. Co1 ar! Micro roc!ssor a,4 Microco,tro&&!r. Sl%>o Microprocessor Microco"troller 1 Microprocessor co"tai"s A23,ge"eral purpose registers,stac, poi"ter, program cou"ter, cloc, timi"g circuit a"d i"terrupt circuit% Microco"troller co"tai"s t!e circuitr# o$ microprocessor a"d i" additio" it !as built- i" ROM, RAM, I4O de ices, timers a"d cou"ters% C It !as ma"# i"structio"s to mo e data bet'ee" memor# a"d CP3% It !as o"e or t'o i"structio"s to mo e data bet'ee" memor# a"d CP3% 3 It !as o"e or t'o bit !a"dli"g i"structio"s% It !as ma"# bit !a"dli"g i"structio"s% 4 Access times $or memor# a"d I4O de ices are more% 2ess access times $or built-i" memor# a"d I4O de ices% ) Microprocessor based s#stem re-uires more !ard'are% Microco"troller based s#stem re-uires less !ard'are reduci"g PC7 si/e a"d i"creasi"g t!e reliabilit#% 1/<.Na1! th! *i#! i,t!rr% t so%rc!s o* -./1". &!e i"terrupts are0 +ector address EAter"al i"terrupt 0 0 IE0 0 0003. &imer i"terrupt 0 0 &10 0 0007. EAter"al i"terrupt 1 0 IE1 0 0013. &imer I"terrupt 1 0 &11 0 0017. Serial I"terrupt Recei e i"terrupt 0 RI 0 00C3. &ra"smit i"terrupt0 &I 0 00C3. 17..E= &ai, th! co,t!,ts o* th! acc%1%&ator a*t!r th! !=!c%tio, o* th! *o&&o$i,9 ro9ra1 s!91!,ts0 MO+ A,V3C.

MO+ R4,VFF. A>2 A,R4 A 3C R4 FF A C4 171% Writ! a ro9ra1 to &oa4 acc%1%&ator A, DPH a,4 DPL $ith 5.H. MO+ A,V30 MO+ 8P.,A MO+ 8P2,A 170.Writ! a ro9ra1 to s%3tract th! co,t!,ts o* R1 o* @a,). *ro1 th! co,t!,ts o* R. o* @a,)0. MO+ PS9,V10 MO+ A,R0 MO+ PS9,V00 S377 A,R1 175. Ho$ th! RS 2050C s!ria& 3%s is i,t!r*ac!4 to 1TL &o9ic 4!#ic!" &!e RS-C3CC sig"al oltage le els are "ot compatible 'it! &&2 logic le els% .e"ce $or i"ter$aci"g &&2 de ices to RS-C3CC serial bus, le el co" erters are used% &!e popularl# used le el co" erters are MC 14(( B MC 14(H or MA= C3C% 176. List so1! o* th! *!at%r!s o* -.<7 1icroco,tro&&!r% a% &!e (0HF is a 1F-bit microco"troller% b% &!e (0HF is desig"ed to use i" applicatio"s '!ic! re-uire !ig! speed calculatio"s a"d $ast I4O operatio"s% c% &!e !ig! speed I4O sectio" o$ a" (0HF i"cludes a 1F-bit timer, a 1Fbit cou"ter, a 4 i"put programmable edge detector, 4 so$t'are timers a"d a F-output programmable e e"t ge"erator% d% It !as 100 i"structio"s, '!ic! ca" operate o" bit, b#te, 'ord, a"d double 'ords% e% &!e bit operatio"s are possible a"d t!ese ca" be per$ormed o" a"# bit i" t!e register $ile or i" t!e special $u"ctio" register% 17/. List th! *!at%r!s o* -./1 1icroco,tro&&!r" &!e $eatures are Wsi"gleP suppl# *) olt operatio" usi"g .MOS tec!"olog#% W40HF b#tes program memor# o" c!ip5"ot o" (0316 W1C( data memor# o" c!ip% W1our register ba",s% W&'o multiple mode,1F-bit timer4cou"ter% WEAte"si e 7oolea" processi"g capabilities% WF4 R7 eAter"al RAM si/e

W3C bi-directio"al i"di iduall# addressable I4O li"es% W( bit CP3 optimi/ed $or co"trol applicatio"s% 177. What is th! *%,ctio, o* NEU" &!e "umeric eAecutio" u"it eAecutes all t!e i"structio"s i"cludi"g arit!metic, logical tra"sce"de"tal, a"d data tra"s$er i"structio"s% &!e "umeric eAecutio" u"it eAecutes all t!e "umeric processor i"structio"s '!ile t!e co"trol u"it 5C36 recei es, decodes i"structio"s, reads a"d 'rites memor# opera"ds a"d eAecutes t!e (0(; co"trol i"structio"s% 17:. Gi#! th! 4isa4#a,ta9!s o* 3%s $i,4o$ t!ch,i+%!" &!e "umeric eAecutio" u"it eAecutes all t!e i"structio"s i"cludi"g arit!metic, logical tra"sce"de"tal, a"d data tra"s$er i"structio"s% &!e "umeric eAecutio" u"it eAecutes all t!e "umeric processor i"structio"s '!ile t!e co"trol u"it 5C36 recei es, decodes i"structio"s, reads a"d 'rites memor# opera"ds a"d eAecutes t!e (0(; co"trol i"structio"s% 17-. What is s$a i,9 o%t" A portio" o$ t!e program or importa"t partial results re-uired $or $urt!er eAecutio" ma# e sa ed bac, o" seco"dar# storage to ma,e t!e p!#sical memor# $ree $or $urt!er eAecutio" o$ a"ot!er re-uired portio" o$ t!e program% &!is is called Us'appi"g outK o$ t!e eAecutable program%