Advanced computer architecture (MCSE104)

Assignment-1
Q1.Classify computer architecture according to Flynn,s, Feng and Handlers classification schems. Q2.Explain shared memory multi processor and distributed memory multi computers. Q3.Define following performance factors of a system a.MIPS Rate b.Throughput Rate c.CPI Q4.Differentiate implicit parallelism and explicit parallelism. Discuss in view of degree Of parallelism. Q5..Explain the conditions for parallelism with an example. Q6.Differentiate hardware and software parallelism and explain with an example. Q7.Explain program flow mechanisms. Q8Compare Control flow, Data flow and Demand Driven computers. Q9.Analyse the data dependencies among the following statements: S1: /RDG_5_______ / R1 1024 / S2: /RDG_5___0____ / R2 Memory(10) / S3: $GG_5___5_ / R1 (R1) + (R2) / S4: 6WRUH_0________5_ / Memory(1024) (R1) / S5: 6WRUH_0__5_________ / Memory(64) 1024 / Note that (Ri) means that the content of register Ri and Memory(10) contains 64 initially. a) Draw a dependence graph to show all the dependencies. b) Are there any resource dependencies if only one copy of each functional unit is available in the CPU? Q10. Compare the PRAM models with physical models of real parallel computers in each of the following categories: a) Which PRAM variant can best model SIMD machines and how? b) Repeat the question in (a) for shared-memory MIMD machines Q11.Expalin Mesh connected ILLIAC network with an example. Q12.define the following terms for various system interconnect architectures: a.Node Degree b.Network Dimeter c.Bisection Bandwidth d.Ststic Connection network e.Dyanamic Connection network Q13Exlplain Omega Networs and Crssbar Switch.

Q14Explain different levels of parallelism during program execution.

Q15.consider the following reservation table for a four stage pipeline with a clock cycle =20ns S1 X X S2 X X S3 X S4 X X 1 what are the forbidden latencies ? 2 Draw the state transition diagram? 3 List all the simple cycles and greedy cycles? 4 Determine the optimal constant latency cycle and the minimal average latency. 5 Let the pipeline clock period be t=20ns determine the throughput of this pipeline Q16. Describe the following terminologies associated with pipeline computer (a)Static pipeline(b) Dynamic pipeline(c)instruction pipeline(d)pipeline throughput Q17.consider the following pipelined processor with four stages. All successor stages after each stage must be used in successive clock periods.

S1

S2

S3

S4

Output (a)Write out the reservation table for this pipeline. (b)List the set of forbidden latencies between task initiations. (c)show initial collision vector. designing or selecting a network topology, several performance parameters must be considered. List 6 such performance parameters.
Q.18 When

Q19

a) What are the forbidden latencies? b) Draw the state transition diagram. c) List all the simple cycles and greedy cycles? d) Determine the minimal average latency (MAL). e) Let the pipeline clock period be =20ns. Determine the throughput of this pipeline. Answer the following questions for the k-ary n-cube network: a) How many nodes are there? b) What is the network diameter? c) What is the bisection width? d) What is the node degree? e) What is the relationship between this topology and rings, meshes, torii, and hypercubes?
Q20.

Huma Gupta