FPGA design tutorial: Advanced HDL synthesis

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Advanced HDL Synthesis for FPGA

This part of the FPGA design tutorial is dedicated to the issues arising when HDL code is synthesized.

Keep FPGA architecture in mind

It is important to know FPGA capabilities in order to produce efficient FPGA designs. When writing HDL code, one should think about how it will be implemented in the particular FPGA. Failure to do this will often lead to area and performance waste. For example, consider a shift register implemented for Xilinx Virtex-4 FPGA: library ieee; use ieee.std_logic_1164.all; entity sreg is port( CLK : in std_logic; CE : in std_logic; RST: in std_logic; DIN : in std_logic; DOUT : out std_logic ); end sreg; architecture behavioral of sreg is signal tmp: std_logic_vector(7 downto 0); begin process (CLK) begin if rising_edge(CLK) then if RST='1' then tmp<="00000000"; elsif CE='1' then tmp<=tmp(6 downto 0)&DIN; end if; end if; end process; DOUT<=tmp(7); end behavioral; It is a valid shift register, but it will be implemented using a chain of 8 flip-flops (spending four Virtex-4 slices). There are cases when we don't actually need to reset a shift register. This will lead to more efficient implementation utilizing SRL16E library element (implemented on LUTs instead of slice flip-flops): library ieee; use ieee.std_logic_1164.all; entity sreg is port( CLK : in std_logic; CE : in std_logic; DIN : in std_logic; DOUT : out std_logic ); end sreg;

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FPGA design tutorial: Advanced HDL synthesis

architecture behavioral of sreg is signal tmp: std_logic_vector(7 downto 0); begin process (CLK) begin if rising_edge(CLK) then if CE='1' then tmp<=tmp(6 downto 0)&DIN; end if; end if; end process; DOUT<=tmp(7); end behavioral; This implementation will use 1 slice instead of 8. The cause of this difference is that SRL16E library element doesn't support reset.

Synthesis constraints
Synthesis constraints are used as guidelines to synthesizer, indicating how it should implement a particular module or signal. Synthesis constraints are not to be confused with implementation constraints, which guide place & route and static timing analysis. Synthesis constraints can be specified in the HDL source, or in separate constraints file. Synthesis constraints depend upon a synthesizer. Specifying synthesis constraints in VHDL source In order to declare a synthesis contraint in VHDL, an attribute must be declared and then linked to the appropriate entity or signal: attribute AttributeName : Type ; attribute AttributeName of ObjectList : ObjectType is AttributeValue ; ObjectList is a list of objects to apply a constraint. Objects that can be assigned constraints are entities, components, labels, signals, variables and types. The following code uses an XST synthesis constraint that forces a multiplier to be implemented in a dedicated DSP48 block. attribute use_dsp48 : string; attribute use_dsp48 of product : signal is "yes"; ... product <= A*B; Specifying synthesis constraints in Verilog source Before Verilog 2001 standard was introduced, Verilog language didn't have any means to specify attributes in source. Synthesis attributes were specified in the comments instead: reg [7:0] dataout[31:0] /* synthesis syn_ramstyle="block_ram" */; These attributes were placed after the signal/module in question. Verilog 2001 (which is now supported by the majority of EDA tools) introduced a syntax element for attribute: (* use_dsp48 = "yes" *) reg [15:0] product;

Inferring Block RAMs

Block RAMs are frequently utilized in FPGA circuits. The usual way to insert a block ram module in the design is to instantiate a component from a vendor-specific library. This solution is often not very desirable because of the lack of portability. Another way that is possible with modern synthesis tools is to write a behavioral description of a RAM module so that a synthesizer can infer that it can be implemented as a block RAM. This behavioral description must be written carefully, otherwise it is possible that a synthesizer won't recognize it. The following example was tested with XST and Synplify synthesizers.

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FPGA design tutorial: Advanced HDL synthesis

Consider a dual-port block RAM with 16-bit data words, 6-bit address, one write port and one read port. Here's its VHDL description: library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity mem1 is port ( CLK : in std_logic; WE : in std_logic; WADDR : in std_logic_vector(5 downto 0); RE: in std_logic; RADDR : in std_logic_vector(5 downto 0); DIN : in std_logic_vector(15 downto 0); DOUT : out std_logic_vector(15 downto 0) ); end mem1; architecture behavioral of mem1 is type ram_type is array (63 downto 0) of std_logic_vector (15 downto 0); signal RAM : ram_type; signal read_addr : std_logic_vector(5 downto 0); attribute syn_ramstyle : string; attribute syn_ramstyle of RAM : signal is "block_ram"; begin process (CLK) begin if rising_edge(CLK) then if WE='1' then RAM(conv_integer(WADDR))<=DIN; end if; end if; end process; process (CLK) begin if rising_edge(CLK) then if RE='1' then read_addr<=RADDR; end if; end if; end process; DOUT<=RAM(conv_integer(read_addr)); end behavioral; A Verilog description of the same module: module mem1 (clk,re,we,waddr,raddr,din,dout); input clk; input re; input we; input [5:0] waddr; input [5:0] raddr; input [15:0] din; output [15:0] dout; reg [15:0] ram [63:0]; /* synthesis syn_ramstyle="block_ram" */ reg [5:0] read_addr; always @(posedge clk) begin if (we) ram[waddr] <= din; end always @(posedge clk) begin if (re) read_addr <= raddr; end assign dout = ram[read_addr];

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FPGA design tutorial: Advanced HDL synthesis

endmodule syn_ramstyle attribute is intended for Synplify, but XST also recognises it. Using behavioral block RAM descriptions is recommended when possible, since it increases portability and facilitates design reuse. Resources Support Library Careers Contacts

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