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????? ??? ??????? ???? ?????? ?????????????? ??????? ???? ???emory accesses in D
SP algorithms tend to exhibit very
predictable patterns; for example, for each sample in an
FIR filter, the filter coefficients are accessed sequentially
from start to finish for each sample, then accesses start
over from the beginning of the coefficient vector when
processing the next input sample. This is in contrast to
other types of computing tasks, such as database processing,
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????? ??? ??????? ???? ?????? ?????????????? ??????? ???? ???s to memory are les
s predictable. DSP
processor address generation units take advantage of this
predictability by supporting specialized addressing modes
that enable the processor to efficiently access data in the
patterns commonly found in DSP algorithms. The most
common of these modes is register-indirect addressing
with post-increment, which is used to automatically increment
the address pointer for algorithms where repetitive
computations are performed on a series of data stored