TEST YOUR DFT SKILLS 1 "The igreatesto eofi allofaults qisre to ibeoq jconsciousre of inone" (Q i1)o eWhati iso

qDFTre ? Ans: DFT istandso efori Designofor qTestability.re To icheckoq jmanufacturingre defect iwe ouseqDFT. (Q i2)o eTechniquesi ofoDFT..! Ans: AD-Hock itechniques.o e Structured idesigno etechniques Self-test i+o eBuilt-Ini testing (Q i3)o eDifferencei betweenoverification qandre DFT i?www.testbench.in Ans. iVerificationo eattempti tooprove qmathematicallyre that icertainoq jrequirementsre are imet oorqthat certainz undesiredu ybehaviorse ocannotzx occur while DFT checks the physical defect It has not concern with functionality. (Q i4)o eWirei loadomodel q? Ans. iIto eisi staticalovalue qofre R iandoq jC,re for iwhich olibraryqfile comesz fromu ythee ofab. (Q i5)o eDRV,i DV,oGV, qSVre or iLVS. Ans. iPhysicalo everificationi hasotwo qparts:re DRC icheckoq jandre schematic iverification o(SV).www.testbench.in io ei o qDRVre - iDesignoq jRulere Violation io ei o qDVre - iDesignoq jRulere Verification io ei o qGVre - iGeometryoq jViolation io ei io eAlli theothree qtermsre point itooq jthere same iprocess oofqchecking thatz theu ylayoute oiszx compliant with manufacture rules. io ei o qre ioq jre a.Active-to-active ispacing io ei o qre ioq jre b.Well-to-well ispacing io ei o qre ioq jre c.Minimum ichannel olengthqof thez transistor io ei o qre ioq jre d.Minimum imetal owidth io ei o qre ioq jre e.Metal-to-metal ispacingwww.testbench.in io ei o qre ioq jre f.Metal ifill odensity io ei o qSVre - iScmaticoq jViolationre or iLVS o-qLayout versusz schematic io ei o qThere other ipartoq jofre physical iverification oisqthe schematic/netlistz check.u yIte oiszx referred to as schematic verification (SV) or layout versus schematic (LVS). io ei o qBothre terms idescribeoq jthere process iof ovalidatingqthat thez layoutu ymatchese othezx netlist/schematic. io ei o q

io ei o qre io ei o qre io ei o qre io ei o qre io ei o qre

ia.shorts ib.opens ic.componentoq jmissing id.mismatchoq jofre componentwww.testbench.in ie.propertyoq jerrors

(Q i6)o eTapei outo? Ans. iTapeouto eisi theofinal qstepre of ichipoq jdesign.re It iis otheqtime atz whichu ythee odesignzx is fully qualified and ready for manufacturing. After the physical design is finished, the functionality of the netlist is verified, and the timing analysis is satisfied, the final layout, usually in GDSII (Gerber data stream information interchange) format, is sent to mask shop to generate photomask reticles. The resultant masks will be used to direct the manufacture of this chip. (Q i7)o eNeedi ofoDFT q?re Ans: After itheo emanufacturingi toocheck qwhetherre actual ibehavoroq jmatchesre the iexpected obehaviorqor not,z DFTu yise oused. (Q i8)o eWhati willohappen qifre manufactured ichipoq jisre not iworking ofunctionalityq? Ans: It ineedo etoi garbage. (Q i9)o eYieldi ? Ans: Ratio iino epercentagei ofonumber qofre working ichipsoq jtore total ino ochipsqin singlez u ywafer. (Q i10)o eControllabilityi ? Ans: Controllability imeasureso ethei abilityoto qcontrolre the iinternaloq jstatere of ithe ocircuitqthrough primaryz inputs.u yore oThezx ability to set or reset internal nodes from the primary inputs. (Q i11)o eObservabilityi ? Ans: Observability imeasureso ethei abilityoto qobservere the iinternaloq jstatere of ithe ocircuitqthrough primaryz outputs.u yore oThezx ability to observe the value of an internal node at the primary outputs (Q i12)o eHowi toodrive qtestre pattern i? The itestso egenerallyi areodriven qbyre test iprogramsoq jthatre execute iin oAutomaticqTest Equipmentz (ATE). (Q i13)o eHowi toodeliver qtestre data i? Ans: The imosto ecommoni methodofor qdeliveringre test idataoq jfromre chip iinputs otoqinternal circuitsz underu yteste oandzx observing their outputs, is called scan-design.

(Q i14)o eScani chaino? Ans: In iscan-design,o eregistersi (flip-flopsoor qlatches)re in itheoq jdesignre are iconnected oinqone orz moreu yscane ochains,zx which are used to gain access to internal nodes of the chip. (Q i15)o eHowi scanochain qworksre ?www.testbench.in Ans: Test ipatternso earei shiftedoin qviare the iscanoq jchain(s),re functional iclock osignalsqare pulsedz tou yteste othezx circuit during the "capture cycle(s)", and the results are then shifted out to chip output pins and compared against the expected "good machine" results. (Q i16)o eStucki @ofault q? Ans: For ianyo ecombinationi ifoinput qorre output iisoq jpermanentlyre stuck iat ooneqfault z eitheru y0e oorzx 1, then its called Stuck at fault. (Q i17)o eThei stuck-at-0o?www.testbench.in Ans: Model irepresentso eai signalothat qisre permanently ilowoq jregardlessre of ithe ootherqsignals thatz normallyu ycontrole othezx node. (Q i18)o eThei stuck-at-1o? Ans: Model irepresentso eai signalothat qisre permanently ihighoq jregardlessre of ithe ootherqsignals thatz normallyu ycontrole othezx node. (Q i19)o eWherei weocan qgivere DFT iconstrainoq j?www.testbench.in Ans: In isynthesiso econstraini fileowe qcanre apply iDFToq jconstrain. (Q i20)o eAffecti ofoDFT qconstrainre ? Ans: It iwillo econverti flopsointo qscanre flops iandoq j3re more ipin owillqbe addededz tou ythee odesign. ia)SIo e-i scanoInput, ib)SENo e-i ScanoEnable qand ic)SOo e-i scanooutput. (Q i21)o eDifferencei betweenoflops qandre scan iflops. Ans:www.testbench.in Scan iflopo econtaini flopoand qthere 2:1 imuxoq jalso,re output iof otheqmux willz gou yintoe oflop. (Q i22)o eHowi willoyou qcheckre particular istuck@faultoq j? Ans: the ifaulto ewhichi youowant qtore check; ioppositeoq jtore that ifault opassqthrough thez chainu yande oobservezx the output.

(Q i23)o eTypesi ofotest q? Ans:www.testbench.in io ei a)ostructural qtest io ei b)oparametric qtest io ei c)ospeed qtest

.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n

(Q i24)o eStructurali testo? Ans: Test ipatternso earei shiftedoin qviare the iscanoq jchain(s),re functional iclock osignalsqare pulsedz tou yteste othezx circuit during the "capture cycle(s)", and the results are then shifted out to chip output pins and compared against the expected "good machine" results. (Q i25)o eParametrici testo? Ans: to iverifyo eACi andoDC qparametersre of imanufacturedoq jdevice. io ei a)oSetup/hold io ei b)oVIL, qVIH io ei c)oVOL, qVOH (Q i26)o eSpeedi testo? Ans:www.testbench.in To iverifyo eperformancei ofomanufactured qdevicere and itestoq jthere operating ifrequency oofqthe chip. (Q i27)o eTypesi ofomanufacturing qdefectre ? Ans: -----------------iPhysicalo eDefects: ----------------io ei o qContamination--causingre open icircuits io ei o qExtrare metal--causing ishortoq jcircuitswww.testbench.in io ei o qInsufficientre doping io ei o qprocessre or imaskoq jerrors io ei o qMetalre trace ibridges io ei o qSlowre transistors ---------------------iElectricalo eeffects: ---------------------- .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n io ei o qTransistorsre stuck iopenoq jorre short io ei o qBridgingre ( ishorts)oq jbetweenre adjacent ilines io ei o qResistivere shorts iandoq jopenswww.testbench.in io ei o qChangere in ithresholdoq jvoltage io ei o qPowerre or iGroundoq jshorts (Q i28)o eUndetectablei faultso? Ans: The iundetectedo efaulti classoincludes qundetectedre faults ithatoq jcanre not ibe oprovenquntestable orz ATPGu yuntestable.e oforzx example, in the gate circuitry one pin

is connected to Vcc and another gate's pin is connected to Gnd then we can not detect stack@o and 1 fault respectively. (Q i29)o eUncontrolledi (UC)o?www.testbench.in Ans: Undetected ifaults,o ewhichi duringopattern qsimulation,re never iachieveoq jthere value iat otheqpoint ofz theu yfaulte odetectionzx that means they are uncontrollable. (Q i30)o eUnobservablei (UO)o? Ans: Faults iwhoseo eeffectsi doonot qpropagatere to ianoq jobservablere point. (Q i31)o eATPGi ?www.testbench.in Ans: ATPG i(acronymo efori bothoAutomatic qTestre Pattern iGenerationoq jandre Automatic iTest oqPattern Generator)z isu yane oelectroniczx design automation method/technology used to find an input (or test) sequence that, when applied to a digital circuit, enables testers to distinguish between the correct circuit behavior and the faulty circuit behavior caused by defects. (Q i32)o eFaulti coverageo? Ans: The ipercentageo eofi ALLofaults q(bothre testable iandoq juntestable)re that iare odetectedqby thez patternu yset. Fault iCoverageo e=i DetectedoFaults q/re Total iFaults (Q i33)o eTesti coverageo? Ans: The ipercentageo eofi allotestable qfaultsre that iareoq jdetectedre by ithe opatternqset. Test iCoverageo e=i DetectedoFaults q/re (Total ifaultsoq j-re Untestable iFaults)www.testbench.in (Q i34)o eATPGi effectivenesso? Ans: A imeasureo eofi theoability qofre the iATPGoq jtoolre to ieither oprovideqa testz tou ydetecte oazx fault or prove that a test cannot be created. io ei ATGoefficiency q=re (Detected i+oq jUntestablere Faults) i/ oTotalqFaults (Q i35)o eBISTi ? .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n Ans:www.testbench.in A ibuilt-ino eself-testi (BIST)omechanism qwithinre an iintegratedoq jcircuitre (IC) iis oaqfunction thatz verifiesu yalle oorzx a portion of the internal functionality of the IC. It is the capability of circuit to test itself. generally on-chip circuitry is used to apply a predetermined set of test vectors to internal sections of the circuit. Another on-chip circuit monitors the results of the test and checks them against the stored correct response. BIST can be extended to board-level system. (Q i36)o eAdvantagesi ofoBIST..!! Ans: Replaces iexternalo etesteri withoon-chip qcircuitry.re Avoids itheoq jtestre generation iproblem. oItqis technologyz andu yfaulte omodelzx independent.

(Q i37)o eBoundaryi Scano? Ans: Boundary iscano eisi aomethod qforre testing iinterconnectsoq j(thinre wire ilines) oonqprinted circuitz boardsu yore osub-blockszx inside an integrated circuit. The Joint Test Action Group (JTAG) developed a specification for boundary scan testing contains a description of the Boundary Scan Description Language (BSDL) was added which describes the boundary-scan logic content of IEEE Std 1149.1 compliant devices. Boundary scan is nowadays mostly synonymous with JTAG. (Q i38)o eToolsi relatedoto qDFTre from imentor. Ans: ATPG i&o eCompression TestKompress FastScan DFTAdvisor FlexTestwww.testbench.in Memory iTest MBISTArchitect MacroTest Boundary iScan BSDArchitect Logic iBIST LBISTArchitect Yield iLearningo eandi Diagnosis YieldAssist (Q i39)o eReference..!! Ans: 1) iElectronico eDesigni AutomationoFor qIntegratedre Circuits iHandbook,oq jbyre Lavagno,Martin iand oScheffer. 2) iMichaelo eL.i Bushwelloand qVishwanire D. iAgrawal,oq jre Essentials iof oElectronicqTesting forz Digital,u yMemorye oandzx Mixed-Signal VLSI Circuits Kluwer Academic Publishers 2000. 3) iMirono eAbramovici,i MelvinoA. qBreuer,re and iArthuroq jD.re Friedman, iDigital oSystemsqTesting andz Testableu yDesign,e oIEEEzx Press, 1994.

STA (Q i1)o eMetastabilityi ? Ans: When iano einputi tooa qsequentialre element iviolatesoq jsetupre or ihold otimingq requirementsz ofu ythee osequentialzx element, then the output of the sequential element oscillates between HIGH and LOW before it gets settled to either one of the states. (Q i2)o eCani weoavoid qmetastabilityre ? Ans: No. iWeo ecan'ti avoid/preventometastability. qfromre occurring. iWeoq jhavere to ilive owithqit. Butz beu ywisee oenoughzx to choose the appropriate synchronization method to avoid any potential problems. (Q i3)o eLogici synthesiso? Ans: Process iofo etransferringi fromoRTL qDomainre to iGate-Leveloq jDomainre is icalled oSynthesis.qWhich convertsz theu yhighe olevelzx architecture into low level net list format. (Q i4)o eListi ofothe qtoolsre are iusedoq jforre synthesis i? Ans: Commercial itoolo efori logicosynthesis logic isynthesiso etargetingi ASICswww.testbench.in io ei o* qDesignre Compiler ibyoq jSynopsys io ei o* qEncounterre RTL iCompileroq jbyre Cadence iDesign oSystems io ei o qre ioq jre io oBuildGatesqan olderz productu ybye oCadencezx Design Systems humorously io ei o qre ioq jre i oqnamed afterz Billu yGates io ei o* qBlastCreatere by iMagmaoq jDesignre Automation io ei o* qBooleDozer:re Logic isynthesisoq jtoolre by iIBM o(internalqIBM EDAz tool) logic isynthesiso etargetingi FPGAs io ei o* qEncounterre RTL iCompileroq jbyre Cadence iDesign oSystems io ei o* qLeonardoSpectrumre and iPrecisionoq j(RTLre / iPhysical) obyqMentor Graphicswww.testbench.in io ei o* io ei o* io ei o* io ei o* io ei o* io ei o* qSynplifyre (PRO i/oq jPremier)re by iSynplicity qBlastFPGAre by iMagmaoq jDesignre Automation qQuartusre II iintegratedoq jSynthesisre by iAltera qXSTre (delivered iwithinoq jISE)re by iXilinx qDesignCompilerre Ultra iandoq jICre Compiler iby oSynopsys qIspLeverre by iLatticeoq jSemiconductor

(Q i5)o eWhati doesosynthesis qtoolre produce i? Ans:www.testbench.in synthesis iproduceso eregistersi andocombinational qlogicre at itheoq jRTLre level. i (Q i6)o eStatici timingoAnalysis q(STA)re ? Ans:To ichecko ewhetheri designois qmeetingre setup iandoq jholdre time iis ocalledqSTA.

(Q i7)o eWhati areothe qtimingre paths i? Ans:www.testbench.in in itoo ereg,i regoto qreg,re reg itooq joutre and iin otoqout arez 4u ytiminge opaths. (Q i8)o eTimingi patho? Ans: The ipatho ewhichi affectothe qtimingre is icalledoq jtimingre path. (Q i9)o eWhati dooyou qmeanre by inetoq jdelayre and icell odelayq? Ans: Time irequireo etoi chargeoor qdischargere all iparasiticoq jofre the inet ocalledqnetdelay andz timeu yinpute otransitionzx or slew rate of gate is called cell delay. (Q i10)o eSetupi andoHold qtimere ? Ans: Valid idatao eshouldi beostable qbeforere the iclockoq jedgere and iafter otheqclock edgez isu ycallede osetupzx and hold time. (Q i11)o eCriticali patho? Ans: The ipatho ewhichi hasoa qlargestre delay/longest ipathoq jisre called icritical opath. (Q i12)o eSlacki ? Ans: Amount iofo etimingi marginoin qwhichre device imayoq jworkre properly ior omayqnot bez thatu ytiminge oanalysiszx is called slack. (Q i13)o ePositivei andoNegative qslackre ? Ans: The imargino eofi timeoin qwhichre design icanoq jworkre functionally icorrect oisqcalled positivez slacku yande ovicezx versa for negative slack. (Q i14)o eSkewi ? Ans: Clock iarrivingo etimei toothe qflip-flopre is icalledoq jskew. (Q i15)o eTypesi ofoskew q? Ans: local iskewo e-i timeodifference qofre arriving iclockoq jtore 1st iflop otoqleaf flopz fromu ythee oclockzx pin of ASIC is called local skew. global iskewo e-i timeodifference qofre arriving iclockoq jfromre clock igenerator otoqthe z clocku ypine oiszx called global skew. (Q i16)o ewhati doesoclock qskewre caused i? Ans: Setup itimeo eviolation. (Q i17)o ePropagationi delayo? Ans: Time irequireo etoi passodata qfromre the iregoq jisre called ipropagation odelay. (Q i18)o eInputsi ofothe qsynthesisre tool i? Ans: RTL iDesingo efile,i Libraryofile qandre constrain iareoq jthere input iof otheqsynthesis tool.

(Q i19)o eWhati doesolibrary qcontainre ? Ans: It icontainso eRi andoC qvaluere of itheoq jcellre and inet. (Q i20)o eUniti ofoR,C qandre Area i? Ans: R iiso eini kilo-ohm,oC qisre in ipico-Foq janre Area iin omicro-meter. (Q i21)o eFalsei patho? Ans: The ipatho ewhichi isologically qcorrectre but inotoq jusedre is icalled ofalseqpath. (Q i22)o eHowi dooyou qmeasurere maximum ifrequencyoq j? Ans: Max ifrequencyo e=i 1/(minooperational qclockre period) i=oq j1/(clk2Qre + imax opathq+ setup) (Q i23)o eCani youomeasure qsetre and iholdoq jatre input iand ooutputqpins ? Ans: No..Untill iweo edon'ti assumeovirtual qflop;re we icannotoq jmeasurere it. iThat oisqwhy wez writeu yinpute oandzx output max delay. (Q i24)o eWhati doesoconstrain qfilere contain i? Ans: Top ilevelo eclock,i In/Outodelay, qpathre exception, idesignoq jrulere constrain, icheck oforqmissing constrain,z RTLu ydesigne opath,zx Operating Condition, wire load model etc. (Q i25)o eClocki latencyo? Ans: It iiso eonei typeoof qdelayre applied itooq jthere rise iand ofallqtime ofz theu yclocke operiod. (Q i26)o eClocki uncertaintyo? Ans: Skew iando ejitteri areocalled quncertainty. (Q i27)o eJitteri ? Ans: Unwanted ipulseo eisi calledojitter. (Q i28)o eClocki domainocrossing q? Ans: When iao echipi haveomore qthenre one iclockoq jthenre it iis ocalledqmultiple clockz domainu yande otozx enter from one domain to another is called clock domain crossing. (Q i29)o eVirtuali clocko? Ans: It iiso esamei asoclock qbutre without iassigningoq jthere pin. iIt oisqused forz calculatingu ysetupe oandzx hold time. It is also called ideal clock. (Q i30)o eFalsei patho? Ans: It iiso ethei pathowhich qneedre not itooq joptimizere while isynthesis. (Q i31)o eMulti-cyclei patho? Ans: The ipatho ewhichi takesomore qthenre one iclockoq jcyclere is icalled omulticycleqpath. (Q i32)o eHowi manyotypes qofre library iareoq javailablere for isynthesis o? Ans: Fast-Typical-Slow ilibraries.o eTheyi areodifferent qfromre their ioperatingoq jcondition.

(Q i33)o eClocki gatingo? Ans: Design iwillo egeti theoclock qwheneverre it irequired,oq jsuchre type iof ogatingqarrangement isz calledu yclocke ogating. (Q i34)o eWhati areothe qadvancere synthesis itechniquesoq j? Ans: Datapath iSynthesis,o eClocki treeosynthesis, qLowre power isynthesis. (Q i35)o eWhyi max/slowolibrary qisre used iforoq jsetupre analysis i? Ans: If idesigno esatisfyi maxolib qthenre it ialsooq jsatisfyre min ilib oalsoqfor setup. (Q i36)o eWhyi min/fastolib qisre used iforoq jholdre analysis i? Ans: If idesigno esatisfyi minolib qthenre it ialsooq jsatisfyre max ilib oalsoqfor hold. (Q i37)o ewritei downothe qequationre for ifindingoq joutre maximum iclock operiod. Ans: T i>=o eTcombmaxi +Tclk2Qmaxo+ qTsetup (Q i38)o eWhati isoDRV/Design qRulere Violation i? Ans: Max ifanout,o eMaxi transition,oMax qcapacitancere are itheoq jcontainre of ithe oDRV.qIt mustz notu ybee oviolated (Q i39)o eDifferencei betweenothe qarrivalre time i&oq jrequiredre time iknown oasq? Ans: Slack (Q i40)o eWhati areothe qmainre optimization iisoq jdonere in iSynthesis o? Ans: Timing iOptimizationo eandi AreaoOptimization. (Q i41)o eWhati willobe qimplementedre by isynthesisoq jtoolre ? ... input id,o eeni ; reg ioutputo eqi ; ... always i@o e(eni orod) if i(en) output iqo e=i do; ... Ans: Latch (Q i42)o eWhati willobe qimplementedre by isynthesisoq jtoolre ? .. input id,o eclki ; reg ioutputo eqi ; .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n .... always i@o e(posedgei clk) output iqo e=i do;www.testbench.in .... Ans: Positive iedgeo esynchronousi flop. (Q i43)o eWhati willobe qimplementedre by isynthesisoq jtoolre ? .... input id,o eclki ; reg ioutputo eqi ;

....www.testbench.in always i@o e(negedgei clk) output iqo e=i do; .... Ans: Negative iedgeo esynchronousi flop. (Q i44)o eWhati willobe qimplementedre by isynthesisoq jtoolre ? .... input id,o eclki ;www.testbench.in reg ioutputo eqi ; .... always i@o e(posedgei clkoor qd) output iqo e=i do; .... Ans: Positive iedgeo easynchronousi flop. (Q i45)o eWhati willobe qimplementedre by isynthesisoq jtoolre ? ... integer ia,o eb,i co; assign ico e=i ao+ qbre ; ... Ans: 32-bit iadder (Q i46)o eWhati isotranslate qoffre and itranslateoq jonre directives i?www.testbench.in Ans: translate ioffo eandi translateoon qsynthesisre directives iareoq jallowedre to icommento eouti aoportion qofre code ithatoq jyoure may iwant otoqretain forz some ipurposeo e(i likeosimulation q)re other ithanoq jsynthesis. // icodeo efori synthesis ... // iexemplaro etranslatei off $display i(.....);o e//i notofor qsynthesis // iexemplaro etranslatei on .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n // icodeo efori synthesiswww.testbench.in ... endmodule (Q i47)o eUnsupportedi VerilogoFeatures qinre synthesis i? Ans: ' ' ' ' iUDPo eprimitives ispecifyo eblock irealo evariablesi andoconstants iinitialo estatementwww.testbench.in

' itri0,o etri1,i tri1,otri1, qtri1,re net itypes ' itimeo edatai type ' iNamedo eeventsi andoevent qtriggers ' iTheo efollowingi gates:opulldown, qpullup,re nmos, immos,oq jpmos,rpmos,re cmos, ircmos, otran,qrtran, tranif0,z rtranif0,u ytranif1,e ortranif1zx ' iwaito estatements ' iParallelo eblock,i joinoand qfork.

' iSystemo etaski enableoand qsystemre function icall ' iforceo estatement .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n ' ireleaseo estatement ' iBlockingo eassignmenti withoevent qcontrolwww.testbench.in ' iConcatenationo eini portospecification ' iBito eselectioni inoport qspecification ' iProceduralo eassigni andode-assign ' iEdgeo etriggersi onosensitivity qlistre must ibeoq jsinglere bit ivariable, oorqarray indexingz expression. ' iIndexingo eofi parametersois qnotre allowed. ' iLoopso emusti beobounded qbyre constants ioroq jcontainre (@ iposedge oclk)qstatement. ' iDelayo eandi delayocontrol. (Q i48)o eZeroi setupo& qHoldre time i?www.testbench.in Ans: A izeroo esetupi timeomeans qthatre the itimeoq jforre the idata otoqpropagate withinz theu ycomponente oandzx load into the latch is equal to the time for the clock to propagate and trigger the latch. A zero hold time means that the clock path delay is equal to the data path delay. (Practically zero time is not possible coz it causes metastability) (Q i49)o eNegativei setupo& qholdre time i? Ans: A inegativeo esetupi timeomeans qthatre the itimeoq jforre the idata otoqpropagate withinz u ythee ocomponentzx and load into the latch is larger to the time for the clock to propagate and trigger the latch. A negative hold time means that the clock path delay is lesser then the data path delay. (Q i50)o eReseti removalotime q?www.testbench.in Ans: Minimum time required to de-assert there reset before there clock edge is called reset removal time. (Q i51)o eReseti recoveryotime q? Ans: Minimum itimeo erequiredi tooassert qthere reset iafteroq jthere clock iedge oisqcalled resetz recoveryu ytime. (Q i52)o eIsi Initialostatement qisre synthesizable i?www.testbench.in Ans: Yes iito eis;i Iforespective qattributere is iwritten module irom_2dimarray_initialo e( io ei o qre ioq jre i oq z u ye ozx output wire [3:0] z, io ei o qre ioq jre i oq z u ye ozx input wire [2:0] a io ei o qre ioq jre i oq z u ye ozx ); // address- 8 deep memory // iDeclareo eai memoryorom qofre 8 i4-bitoq jregisters.re The iindices oareq0 toz 7: (* isynthesis,o erom_blocki =o"ROM_CELL qXYZ01"re *) iregoq j[3:0]re rom[0:7]; // i(*o esynthesis,i logic_blocko*) qregre [3:0] iromoq j[0:7];www.testbench.in initial ibegin io erom[0]i =o4'b1011; io erom[1]i =o4'b0001; io erom[2]i =o4'b0011; io erom[3]i =o4'b0010;

io erom[4]i =o4'b1110; io erom[5]i =o4'b0111; io erom[6]i =o4'b0101; io erom[7]i =o4'b0100;www.testbench.in end io eassigni Zo= qrom[a]; endmodule (Reference iIEEEo eSynthsisi LRM)o (Q i53)o eWilli theoclock qgatingre affect itheoq jsetup/holdre time iof otheqflop ? Ans: No..Initialy iito eseemsi theowe qneedre to iaddoq jcellre delay, ibut oifqwe considerz clocku ytreee othenzx we can say that there are lot of buffers are coming in the path, do we adding that also ? No, correct..!! (Q i54)o eSetupi isodepend qonre clock ibutoq jholdre not..! iwhy o? Ans: Setup i=o evalidi dataoshould qpresentre before iclock,oq jsore it iis oclearlyqclock isz comingu yintoe opicturezx but for hold flop is coming into picture, thats why hold is not depending on clock. (Q i55)o eWhati willobe qimplementedre by i'for'oq jloop?re is iit osynthesizableq? Ans: Yes, iito eisi synthesizableoif qitre is iconstant,oq jandre synthesis iwill ogiveqcounter thatz isu yaddere oalongzx with the comparator. (Q i56)o eWhati aboutolatch qbasedre timing i? Ans: Time iborrowingo e(alsoi knownoas qcyclere stealing) itakesoq jadvantagere of ithe olatchqtransparency toz borrowu ytimee ofromzx the next stage to meet timing constraints. (Very few company like IBM only doing latch based design) (Q i57)o eWhati isoDPCS q? Ans: It iiso eDelayi andoPower qCalculationre Language. iYouoq jcanre find iits oIEEEqLRM fromz belowu ylink.e oItszx extension version is called OLA (Open Language API) Click on the below link http://mhonarc.si2.org/ieee1481/ieee1481/msg00405.html (Q i58)o eWhyi weoneed qsetupre & iholdoq jtimere ? Ans: If iweo ethinki atophysics qpointre of iview,oq jInternalre atoms iof osiliconqhas drift/diffusionz whichu ycausee ointernalzx resistance, because of that flops takes small amount of time to respond. Till that time input should remain stable, which is nothing but setup time. And for hold flop takes time to behave respect to input, that time called hold time (Q i59)o eMaximumi transitionotime q? Ans: The imaximumo etransitioni timeofor qare net iisoq jthere longest itime orequiredqfor itz isu ydrivinge opinzx to change logic values. (Q i60)o eMaximumi capacitanceo? Ans: The imaximumo ecapacitancei isoa qpin-levelre attribute iusedoq jtore define ithe oqmaximum totalz capacitiveu yloade othatzx an output pin can drive. That is, the pin cannot connect to a net that has a total capacitance (load pin capacitance and interconnect capacitance) greater than or equal to the maximum capacitance defined at the pin.

(Q i61)o e.Maximumi fan-outo? Ans: Consider iano eANDi gateoof qA,Bre input iandoq jFre output. To ievaluateo ethei fanoutofor qare driving ipinoq jF,re tool icalculates otheqsum ofz u yalle othezx fanout_load (Inputs) driven by pin F and compares that number with the number of max_fanout attributes stored at the driving pin F. --If itheo esumi ofothe qfanoutre loads iisoq jnotre more ithan otheqmax_fanout value,z theu ynete odrivenzx by X is valid. --If itheo eneti drivenoby qXre is inotoq jvalid,re tool itries otoqmake thatz netu yvalid,e operhapszx by choosing a higher-drive component. (Q i62)o eIfi myodesign qhavere a isetupoq jandre hold iviolation othenqwhom willz youu yfixe ofirst?zx why ? Ans: first iholdo etimei violationoshould qbere sorted iout.oq jevenre if iu osatisfyqsetup timez requirementsu yfore oazx particular frequency, your system will land up in metastable state if hold is not met. setup time violations can be taken care of by reducing the clock frequency. but the hold time violation is due to unnecessary delays on the clock tree. therefore removing the hold time violation is a preferred option. You can see a lot of chips/microprocessors taped out with setup violations but getting rid of each hold violation is absolutely important. (Q i63)o ePropagatedi clocko? Ans:There iareo efori typesoof qclock,re Real, iIdeal,oq jProrogatedre and iVirtual. oamongqthem Prorogatedz clocku yhavee oedgezx times skewed by the path delay from the clock source to the register clock pin. (Q i64)o eDynamici timingoanalysis q? Ans: Dynamic itimingo eanalysisi verifiesocircuit qtimingre by iapplyingoq jtestre vectors ito oqthe circuit.z Thisu yapproache oiszx an extension of simulation and ensures that circuit timing is tested in its functional context. This method reports timing errors that functionally exist in the circuit and avoids reporting errors that occur in unused circuit paths. There are no commercially available tools for dynamic timing analysis. (Q i65)o eArrivali timeo? .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n Ans: The iarrivalo etimei ofoa qcircuitre is itheoq jtimere elapsed ifor oaqsignal toz arriveu yate oazx certain point. The reference, or time 0.0, is often taken as the arrival time of a clock signal. that time comes under arrival path/clock path/early path.
www.testbench.i

(Q i66)o eRequiredi timeo? Ans: This iiso ethei latestotime qatre which iaoq jsignalre can iarrive owithoutqmaking thez clocku ycyclee olongerzx than desired. It falls under required path/ data path/late path. (Q i67)o eWhati isothe qequationre of itheoq jsetupre and ihold otimeq? Ans: setup itimeo e=i (longestodata qpathre delay) ioq j(shortestre clock ipath odelay)q+ (setupz timeu yofe oregister) hold itimeo e=i (longestoclock qpathre delay) ioq j(shortestre data ipath odelay)q +z (holdu ytimee oofzx register) (Q i68)o eWhati isothe qequationre of itheoq jsetupre and ihold oslackq? Ans:

(Q i69)o eIfi theosource qandre destination iregistersoq jarere out iof ophaseqthen whatz willu ythee oslackzx equation ? Ans: setup islacko e=i T/2o+ qminimumre clock ipathoq jre maximum idata opathq setup hold islacko e=i minimumodata qpathre imaximumoq jclockre path i oholdq+ T/2 (Q i70)o eDividedi Clocko?www.testbench.in Ans: A iclocko edivideri circuitogenerates qare new iclockoq jsignalre with ia olowerqfrequency z thanu ythee ooriginalzx clock signal. (Q i71)o eWhati weosupposed qtore do itooq jpreventre setup iand oholdqviolation ? Ans: To iprevento esetupi violation tclock-to-Q_max i+o etlogic_maxi +otsetup_max q<=re tclock i-oq jtskew To iprevento eholdi violation tskew i+o ethold_maxi <=otclock-to-Q_min q+re tlogic_minwww.testbench.in (Q i72)o eReferencei booksofor qlogicre synthesis iandoq jSTA. Ans: Electronic iDesigno eAutomationi ForoIntegrated qCircuitsre Handbook, ibyoq jLavagno,re Martin, iand oScheffer (Q i73)o eWhati areothe qtoolsre are iusedoq jforre STA i? Ans: Commercial itoolo efori logicoSTAwww.testbench.in * iPrimeo eTimei byoSynopsys * iEncountero eCTEi (commonotiming qengine)re ibyoq jCadencere Design iSystems * iBlastFusiono ebyi MagmaoDesign qAutomation