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A 90-nm CMOS 5-GHz Ring-Oscillator PLL With Delay-Discriminator-Based Active Phase-Noise Cancellation
Seungkee Min, Member, IEEE, Tino Copani, Associate Member, IEEE, Sayfe Kiaei, Fellow, IEEE, and Bertan Bakkaloglu, Senior Member, IEEE
AbstractRing oscillators (ROs) provide a low-cost digital VCO solution in fully integrated PLLs. However, due to their supply noise sensitivity and high noise oor, their applications have been limited to low-performance applications. The proposed architecture introduces an analog feed-forward adaptive phase-noise cancellation architecture that extracts and suppresses phase noise of ROs outside the PLL bandwidth. The proposed technique can improve the phase noise at an arbitrary offset frequency and bandwidth, and, after initial calibration for gain, it is insensitive to process, voltage, and temperature variations. An experimental fractional PLL, with a loop bandwidth of 200 kHz, is utilized to demonstrate the active phase-noise cancellation approach. The cancellation loop is designed to suppress the phase noise at 1-MHz offset by 12.5 dB and reference spur by 13 dB with less than 17% increase in the overall power consumption at 5.1-GHz frequency. The measured phase noise at 1-MHz offset after cancellation is 105 dBc/Hz. The proposed RO-PLL is fabricated in 90-nm CMOS process. With noise cancellation loop enabled, the PLL consumes 24.7 mA at 1.2-V supply. Index TermsDelay-discriminator, frequency phase-locked loop (PLL), ring-oscillator VCO. synthesizer,

I. INTRODUCTION OLTAGE-CONTROLLED oscillators (VCOs) are one of the most critical blocks in phase-locked loops (PLLs). LC-tank VCOs have a superior phase-noise performance. However, they require bulky passive resonators and calibration to overcome their limited tuning range. Ring-oscillator (RO)-based VCOs are attractive for digital system applications owing to their ease of integration, small die area, and scalability in deep submicron processes. However, due to their supply sensitivity and poor phase-noise performance, they have limited use in applications demanding low phase-noise oor, such as wireless or optical transceivers. Particularly, the out-of-band phase noise of RO-based PLLs is dominated by
Manuscript received September 10, 2012; revised January 17, 2013; accepted January 18, 2013. Date of publication March 29, 2013; date of current version April 19, 2013. This paper was approved by Guest Editor Srenik Mehta. S. Min was with Arizona State University, Tempe, AZ 85287 USA. He is now with the RF Division, Freescale Semiconductor, Tempe, AZ 85259 USA. T. Copani was with Arizona State University, Tempe, AZ 85287 USA. He is now with the Mixed Process Division, IBP Group, STMicroelectronics, Catania, 95121 Italy (e-mail: tino.copani@st.com). S. Kiaei and B. Bakkaloglu are with Arizona State University, Tempe, AZ 85287 USA. Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/JSSC.2013.2252515

the RO noise oor, which cannot be suppressed by the loop gain. Wide-loop-bandwidth PLLs can suppress RO phase noise at higher frequencies; however, they suffer from increased in-band noise due to contributions generated by reference, phase detectors, and charge-pumps. Most phase-noise cancellation schemes reported so far have been targeting deterministic modulator quantization noise in fractional- synthesizers [3]. These approaches enable wider loop bandwidths and cancel close-in phase noise due to quantization error in the fractional controller. However, they cannot track and cancel random phase errors in a PLL. Recently, different approaches have been proposed to minimize PLL phase noise outside loop bandwidth through cancellation [2][5]. A current-steering DAC in parallel with the charge-pump is employed in [3] to cancel the modulator quantization noise in a fractional- PLL. In [4], a dedicated supply regulator is used to attenuate the RO supply noise at the cost of reduced supply voltage headroom and power efciency. An auxiliary circuit with inverse delay sensitivity to supply noise is used to compensate for the delay variation of inverter cells in [5]. In this paper, an online feed-forward phase-noise extraction and cancellation technique based on a delayed-discriminator phase detector is presented. The proposed circuit can attenuate the RO phase noise in an arbitrary band of interest. This approach can cancel both the ambient and inherent device noise without the need for online calibration. The cancellation path gain and bandwidth tracks process, voltage, and temperature variations (PVT). Due to gain and bandwidth tracking, a one-time calibration is sufcient. The implemented noise-cancelling loop can enable RO-PLL-based frequency synthesizers to be utilized in high-sensitivity applications requiring low phase noise, such as broadband tuners and RF transceivers. The remainder of this paper is organized as follows. Section II introduces the proposed PLL architecture. Section III shows the transistor-level implementations. Measurement results are presented in Section IV. Finally, Section V draws the conclusions. II. PROPOSED ARCHITECTURE A. Time Domain Noise Cancellation Analysis As shown in Fig. 1(a), in a free-running RO, each variable delay cell exhibits random phase error due to device, supply and substrate noise. When the RO VCO is locked within a PLL, the phase error accumulation is ltered by the PLL dynamics. As shown in Fig. 1(b), the dc and low-frequency components of the VCO control voltage determine the close-in phase noise. Within

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Fig. 1. Phase noise and jitter accumulation in (a) a free-running RO, (b) a phase-locked RO, and (c) in the proposed delay-discriminator-based noise cancellation architecture.

the PLL loop bandwidth, deviations of the VCO frequency is locked to the reference clock and is attenuated by the PLL loop gain. The phase noise of the VCO outside the PLL bandwidth is dominated by the ROs noise oor characteristic and our approach tries to address noise performance in this region. There are several techniques to measure the phase noise and jitter of integrated oscillators. In [1], a delay line and mixer (i.e., delay-line discriminator) was used to convert the instantaneous phase deviations of an oscillator to voltage deviations, enabling an on-chip real-time phase noise measurement. This technique does not require a spectrally clean reference clock and can extract the phase noise for a wide range of frequency offsets from the carrier frequency. As shown in Fig. 2, the proposed PLL utilizes a similar delay-line discriminator to measure the ROs instantaneous phase noise in a selected bandwidth and to cancel the phase noise with a voltage-controlled delay element outside the PLL. The delay element is matched with the VCO delays and tracks the PVT variations of the VCO. As shown in Fig. 1(c), the existing delay elements inside the RO can also be used for the delay-line discriminator delay line. The two inputs of the discriminator mixer shown in Fig. 1(c) and its delayed version . The are represented by and can be represented by signals (1) is the RO signal swing with oscillation frequency where . The spot phase noise can be represented by the peak sinu-

at a frequency offset , and is the RO soidal jitter level line delay. Assuming signal swing of the VCO for simplicity is represented unity , the output of the mixer as follows:

(2) As shown in (2), the mixer output contains the sum and difference of the delay chain signal phase terms. After ltering higher harmonics, the mixer output can be represented by

(3) where is the discriminator gain in V/rad. Assuming a quadrature phase shift between the two mixer inputs, where

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Fig. 2. Block diagram of the delay-discriminator-based feed-forward phase-noise cancellation PLL.

, and small phase-noise modulation index ( 0.2 rad), the bandpass lter (BPF) output is represented by

(4) Assuming a small-signal deviation, the small-signal transfer function for the discriminator becomes [1] (5) As shown in (5), the discriminator measures the RO phase noise at a given frequency offset, amplied by the RO delay and discriminator gain . It is important to note that a small quadrature error only impacts the gain of the discriminator path. Assuming an imperfect quadrature generation, , here represents the quadrature error, and the cancellation signal becomes

Assuming a static quadrature phase error , the cancellation signal only incurs a gain error, which can be calibrated at the factory. As shown in Fig. 2, a BPF is required to suppress the cancellation path icker noise. The high-pass lter before the cancellation delay element allows the PLL to control the dc and low-frequency VCO frequency shifts, which is important to set the steady state output frequency and reduce in-band phase noise. Therefore, in the proposed approach, the PLL controls the steady-state VCO frequency, while the cancellation path suppresses the far-out phase noise. In order to achieve effective phase-noise cancellation, the differential BPF output is inverted and applied to the auxiliary delay stage outside the PLL. In general, the VCO output phase without cancellation can be represented in the time domain by (8) The output of the cancellation delay cell becomes (9) is the auxiliary delay cell sensitivity in rad/V. As where discussed in Section IV, the gain of the delay discriminator path is designed to match the delay characteristics of the main VCO. As shown in (9), the VCO output phase noise within the BPF bandwidth is cancelled by the delay cell outside the VCO. B. Frequency-Domain Noise Cancellation Analysis

(6) Using small-signal approximation, the cancellation signal becomes

Fig. 3 shows a phase-domain linearized ac model of the active noise cancellation VCO within a PLL. In this model the feedforward path is represented by the mixer gain block , BPF transfer function and the auxiliary delay element delay . The input-referred noise of the VCO is represented by , and the PLL output phase noise after cancellation can be represented by (10)

(7)

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Fig. 3. PLL small-signal model for active noise cancellation.

Fig. 4. VCO contribution to PLL phase noise with and without active noise cancellation enabled.

As shown in (10), within the passband of , the phase noise of the VCO can achieve additional suppression. Typical ac response of the PLL with and without cancellation is shown in Fig. 4. It is important to analyze the phase-noise contribution of the cancellation loop to the PLL itself. Since the cancellation loop is online, its contribution to the overall noise oor should be negligible with respect to the VCO phase noise. Fig. 5 shows a linearized ac noise analysis of the VCO with an embedded feedforward path. Using cascaded noise analysis, the total noise voltage referred to the cancellation is represented by

where the gains of phase shifter, mixer, BPF, and VGA are , and , respectively, represented by and noise associated with these blocks are represented by , and , respectively. Expressing the open-loop VCO output phase-noise PSD as , the output phase noise after the feedforward path is added and becomes rad Hz (12)

represents the auxiliary stage voltage to delay charThe acteristics in s/V and is matched to the VCO delay cells, and , where is VCO delay chain gain represented by the derivative of with respect to control voltage [6] and is given by

(11)

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Fig. 5. Linearized ac noise model of cancellation loop.

tion is independent of voltage and temperature variations, which minimizes any further calibration. One-time calibration is performed to ensure that the feed-forward phase noise measurement chain gain to match the VCO gain. The gain is calibrated by sweeping VGA gain settings until a minimum phase noise at 1-MHz offset is achieved. After the calibration, the feed-forward path gain and VCO gain track each other across PVT, as described in Section III-B. It is important to note that the calibration is performed only on the gain and cancellation bandwidth of the path, and these settings are performed only on the BPF and the VGA driving the nal correction gain stage. The schematic of the proposed RO and delay-discriminator-based noise-cancelling loop is shown in Fig. 8. A. Active Inductor Ring Oscillator The RO is implemented with ve pseudo-differential variable delay inverter cells shown in Fig. 8. The delay cell topology uses active inductors to compensate for the parasitic capacitances [7] and increase the delay cell speed. Active inductors have several advantages over passive inductors, including substantial reduction in die area and minimum substrate noise coupling in comparison to passive inductors. However, they have signicantly higher active device noise in comparison to passive inductors. The noise-cancelling architecture is a very good candidate for this topology, since it suppresses the noise generated due to the active inductor devices in the band of interest. The active inductors are realized by MOS active loads Mn -Mn and variable resistors Mg -Mg . The inductance value is determined by the equivalent resistance at Mn -Mn gate. By adjusting the triode resistance , the effective impedance at the inverter is controlled as follows:

Fig. 6. Noise contribution of the feed-forward path in comparison to an openloop, uncancelled VCO and individual noise contributions of the cancellation loop.

when

(13) It is important to note that, for an is given by stage VCO, the VCO gain The stage delay time constant is represented by as (15)

(14) is VCO frequency in PLL when it is locked, and where represents the voltage to delay gain of the auxiliary delay cell used in cancellation. As shown in (14), the VCO frequency gain is times greater than the individual delay cell voltage characteristics, which reduces the noise contributions of the feed-forward path by . As shown in Fig. 6, the noise contribution of the feed-forward path to an open-loop, uncancelled VCO at 1-MHz offset is around 20 dB lower than the VCO itself. The feed-forward noise contribution is 12 dB lower than the cancelled VCO, ensuring no signicant noise impact on the overall VCO oor noise. III. NOISE CANCELLATION CIRCUIT IMPLEMENTATION Fig. 7 shows the block diagram of the proposed PLL with RO and adaptive feed-forward phase-noise-cancelling circuit. The noise-cancelling loop consists of an active polyphase lter for quadrature generation, discriminator mixer, BPF, and a variable gain amplier (VGA) for gain calibration. The cancella-

(16) From (16), inductance of the active inductor is directly tuned by varying resistance . Furthermore, active inductor load of delay cell is signicantly smaller than passive inductor load. The measured tuning curve of the oscillator is shown in Fig. 14. B. Feed-Forward Active Noise Cancellation Path As shown in the discriminator analysis, quadrature phase shift between the two mixer inputs, where , achieves maximum phase discriminator sensitivity and linearity at the mixer output. An active -C polyphase lter is used in the discriminator input to maintain quadrature operation at the mixer input. The implementation of the polyphase lter with constant Gm biasing is shown in Fig. 10. Following

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Fig. 7. Schematics of RO delay cells with active inductors and feed-forward noise-cancelling loop.

Fig. 8. RO delay cell with active inductors.

Fig. 10. Active polyphase lter with constant Gm biasing.

high phase discrimination linearity and low icker noise. The RC pole in the TIA feedback path determines the cancellation bandwidth and helps with rejection of higher harmonics at the mixer output. Fig. 11 shows the TIA used in the mixer. The combined gain of the active polyphase lter followed by the passive mixer is represented by as follows:
Fig. 9. Schematic of constant Gm biasing for PPF, TIA, and VGA.

(17) is the polyphase lter transconductance, and where is the passive mixer transimpedance gain. As shown in Fig. 9, the lter is kept constant by the beta-multiplier based biasing circuit, and the degeneration resistance is matched with . This ensures a process and temperature independent gain

the polyphase lter, fully differential double-balanced passive mixer with transimpedance amplier (TIA) provides a rst-order low-pass ltering and frequency discrimination. A passive mixer operating in triode mode is selected to achieve

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Fig. 11. Schematic of TIA stage amplier used in the BPF and mixer.

Fig. 12. Digitally controlled symmetric load VGA for phase-noise extraction gain calibration and its interface to cancellation delay cell.

Fig. 14. Frequency range with respect to control voltage across temperature and process.

Fig. 13. Die micrograph of the active noise-cancellation PLL.

for . The gain variation across 80 C is reduced from 2 dB down to 0.4 dB. The low-frequency component of the discriminator output is proportional to the steady-state frequency of the RO. Since the RO steady state frequency is determined by the PLL, the low frequency components of the cancellation path need to be ltered before it is applied to the VCO. As shown in Fig. 7, a DC feedback path through and removes DC components at the mixer output providing a high pass pole [8]. High-pass cut-off frequency of the proposed lter

is controlled by the of the feedback OTA and low-pass cut-off is controlled by 1/RC of the feed-forward TIA feedback network. To extend the bandwidth of the phase noise extraction path, either the transresistance gain needs to be reduced, which increases noise and increases the TIA power, or the TIA feedback capacitor should be reduced, which also increases the power consumption of the TIA to achieve dominant pole stability. The high-pass cut-off frequency of the BPF is controlled by changing transconductance and . In the proposed system, the HPF pole is placed around 20 kHz, and the low-pass pole of the BPF is at 20 MHz. A fully differential VGA provides a gain tuning for process variations in the variable-delay cell tuning characteristics. This gain adjustment is done once in a factory setting and can be xed for the regular operation. The gain matching of the feed-forward path is performed by sweeping VGA gain settings until a minimum phase noise at the BPF center frequency is achieved. The digitally controlled VGA that is used for this

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Fig. 15. Feed-forward cancellation path gain variation with and without conbias. stant

Fig. 17. PLL output PSD with 10-MHz digital divider modulation showing 13-dB spur reduction: (a) PSD without noise-cancelling loop and (b) PSD with the loop enabled.

path gain and VCO gain tracks each other across PVT as described. The calibration is only needed for the gain and cancellation bandwidth of the path. The cancellation voltage is used to modulate the delay of the cancellation element, using the same characteristics shown in (17). IV. MEASUREMENT RESULTS The proposed PLL has been fabricated in a 90-nm CMOS technology with 0.38 mm 0.32 mm core area. Fig. 13 shows the die micrograph. The PLL with cancellation loop enabled consumes 24.7 mA from a 1.2-V power supply. The implemented RO operates from 3.5 up to 7.1 GHz, and the output frequency is measured at 5.11 GHz with 512 divider ratio with a reference crystal frequency of 10 MHZ. Fig. 15 shows the improvement in the gain variation in the feed-forward cancellation path, including the VGA and the delay element using constant-Gm biasing. Fig. 17 shows the phase-noise measurements before and after enabling the cancellation loop. The measured phase noise reduces up to 20-MHz offset with a 200-kHz PLL loop bandwidth. As shown in Fig. 16, the cancellation loop attenuates the phase noise at 1-MHz offset by 12.5 dB to 105 dBc/Hz. As shown in [9], every 6-dB reduction in the oor noise of a VCO requires doubling of the VCO quiescent

Fig. 16. Measured PLL output phase noise with and without phase-noise cancellation at frequencies of (a) 4.9 GHz and (b) 5.2 GHz.

calibration and its interface to the delay cell is shown in Fig. 12. The VGA performs differential to single-ended conversion of the control signal, and adding the static offset bias from a replica bias of the RO. After initial gain calibration, the feed-forward

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loop reduces the 10-MHz reference spur tone by 13 dB. This result shows that the proposed architecture can also be used to mitigate out-of-band quantization noise of fractional- frequency synthesizers. The performance of the implemented PLL is summarized in the Table I. V. CONCLUSION An RO-based PLL with active noise cancellation is integrated in 90-nm CMOS process. The active noise-cancellation circuit measures and cancels the phase noise in a selected bandwidth by using a similar delay element as used in the main VCO. The feed-forward cancellation circuit tracks the process and temperature variations of the VCO delay element, requiring only a one-time gain adjustment. The proposed approach can suppress several ambient noise sources also, such as supply and substrate noise. A 12-dB phase noise reduction is achieved with only 35% increase in the VCO power and 17% increase in the overall PLL power. The measured phase noise at 1 MHz offset after enabling the feed-forward path is 105 dBc/Hz. The circuit performs over 12.5 dB of phase noise reduction at 10-MHz offset and 13 dB of reference spur rejection. REFERENCES
[1] W. Khalil, B. Bakkaloglu, and S. Kiaei, A self-calibrated on-chip phase-noise-measurement circuit with 75 dBc single-tone sensitivity at 100 kHz offset, in ISSCC Dig. Tech. Papers, 2007, pp. 546547. [2] A. Elshazly, R. Inti, W. Yin, B. Young, and P. K. Hanumolu, 0.4-to-3 GHz digital PLL with supply-noise cancellation using deterministic background calibration, in ISSCC Dig. Tech. Papers, 2011, pp. 9294. [3] H. Hedayati, B. Bakkaloglu, and W. Khalil, A 1 MHz bandwidth fractional-N synthesizer for WiMAX applications, in type-i ISSCC Dig. Tech. Papers, 2009, pp. 390391. [4] E. Alon, J. Kim, S. Pamarti, K. Chang, and M. Horowitz, Replica compensated linear regulators for supply-regulated phase-locked loops, IEEE J. Solid-State Circuits, vol. 41, no. 2, pp. 413424, Feb. 2006. [5] M. Mansuri and C.-K. K. Yang, A low-power low-jitter adaptivebandwidth PLL and clock buffer, in ISSCC Dig. Tech. Papers, 2003, pp. 430440. [6] S. Ye, L. Jansson, and I. Galton, A multiple-crystal interface PLL with VCO realignment to reduce phase noise, IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 17951803, Dec. 2002. [7] S. Hara, T. Tokumitsu, T. Tanaka, and M. Aikawa, Broadband monolithic microwave active inductor and its application to miniaturized wideband amplier, IEEE Trans. Microw. Theory Tech., vol. 36, no. 12, pp. 19201924, Dec. 1988. [8] R. Harjani, J. Kim, and J. Harvey, DC-coupled IF stage design for a 900-MHz ISM receiver, IEEE J. Solid-State Circuits, vol. 38, no. 1, pp. 126134, Jan. 2003. [9] T. C. Weigandt, Low-phase-noise, low-timing-jitter design techniques for delay cell based VCOs and frequency synthesizers, Ph.D. dissertation, Dept. Electr. Eng. Comput. Sci., Univ. California, Berkeley, CA, USA, 1998. [10] K. H. Cheng, Y. C. Tsai, Y. L. Lo, and J. S. Huang, 0.5-V 0.42.24-GHz inductorless phase-locked loop in a system-on-chip, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 58, no. 5, pp. 849859, May 2011. [11] Z.-Z. Chen and T.-C. Lee, The design and analysis of dual-delay-path ring oscillators, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 58, no. 3, pp. 470478, Mar. 2011. [12] L. H. Qi, G. W. Ling, S. Liter, L. W. Meng, and Z. Y. Ping, A lownoise multi-GHz CMOS multi-loop ring oscillator with coarse and ne frequency tuning, IEEE Trans. Very Large-Scale Integr. (VLSI) Syst., vol. 17, no. 4, pp. 571577, Apr. 2009. [13] H. Q. Liu, W. L. Goh, and L. Siek, A 0.18- m 10-GHz CMOS ring oscillator for optical transceivers, in Proc. IEEE Int. Symp. Circuits Syst., May 2005, vol. 2, pp. 15251528.

Fig. 18. Performance comparison of state-of-the-art ring oscillators with respect to the proposed approach, with and without active noise cancellation.

TABLE I PLL PERFORMANCE SUMMARY

current. Following this model, a 12-dB reduction in the VCO phase noise would require increase in the VCO power. The proposed approach achieves this reduction with only 35% increase in the VCO power and 17% increase in the overall PLL power to achieve this reduction. On the other hand, the adopted 90-nm CMOS node, the die area of the core VCO is increased by 50% due to the cancellation path. The die area overhead is mainly due to the tunable BPF. Fig. 18 shows the performance of the proposed approach with and without the feed-forward path enabled. The proposed approach can also be used in fractional- applications. Fig. 17 shows PLL output PSD before and after the cancellation when the feedback divider is modulated to achieve a fractional division. The cancellation

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Seungkee Min (M12) received the B.S. degree from Illinois Institute of Technology, Chicago, IL, USA, in 2004, and the M.S. degree from Pennsylvania State University, State College, PA, USA, in 2007, and the Ph.D. degree from Arizona State University, Tempe, AZ in 2011, all in electrical engineering. He is currently an RF Design Engineer with Freescale Semiconductor, Tempe, AZ, USA. His current research interests including RF and analog integrated circuits.

Tino Copani (A08) was born in Catania, Italy, in 1972. He received the Laurea degree in electronics engineering and Ph.D. degree in electronics and automation engineering from the University of Catania, Catania, Italy, in 1998 and 2004, respectively. From 2000 to 2004, he was with the Radio Frequency Advanced Design Group, a joint research group between the University of Catania and STMicroelectronics, where he was involved with the design and development of RFICs for satellite communications. In 2005, as a Post-Doctoral Research Associate, he joined Connection One Center, Arizona State University, Tempe, AZ, USA. Since December 2010, he has been with the Mixed Process Division, STMicroelectronics, Catania, Italy, where he is involved in the design of BiCMOS RFICs for wireless infrastructures. His current research interest is the design of VCOs, frequency synthesizers, and building blocks for low-power RFICs and MMICs.

Sayfe Kiaei (F12) received the Ph.D. degree from the University of Washington, Seattle, WA, USA, in 1987. He was a Senior Member of Technical Staff with the Wireless Technology Center and Broadband Operations at Motorola from 19932001 where he was responsible for the development of Wireless Transceiver ICs, and Digital Subscriber Lines (DSL) transceivers. Before joining Motorola, he was an Associate Professor with Oregon State University from 1987 to 1993, where he taught courses and performed research in digital communications, VLSI system design, advanced CMOS IC design, and wireless systems. He is currently a Professor and the Director of the Connection One Center (NSF I/UCRC Center) at Arizona State University, Tempe, AZ, USA, where he is also currently the Associate Dean of Research. Dr. Kiaei is a member of the IEEE Circuits and Systems Society, the IEEE Solid State Circuits Society, and the IEEE Communication Society. He has been on the technical program committee and/or chair of many conferences, including: RFIC, MTT, ISCAS, and other international conferences. He has published over 100 journal and conference papers and holds several patents and his research interests are in wireless transceiver design, RF and Mixed-Signal ICs in CMOS and SiGe. He was the recipient of the Carter Best Teacher Award of the Oregon State College of Engineering, the IEEE Darlington Award, and the Motorola 10X Design Award.

Bertan Bakkaloglu (M94SM08) received the Ph.D. degree from Oregon State University, Corvallis, OR, USA, in 1995. He joined the Mixes Signal Wireless Design Group, Texas Instruments, Inc., Dallas, TX, USA, where he was involved with analog, RF, and mixed-signal front-ends for wireless and wireline communication ICs. He worked on system-on-chip designs with integrated battery management and analog baseband functionality as a design leader. In 2004 he joined the Electrical Engineering Department, Arizona State University, Tempe, AZ, USA, as an Associate Professor. His research interests include RF and PA supply regulators, RF synthesizers, biomedical and instrumentation circuits and systems, high speed RF data converters and RF built-in-self-test circuits for communication ICs. Dr. Bakkaloglu is a technical program chair and steering committee member for IEEE RFIC conference and an associate editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS and the IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES.