Design and Implementation of 32 Bit Unsigned

Multiplier Using CLAA and CSLA

V.Vijayalakshmil, R.Seshadd, Dr.S.Ramakrishnan3
1
,
2
Arunai Engineering College,
3
Sakthi Mariannan Engineering College,
1
,
2
Tiruvanamalai,
3
Thandalam, Chennai.
I
viji5818@gmail.com,
2
seshadriaec@gmail.com,
3
jkang69@yahoo.com
Ahstact-This project deals with the comparison of the VLSI
design of the carry look-ahead adder (CLAA) based 32-bit
unsigned integer multiplier and the VLSI design of the carry
select adder (CSLA) based 32-bit unsigned integer multiplier.
Both the VLSI design of multiplier mUltiplies two 32-bit
unsigned integer values and gives a product term of 64-bit
values. The CLAA based multiplier uses the delay time of 99ns
for performing mUltiplication operation where as in CSLA
based multiplier also uses nearly the same delay time for
mUltiplication operation. But the area needed for CLAA
multiplier is reduced to 31 % by the CSLA based multiplier to
complete the mUltiplication operation. These multipliers are
implemented using Altera Quartus II and timing diagrams are
viewed through avan waves.
Keywords-CLAA; CSLA; Delay; Area; Array Multiplier;
VHL Modeling & Simulation.
T. INTRODUCTION
Digital computer aritmetic is an aspect of logic
design with the objective of developing appropriate
algoritms in order to achieve an effcient utilization of the
available hardware. The basic operations are addition,
subtraction, multiplication and division. In this, we are going
to deal with the operation of additions implemented to the
operation of multiplication. The repeated form of the
addition operations and shifing results in the multiplication
operations.
Given that the hardware can only perform a
relatively simple and primitive set of Boolean operations,
aritmetic operations are based on a hierarchy of operations
that are built upon the simple ones. In VLSI designs, speed,
power and chip area are the most ofen used measures for
determining the performance and effciency of the VLSI
architecture.
Multiplications and additions are most widely and
more ofen used aritmetic computations performed in all
digital signal processing applications. Addition is a
fndamental operation for any digital multiplication. A fast,
area effcient and accurate operation of a digital system is
greatly infuenced by the performance of the resident adders.
Adders are also very important component in digital systems
because of their extensive use in these systems.
In this project we are going to compare the
performance of different adders implemented to the
multipliers based on area and time needed for calculation.
On comparison with the carry look-ahead adder (CLAA)
based multiplier the area of calculation of the carry select
adder (CSLA) based multiplier is smaller and better with
nearly same delay time. Here we are dealing with the
comparison in the bit range of n*n (32*32) as input and 2n
(64) bit output.
Hence, to design a better architecture the basic
adder blocks must have reduced delay time consumption and
area effcient architectures. The demand is of DSP style
systems for both less delay time and less area requirement
for designing the systems. Our interest is in the basic
building blocks of arithmetic circuits that dominate in DSP
applications, VLSI architectures, computer applications and
where ever reduced area computation is needed.
IT. CARRY LOOK-AHEAD ADDER
Carry Look Ahead Adder can produce carries faster
due to parallel generation of the carry bits by using
additional circuity. This technique uses calculation of carry
signals in advance, based on input signals. The result is
reduced carry propagation time. For example, ripple adders
are slower but use the least energy.
Figurel. Carry Look-Ahead Adder
978-1-4673-5301-4/13/$31.00 2013 IEE
Let Gi is the carry generate fnction and Pi be the
carry propagate fnction, Then we can rewrite the carry
fnction as follows:
Gi = Ai Bi.
Pi = (Ai xor Bi).
Si = Pi xor Ci.
Ci+l= Gi + Pi.Ci.
(1)
(2)
(3)
(4)
Thus, for 4-bit adder, we can compute the carry for
all the stages as shown below:
C
1
= G
o + Po
.C
o.
(5)
C2 = G
1 + P1
.C
1
= G
1 + P1.
G
O + P1.PO.CO (6)
C3 = G
2 + P2.C2 = G
2 + P2.
G
1 + P2.P I.
G
O
+ P2.P1.PO.CO (7)
C4 = G
3 + P3.C3 = G
3 + P3.
G
2 + P3.P2 .
G
1 + P3.P2.P1.
G
O
+ P3.P2.Pl.PO.CO (8)
In general, we can write:
The sum fnction:
In general, we can write the algorithm as:
If Carry in =1, then the sum and carry out are given by,
Sum (i) =a (i) xor b (i) xor '1'. (11)
Carry (i+ 1) = (a (i) and b (i)) or (b (i) or a (i)). (12)
If Carry in =0, then the sum and carry out are given by,
The sum fnction:
Sum (i) = a (i) xor b (i).
Carry (i+ 1) = (a (i) and b (i)).
The carry fnction:
IV. MU TIPLTER FOR UNSIGNED DATA
(13)
(14)
(IS)
(16)
(9) Multiplication involves the generation of partial
The carry fnction:
Ci+l= Gi + Pi.Ci. (10)
T CAY SELECT ADDER
The concept of CSLA is to compute alterative
results in parallel and subsequently selecting the correct
result with single or multiple stage hierarchical techniques.
In CSLA both sum and carry bits are calculated for two
alteratives Cin=O and 1. Once Cin is delivered, the correct
computation is chosen using a mux to produce the desired
output. Instead of waiting for Cin to calculate the sum, the
sum is correctly output as soon as Cin gets there. The time
taken to compute the sum is then avoided which results in
good improvement in speed.
Cin
S7:4 5:0
Figure2. Carry Select Adder
products, one for each digit in the multiplier, as in
Figure3.These partial products are then summed to produce
the fnal product. The multiplication of two n-bit binary
integers results in a product of up to 2n bits in length [2].
b (0)
b (1)
b (2)
b (31)
32
ro(63 dowto 32)
prod(31 ) [rod(O)
Figure3. A partial schematic ofthe multiplier
We used the following algorithm to implement the
multiplication operation for unsigned data.
v. MULTIPLICATION ALGORITHM
Let the product register size be 64 bits. Let the
multiplicand registers size be 32 bits. Store the multiplier in
the least signifcant half of the product register. Clear the
most signifcant half of the product register.
Repeat the following steps for 32 times:
1. If the least signifcant bit of the product register is "1"
then add the multiplicand to the most signifcant half of the
product register.
2. Shif the content of the product register one bit to the right
(ignore the shifed-out bit.)
3. Shif-in the carry bit into the most signifcant bit of the
product register. Figure 4.Shows a block diagram for such a
multiplier [2].
Multiplicand
Shland Add
Con 11'01 Luge
Figure4. Multiplier oftwo n-bit values.
VI. VHDL SIMULATIONS
The VHL simulation of the two multipliers is
presented in this section. T this, waveforms, timing
diagrams and the design summary for both the CLAA and
CSLA based multipliers are shown in the fgures. The
VHL code for both multipliers, using CLAA and CSLA,
are generated. The VHL model has been developed using
Altera Quartus IT and timing diagrams are viewed through
avan waves. The multipliers use two 32-bit values.
40.0ns 50ns 601
I I I
J16/6/1JJ
X
1/w1
1
wJ111
)
11MJ/1MJ
X
1W1JJ1
1
1Ww
)
JJ11JJ1/1W JJ11 X !161wJ /11111J
+
J61J11J111MJ61/1
)
FigureS. Waveform for a CLAA based multiplier
40.0ns 5.0ns 61
I I
J!6/6/!JJ
1
1/!
X
111
11MJ/!MJ 1W1JJ1
X
1W
1J11JJ1/1W JJ/1 t 16!/J/1!11!
X
J61J11J1!1MJ61/1
Figure6. Waveform for a CSLA based multiplier
Timing Anale Summar
Ty Slk
.. .
1 Worscae t /A
Rered
I If IT
Ti Ti
ro 0
fro
I
To
C Cb
Noe
T9.5b a] -"IS] ..
}
Figure7. Timing Analysis for CLAA based multiplier
Timing Analer Summar
Type Slack
Required Actual
From To
From To
Time Time Clock Clock
I Worstcase tpd NIA None 99.553 m all] suml63] .. ..
FigureS. Timing Analysis for CSLA based multiplier
Fd
P
0
Failed
Paths
0
Quartus II Version
Revision Name
8.1 Build 16 101280 SJ Web Edion
CLAuttiplier
Top-evel Entr Name CLultiplier
Family Cyclone II
Device EP=3F6726
Timing Models Rnal
Met timing requirements Yes
Total logic elements 2.97/3.216 (9 %)
Total combinational functions 2.957 I 3.216 (9 %)
Dedicated logic register 0 / 3.216 ( 0 % )
Total registers 0
Total pins 129 / 475 (27 %)
Total virual pins 0
Total memory bs 0/48.8 (0 %)
Ebedded Multiplier 9i elements 0 / 70 ( 0 % )
Total PLLs 0/4(0%)
Figure9. Design summary ofCLAA multiplier
I
j
Quartus II Verion
Revision Name
T opevel Enity Name
Family
Device
Timing Models
8.1 Build 16 101280 SJ Web Edion
cs amultiplier
csamultiplier
Cyclone II
EP23F6726
Rnal
Met timing rquirements Yes
Total logic elements 2,039/3.216 (6'4)
Total combinational functions 2,0 / 3.216 ( 6 +4)
Dedicated logic register 0 / 3.216 ( 0 % )
Total registers 0
Total pins 129/475 ( 27 %)
Total virtual pins 0
Total memory bs 0 1 4,8 ( 0 ". )
Embedded Muiplier 9 elements 0 I 70 ( 0 '4 )
Total PLLs 0/4(0%)
FigurelO, Design summary ofCSLA multiplier
Under the worst case, the multiplier with a carry
look-ahead adder uses time = 98.5 ns, while the multiplier
with the carry select adder uses time = 99.5 ns.
VII, PERORACE AALYSTS
A. Area Analysis
The performance analysis for the area of CLAA and
CSLA based multipliers are represented i the form of the
diagram shown i fgure II.
Figure I I , Area analysis chart
B. Dela Analysis
The performance analysis for the delay time of
CLAA and CSLA based multipliers are represented i the
form of the diagram shown i fgure 12.
CLAA CSLA
Figure I 2, Delay analysis chart
C.Area Delay Product Analysis
The performance analysis for the area delay product
of CLAA and CSLA based multipliers are represented i the
form of the diagram shown i fgure13.
CLAA
Figure I 3, Area delay product analysis chart
The area needed and delay for both the CLAA and
CSLA implemented to the multiplier was analyzed and the
comparison was shown i the fgure 14 i the form of a table.
D.Analysis Table
Tn this analysis table shown i fgurel4, the delay
time is nearly same, the area and the area delay product of
CSLA based multiplier is reduced to 31 % when compared to
CLAA based multiplier.
Figurel4. Analysis Table
Multiplier type
Delay Delay Area
Area
(ns) Product
CLAA based
2957
multiplier
98. 5 logic 291264.5
cells
CSLA based
2039
multiplier
99. 5 logic 202880.5
cells
VITI. CONCLUSION
A design and implementation of a VHDL-based 32-
bit unsigned multiplier with CLAA and CSLA was
presented. VHL, a Very High Speed Integrated Circuit
Hardware Description Language, was used to model and
simulate our multiplier. Using CSLA improves the overall
performance of the multiplier.
Thus a 31 % area delay product reduction is
possible with the use of the CSLA based 32 bit unsigned
parallel multiplier than CLAA based 32 bit unsigned parallel
multiplier.
IX. FUTURE WORK
This 32 bit multiplier can be frther extended to 64
bit multiplier and 128 bit multiplier using the proposed
method for multiplication operation can be done as fture
work.
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h
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Dr.S.Ramakrishnan was born in Tirunelveli, India in 1969. He
received his Bachelors of Engineering degree fom the deprment
of Electronics and Instrumentation fom Annamalai University,
Chidambaram, India and Masters Degree & Ph.D in Electrical
Engineering fom Anna University, Chennai India. He has over 15
years of teaching experience afer 5 years experience in the
industry. He is currently working as Principal & HeadDeprment
of IT in Sakthi Mriamman Engineering College, Chennai,
India.He is the member of IEE & ITE. He has published in many
peer refeled interational and national journals and conferences.
Mr.R.Seshadri received the B.E and M.E degrees, both in
Electronics and communication engineering fom the S.K.P
Engineering College, Tiruvannamalai, Tamilnadu, India. He has
doing the Ph.D degree in Digital Signal Processing Architecture
at Anna University, India. Currently, he is working as a Assistant
Professor in Arunai Engineering College, Tiruvannamalai,
Tamilnadu, India. He has having 4 years of teaching Experience.
V.Vijayalakshmi was born on October 12, 1990 in
Tiruvannamalai, Tamilnadu, India. She has received the B.E degree
in Electrical and Electronics Engineering from Arunai College of
Engineering, Anna University, Chennai, Tamilnadu, India, in May
2011. She is currently pursuing her M.E degree in Applied
Electronics fom Arunai Engineering College, Anna University,
Chennai, Tamilnadu, India from 2011 to 2013. She has published a
journal in National conference conducted by Sri Balaji
Chockalingam Engineering College on January, 2013. Her areas of
interest include VLSI and Control Systems.