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Buscar:Search <#>Advanced Search <search.jspa?firstLoad=1> Analog Devices Worldwide Technical Support <http://www.analog.com/en/content/technical_support_page/fca.html> EngineerZone <http://ez.analog.com/welcome> Todos los lugares </places> Direct Digital Synthesis (DDS) </community/dds> Discusiones </community/dds/content?filterID=content~objecttype~objecttype[thread]> Ingrese un ttulo. No puede publicar un mensaje en blanco. Ingrese su mensaje y vuelva a intentar. *11 Respuestas* Respuesta ms reciente </message/19939?tstart=0#19939>: 24/02/2011 09:27 PM por Radarsign RSS </community/feeds/messages?thread=5197> AD9958 non-documented startup issue </message/16378#16378> Esta pregunta es una *supuesta respuesta.* Radarsign </people/Radarsign> Member *Radarsign </people/Radarsign>* 2/12/2010 08:22 AM Actualmente moderados A AD9958 is being used as a quadrature generator for radar testing. None of the modulation capabilities of this part are being used. The part did produce very nice sine waves but a recent code change caused the output to disappear. A SPI logic probe verified that the device was receiving the proper initialization code, same code as when the part produced an output. Register values are below.

freqh = $0040 freql = $0fb9 ' 33.333Mhz for 32583hz output default

phase = $0000 CSR = $c2 ' FR1a = $00 ' FR1b = $0000 FR2 = $0040 CFRa = $00 CFRb = $0201 ACRa = $00 ACRb = $13FF

' phase in MSB 14 bits ch0=$42, ch1=$82, both=$c2 temp set so PLL is off

' $0300=200mV, $0200=50mV, SINE ' Max amplitude

A 5us positive going pulse on IO_UPDATE at the completion of the register data load sends the values to the core.

We went back to the code change and discovered that we had terminated SYNC_IO ((SDIO_3) low as we were in 2 bit serial comm mode and we did not need to terminate a serial command early. This should be the proper termination for this pin in such cases but this was the cause of the output not being updated. See page 31, left column, paragraph 6 of the data sheet.

Examining the prior working code we observed that SDIO_3 was high during the 5ms reset pulse and when brought low after the reset but before the DDS' chip select was brought low. This enables the proper output signal to be generated but is not in the documentation. Terminating SDIO_3 high or low causes the output to not function. It seems to need to be high and then go low to enable proper operation.

What is the proper sequence of signals to properly bring up the device with SDIO_3, Master Reset, and IO_UPDATE? None of the timing diagrams in the data sheet seem to show this requirement of SYNC_IO needing to have a high to low transition.

A schematic is attached.

Charles Jenkins Radarsign * HTX TEST Quadrature Gen D.pdf </servlet/JiveServlet/download/16378-4495/HTX%20TEST%20Quadrature%20Gen%20D. pdf> (279.1 K) * 3671 Vistas * Etiquetas: ninguno (agregar <#>) quadrature </community/dds/tags#/?tags=quadrature>, dds </community/dds/tags#/?tags=dds>, ad9958 </community/dds/tags#/?tags=ad9958>, sync_io

</community/dds/tags#/?tags=sync_io> * *1. </message/16398#16398> Re: AD9958 non-documented startup issue </message/16398#16398> * Georgy </people/Georgy> Regular Contributor *Georgy </people/Georgy> * 2/12/2010 11:23 AM (en respuesta a Radarsign </message/16378#16378>) Actualmente moderados Hi, Radarsign! I hope only one CLK used with? (There are two CLKs = 20 MHz and 33,333 MHz)/ And R208 (A...D) resistance? Not large? This ones may be in the way programing. o Reportar abuso </message-abuse!input.jspa?objectID=16398&objectType=2> o Me gusta (0 <#>) * *2. </message/16424#16424> Re: AD9958 non-documented startup issue </message/16424#16424> * Radarsign </people/Radarsign> Member *Radarsign </people/Radarsign> * 2/12/2010 03:06 PM (en respuesta a Georgy </message/16398#16398>) Actualmente moderados Hello Georgy

Thank you for your insight. The two clocks are options. Of course only one at a time :-). R208 is 10K and is just for unknown options if needed. Easier to overdrive a resistor than cut a trace. Since the IO functions of these pins are not programmed their termination should not matter.

As far as programming is concerned the same code was used to produce a sine wave or produce a zero output (no current sinks operating DC level on output is 1.8V). The only difference is in how I manipulated the SDIO_3 while in 2 wire mode. In this mode SDIO_3 is

supposed to be used to stop a register load at some time before the end if brought high so I figured terminating it low was best if that function is not needed. Termination low means no putput. Same with termination high. Only if it transitions high to low does the output function. This is what I am curious about. No info on this in the data sheet.

From: Georgy Shebetovskiy analog@sgaur.hosted.jivesoftware.com <mailto:analog@sgaur.hosted.jivesoftware.com> Sent: Thursday, December 02, 2010 11:23 AM To: Charles Jenkins Subject: Re: AD9958 non-documented startup issue <http://ez.analog.com/message/16424#16424> New message: "AD9958 non-documented startup issue" Re: AD9958 non-documented startup issue <http://ez.analog.com/message/16424#16424>

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AD9958 non-documented startup issue

reply from Georgy <http://ez.analog.com/people/Georgy> Shebetovskiy in Direct Digital Synthesis (DDS) - View the full discussion <http://ez.analog.com/message/16398#16398 o Reportar abuso </message-abuse!input.jspa?objectID=16424&objectType=2> o Me gusta (0 <#>) *

*3. </message/16449#16449> Re: AD9958 non-documented startup issue </message/16449#16449> * Georgy </people/Georgy> Regular Contributor *Georgy </people/Georgy> * 3/12/2010 04:39 AM (en respuesta a Radarsign </message/16424#16424>) Actualmente moderados Hi, *Radarsign*! None the less this resistance will be no more 1000 Ohm IMHO. (I know, MK with shorted data pin no worked.)

Regards! o Reportar abuso </message-abuse!input.jspa?objectID=16449&objectType=2> o Me gusta (0 <#>) * *4. </message/16563#16563> Re: AD9958 non-documented startup issue </message/16563#16563> * DSB </people/DSB> Analog Employee *DSB </people/DSB> * 6/12/2010 04:51 PM (en respuesta a Radarsign </message/16378#16378>) Actualmente moderados Hi Radarsign,

After power up, you should send a master reset to the AD9958. The master reset is an ansynchronous operation. A master reset sets the registers to their default state. See the register map for default register settings on pages 36 - 38.

Note, the default state for the serial port interface is single-bit two wire mode. In this mode, you must control the SDIO_3 line at all times. You could hardwire SDIO_3 low, if not used. There should be no reason for the SDIO_3 to toggle high then low or vica versa if not used. If you want to change communication to (single-bit three wire mode, or dual mode or 4 bit mode), you should first write to the CSR register and IO_UPDATE. Then continue programming in whatever serial interface mode desired.

There is a note in the data sheet (on page 33, 2nd column six

paragraph) concerning the importance of controlling SDIIO_3. See the following note below. This should extend to 2 wire mode and single-bit 3 wire mode also.

When programming the device for 4-bit serial mode, it is important to keep the SDIO_3 pin at Logic 0 until the device is programmed out of the single-bit serial mode. Failure to do so can result in the serial I/O port controller being out of sequence.

Note, I purposely shorted SDIO_3 and change from default to single-bit three wire mode and 2 bit mode and it worked as expected.

I hope this helps.

o Reportar abuso </message-abuse!input.jspa?objectID=16563&objectType=2> o Me gusta (0 <#>) * *5. </message/16574#16574> Re: AD9958 non-documented startup issue </message/16574#16574> * Radarsign </people/Radarsign> Member *Radarsign </people/Radarsign> * 6/12/2010 06:50 PM (en respuesta a DSB </message/16563#16563>) Actualmente moderados Your suggestions are right on and exactly what I expected with the exception of the last line.

A 5uS pulse is sent to MSTCLR

Register $00 is set for 3 wire com.

Each register setting after that has a high to low CS transition with a return to high at the completion of the register serial programming. We are not in need of truncating the serial string.

Each register program is separated by 100uS

After the last register is programmed we do a 5uS IO_Update and expect to see output from the DACs.

In our first code that worked SDIO_3 was high during reset and brought low a short time later. 10mS after SDIO_3 was brought low the register programming starts.

We then cleaned up a few port pins by recovering the drive to SDIO_3. We tied this line low. No output. We tied it high. No output. We set it high, reset the part and set it low. We got output.

I will be moving this around tomorrow to verify. I will also switch to 2 wire and see if it makes a difference. We never do a read command so it should not affect the current code.

I am also going to try a long CS that lasts the duration of all the register programming and see if that affects anything. How did you configure your CS for the register programming?

From: DSB analog@sgaur.hosted.jivesoftware.com <mailto:analog@sgaur.hosted.jivesoftware.com> Sent: Monday, December 06, 2010 4:52 PM To: Charles Jenkins

Subject: Re: AD9958 non-documented startup issue <http://ez.analog.com/message/16574#16574> New message: "AD9958 non-documented startup issue" Re: AD9958 non-documented startup issue <http://ez.analog.com/message/16574#16574>

<http://ez.analog.com/index.jspa> Analog Devices EngineerZone

AD9958 non-documented startup issue

reply from DSB <http://ez.analog.com/people/DSB> in Direct Digital Synthesis (DDS) - View the full discussion <http://ez.analog.com/message/16563#16563 o Reportar abuso </message-abuse!input.jspa?objectID=16574&objectType=2> o Me gusta (0 <#>) * *6. </message/16613#16613> Re: AD9958 non-documented startup issue </message/16613#16613> * DSB </people/DSB> Analog Employee *DSB </people/DSB> * 7/12/2010 09:01 AM (en respuesta a Radarsign </message/16574#16574>) Actualmente moderados I used the AD9958 evaluation board and software. As a result, the pulse widths of the CSB line varies all around depending on what's been programmed. It's also different between computers and their clock speeds. However, if you have good control of the SPI lines, the CSB line could be tied low all the time. The CSB feature was implemented for multiple parts sharing the same SPI interface lines. This to pick and choose the device to program.

o Reportar abuso </message-abuse!input.jspa?objectID=16613&objectType=2> o Me gusta (0 <#>) * *7. </message/17315#17315> Re: AD9958 non-documented startup issue </message/17315#17315> * Johann </people/Johann> Member *Johann </people/Johann> * 21/12/2010 05:26 PM (en respuesta a Radarsign </message/16378#16378>) Actualmente moderados Hello everybody!!

I`ve just logged in because I want you to support me please!! I am working with the ad9958 and I've reviewed datasheet over and over and I have the same problem!! I did not get the frequency output that I want. I am using the single bit two-wire configuration but I do not have an analyzer so I cannot see the entire communication between the software and the eval board. I am using an external microcontroller and I first send a master reset pulse, then an IO_UPDATE pulse and then I am only sending the tuning word (It is supposed I am in the default mode). When I saw that anything happens, I started to access register by register till the register 04, after that I send the IO_UPDATE signal but I still have the same problem. After that I started to use the SDIO_3, when accesing each register I toggle first SDIO_3 and then CS, do I have to send an IO_UPDATE at each register configuration?? An interesting point is what Radar mentions, the question is, in the first RESET pulse, do I have only to put in high SDIO_3 and then to put it in low state?? or in each process.

Thanks a lot!!!

Regars!! o Reportar abuso </message-abuse!input.jspa?objectID=17315&objectType=2> o Me gusta (0 <#>) * *8. </message/17331#17331> Re: AD9958 non-documented startup issue </message/17331#17331> * Radarsign </people/Radarsign> Member *Radarsign </people/Radarsign> * 21/12/2010 09:49 PM (en respuesta a Johann </message/17315#17315>) Actualmente moderados I found, and have not had time to test thoroughly, that in two or three wire mode, SDIO_3 needs to be high at the master reset to the 9958 and then go low after the reset. It should stay low for the remainder of the com cycle.

I thought that CS should go low at the start of the first register access and then stay low for all other accesses. While debugging another issue below I put in a CS cycle (high low high) at each register access but I think this is redundant. For systems that have no other devices on the spi data or clock, ADI says that CS can be tied low. In keeping with good SPI design practice I control it like any SPI peripheral.

My first experience with the part produced no output even though the SDIO_3 action referenced above was taking place. I had used another device as a guide to the output filter and forgot that this part has open drain current sources. I was terminating the DACs to ground! That will not work with the 9958. The DACs are current sink only and need pull ups. 50 ohms to 1.8V on the positive output and 25 ohms to 1.8V on the negative output works. See if you are feeding the DACs some current if your SPI is working like described above.

From: Johann analog@sgaur.hosted.jivesoftware.com <mailto:analog@sgaur.hosted.jivesoftware.com> Sent: Tuesday, December 21, 2010 5:27 PM To: Charles Jenkins Subject: Re: AD9958 non-documented startup issue <http://ez.analog.com/message/17331#17331> New message: "AD9958 non-documented startup issue" Re: AD9958 non-documented startup issue <http://ez.analog.com/message/17331#17331>

<http://ez.analog.com/index.jspa> Analog Devices EngineerZone

AD9958 non-documented startup issue

reply from Johann <http://ez.analog.com/people/Johann> in Direct Digital Synthesis (DDS) - View the full discussion <http://ez.analog.com/message/17315#17315 o Reportar abuso </message-abuse!input.jspa?objectID=17331&objectType=2> o Me gusta (0 <#>) * *9. </message/17345#17345> Re: AD9958 non-documented startup issue </message/17345#17345> * Johann </people/Johann> Member *Johann </people/Johann> * 22/12/2010 10:12 AM (en respuesta a Radarsign </message/17331#17331>) Actualmente moderados Hi Radarsign!

I am going to try doing what you told me about SDIO_3 in the master reset event. I think I should not have problem with the DAC's due to the first step of my project is by using the eval board, even so, I will check it. I've got another doubt about you mentioned before, when you said that you cleaned up some port pins for recovering the drive of the SDIO_3, did you do that process before or after having programmed the registers?

Thanks for your answer and I hope you can continue helping me!

Regards! o Reportar abuso </message-abuse!input.jspa?objectID=17345&objectType=2> o Me gusta (0 <#>) * *10. </message/19917#19917> Re: AD9958 non-documented startup issue </message/19917#19917> * Johann </people/Johann> Member *Johann </people/Johann> * 24/02/2011 01:16 PM (en respuesta a Johann </message/17345#17345>) Actualmente moderados Hi again Radarsign!

I still have the same problem with the AD9958, I have decided not to use the evalboard. I think it will be better if I do the PCB with the chip, but I am now facing another problem, I am doing the design in Altium and I saw that the schematic that you shared us, is done in the same software. . . so, could you share the schematic and the footprint? Because I reviewed in the Analog Devices web and they dont have it.

I will be grateful with you.

Regards! o Reportar abuso </message-abuse!input.jspa?objectID=19917&objectType=2> o Me gusta (0 <#>) * *11. </message/19939#19939> Re: AD9958 non-documented startup issue </message/19939#19939> * Radarsign </people/Radarsign> Member *Radarsign </people/Radarsign> * 24/02/2011 09:27 PM (en respuesta a Johann </message/19917#19917>) Actualmente moderados You can reply to me at refd123 and I will send the Altium files. This is a gmail account.

I have included the picbasic code I used to test the DDS. It turns out that SDIO_3 can be tied low, the DDS reset and then a standard SPI interface started composed of a high to low CS then the clocking out of ALL the register data. The final operation is to raise CS and then send a pulse to IO Update to send the shift registers to the DACs.

'*****************

' DDS setup variables

'*****************

freqh

var word

' freq set bits 32-16

freql

var word

' freq set bits 15-0

phase

var word

' phase set bits 13-0

CSR var byte ch1=$82, both=$c2)

' Channel Select bits 7-0 (ch0=$42,

'b7

channel 1 enable

'b6

ch 0 enable

'b5

'b4

'b3

'b2:1

00 single serial mode 2 wire

' (SPI)

01 single serial mode 3 wire

'

10 2 bit serial

'

11 4 bit serial

'b0

1 = LSB first

FR1a

var byte

' Function Reg bits 23-16 ($14)

'b23

VCO gain (0= sysclk<160Mhz)

'b22:18 PLL divider 4 to 20

'b17:16 Charge pump (00=75uA)

FR1b

var word

' FR1 bits 15-0 ($0000)

'b15

'b14:12 profile pin config (000)

'b11:10 RU/RD control (00)

'b9:8

Modulation level (00)

'b7

Reference clock (0)

'b6

Ext pwr down (0)

'b5

SYNC_CLK on (0)

'b4

DAC ref enabled (0)

'b3:2

00

'b1

hdwr sync off (0)

'b0

software sync off (0)

FR2

var word

' FR2 bits 15-0 ($0040)

'b15 IOUPDATE (0)

Load word not applied until

'b14

normal sweep accum. (0)

'b13

load phase but not update (0)

'b12

normal phase accum (0)

'b11:8 0000

'b7

auto sync disable (0)

'b6

sync out active (1)

'b5

sync status (read)

'b4

Mask b5 (0)

'b3:2

00

'b1:0

Clock offset (00)

CFRa

var byte

' CFR bits 23-16 ($00)

'b23:22 Sweep type

'

00 N/A

'

01 Amplitude Sweep

'

10 Frequency Sweep

'

11 Phase Sweep

'b21:16 000000

CFRb

var word

' CFR bits 15-0 ($0300)

'b15

L sweep no-dwell off (0)

'b14

L sweep enable off (0)

'b13 off (0)

load L sweep ramp w IOUPDATE

'b12:11 00

'b10

'b9:8

DAC FS current (max 11)

'b7

Digital core power down off (0)

'b6

DAC power down off (0)

'b5

Match pipe delay off (0)

'b4

Sweep Accum clear off (0)

'b3

Clear Sweep off (0)

'b2

Auto Phase clear off (0)

'b1

Clear Phase off (0)

'b0

Channel is Cosine (0), Sine (1)

CFRTMP

var word

'temp storage for CFRb

ACRa

var byte

' Amplitude Control Reg bits 23-16 ($00)

'b23:16 Ramp Rate (00000000)

ACRb

var word

' ACR bits 15-0 ($1200)

'b15:14 incr/decr step size (00)

'b13

'b12

amp multi enable on (1)

'b11

RU/RD enable off (0)

'b10

ARR load at IOUPDATE off (0)

'b9:0 sets output amplitude

Amplitude scale (1000000000)

setdds:

' set up DDS both channels settings.

' If channel 0 is Sine and channel 1 is Cosine SUM1 will be larger than SUM2.

low OE12 before DDS reset

' have SDIO_3 low

pauseus 100

pulsout MSTRST,50

' Reset DDS 50uS

pauseus 100

' wait .1mS

low

OE12

low DDSCS spiby bringing CS low

' enable DDS

shiftout MOSI, SCLK,1,[$00,CSR]

'set channels (both)

'

high

DDSCS

pauseus 100

' wait 100uS

'

low

DDSCS

shiftout MOSI, SCLK,1,[$01,FR1a,FR1b\16]

'set FR1

'

high

DDSCS

pauseus 100

'

low

DDSCS

shiftout MOSI, SCLK,1,[$02,FR2\16]

'set FR2

'

high

DDSCS

pauseus 100

'

low

DDSCS

shiftout MOSI, SCLK,1,[$03,CFRa,CFRb\16]

'set CFR SINE

'

high

DDSCS

pauseus 100

'

low

DDSCS

shiftout MOSI, SCLK,1,[$04,freqh\16,freql\16]

'set frequency

'

high

DDSCS

pauseus 100

'

low

DDSCS

shiftout MOSI, SCLK,1,[$05,phase\16]

'set phase

'

high

DDSCS

pauseus 100

'

low

DDSCS

shiftout MOSI, SCLK,1,[$06,ACRa,ACRb\16]

'set amplitude

'

high

DDSCS

pauseus 100

CSR = $82 1 for COS (ch0 SINE)

'set up channel

CFRTMP = CFRb-1

'COS wave on

'

low

DDSCS

shiftout MOSI, SCLK,1,[$00,CSR]

'

high

DDSCS

pauseus 100

'

low

DDSCS

shiftout MOSI, SCLK,1,[$03,CFRa,CFRTMP\16]

high

DDSCS

`DDS CS back high

pulsout IOUPDATE,50

'send to DAC

I will leave the details of PICBASIC to you or anyone else. Details are at www.melabs.com.

Charlie

From: Johann analog@sgaur.hosted.jivesoftware.com <mailto:analog@sgaur.hosted.jivesoftware.com> Sent: Thursday, February 24, 2011 1:17 PM To: Charles Jenkins Subject: Re: AD9958 non-documented startup issue <http://ez.analog.com/message/19939#19939> New message: "AD9958 non-documented startup issue" Re: AD9958 non-documented startup issue <http://ez.analog.com/message/19939#19939>

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AD9958 non-documented startup issue

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