Chapter 1: Field Programmable Gated Array (FPGA) Overview

Field Programmable Gate Arrays (FPGAs) are programmable semiconductor devices that are based around a matrix of Programmable Logic Blocks connected through programmable interconnects. As opposed to Application Specific Integrated Circuits (ASICs), where the device is custom built for the particular design, FPGAs can be programmed to the desired application or functionality requirements. Advantages of FPGAs include the ability to re program in the field to fix bugs, and may include a shorter time to market and lower nonrecurring engineering costs FPGAs were first introduced almost two and a half decades ago. Since then they have seen a rapid growth and have become a popular implementation medium for digital circuits. Flexible nature of FPGAs makes them significantly larger, slower, and more power consuming than their ASIC counterparts. These disadvantages arise largely because of the programmable routing interconnect of FPGAs which comprises of almost 90% of total area of an FPGA. An older study [23] had shown that designs implemented on FPGAs need on average 40 times as much area, draw 12 times as much dynamic power, and run at one third the speed of corresponding ASIC implementations. The advancement in process technology has greatly enhanced the logic capacity of FPGAs and has in turn made them a viable implementation alternative for larger and complex designs. Further, programmable nature of their logic and routing resources has a dramatic effect on the quality of final devices area, speed, and power consumption. In the following section, we summarily describe the architecture of FPGA and its primary building blocks. We will use the terminology used by Xilinx FPGAs which we have used for our implementation.

1.1. FPGA Architecture

The basic building blocks of an FPGA are CLBs (Configuration Logic Blocks), Slices and LUTs (Look-Up Tables). Figure 1-1 is a simplified schematic of the CLB, Slice, LUT and flip-flops. There are thousands of CLBs in an FPGA connected through programmable interconnects. The CLBs are the main logic resources for implementing sequential as well as combinatorial circuits. Each CLB element is connected to a switch matrix for access to the general routing matrix (shown in Figure 1-1). A CLB element contains a pair of slices. These two slices do not have direct connections to each other, and each slice is organized as a

column.

Every slice contains four logic-function generators (look-up tables or LUTs),

eight storage elements (Flip-Flops), wide-function multiplexers, and carry logic. The number of slices in an FPGA varied depending on the part number and determines the logic capability of the device. For example, Xilinx Virtex-6 240T FPGA contains 37,640 slices. The function generators in Virtex-6 FPGAs are implemented as six-input look-up tables (LUTs). The function generators can implement any arbitrarily defined six-input Boolean function. Each function generator can also implement two arbitrarily defined fiveinput Boolean functions, as long as these two functions share common inputs.

Figure 1-1. Arrangement of CLBs, Slices, LUTs and Flip-Flops in an FPGA

While the CLB provides the logic capability, flexible interconnect routing routes the signals between CLBs and to and from I/Os. The routing interconnect of an FPGA consists of wires and programmable switches that form the required connection. The routing interconnect of an FPGA must be very flexible so that it can accommodate a wide variety of circuits with widely varying routing demands. Although the routing requirements vary from circuit to circuit, certain common characteristics of these circuits can be used to optimally design the routing interconnect of FPGA architecture. For example, most of the designs exhibit locality, hence requiring abundant short wires. But at the same time there are some distant connections, which leads to the need for sparse long wires. The arrangement of

routing resources, relative to the arrangement of logic blocks of the architecture, plays a very important role in the overall efficiency of the architecture. FPGAs also provide support for dozens of I/O standards thus providing the capability to connect to different components and Integrated Circuits (ICs). Embedded Block RAM memory is available in most FPGAs, which allows for on-chip memory in the design. The on-chip memory can operate at very high speed and provide very low latency, but is generally a scarce resource. Some of the LUTs can also be used as a memory element when configured as distributed block RAM. FPGAs also provide embedded phase-locked loops (PLLs) that enable generation of desired high-speed frequencies from a single clock source. Also, there are dedicated clock routing within the FPGA to ensure that clock signals do not experience significant skew while travelling from one end of the FPGA to another.

1.2. FPGA Design Flow

FPGA design is generally large and complex and requires the help of electronic design and automation (EDA) software. These EDA software automatically take care of the routing and timing considerations within an FPGA based on the constraints given by the user and make the task of implementing a digital circuit on an FPGA relatively straightforward.
Define requirements

HDL based design

Simulation

Synthesis

Translate

Map

Place & Route

Configure FPGA

Generate Bitstream

Figure 1-2. FPGA design process

Coding for FPGA is done using Hardware description languages like VHDL and Verilog HDL. Once the code is ready, it is simulated using discrete event simulators like Modelsim. After the design is verified, EDA software such as Xilinx ISE is used to create a bitstream for programming the FPGA. The FPGA design flow is broken down into multiple steps summarized in Figure 1-2.

Synthesis: analyses the HDL code and attempts to infer design specific building blocks (such as multiplexers, RAMs, adders, and subtractors). Finite State Machine (FSM) recognition is also part of the HDL synthesis step. The output of synthesis step is called a netlist. Synthesis can be performed for individual modules of code which can then be combined in later stage of implementation. Design constraints used to control specific parameters during FPGA implementation like FSM coding style, resource sharing etc should be defined before synthesis. Translate: merges the individual netlists used in the design with the user specified constraints into a common design file. During translation, the logical design is reduced to FPGA specific primitives.

Map: fits the design into the available resources on the target device into FPGA elements such as CLBs and IOBs. The output of this stage is the logical design mapped to the components in the FPGA.

Place and Route: places and routes the design to the timing constraints. This is the final step of mapping the logical design to the FPGA. If the design is not coded properly or the constraints are not properly specified, it may happen that the tool fails to find a feasible placement for the CLBs and IOBs created during the map procedure. In such a case, the designer needs to look at the bottleneck logic pathways and improve the design.

Generate Programming File: creates a bitstream file that can be downloaded to the FPGA device. After the design is completely routed, the FPGA device must be configured so it can execute the desired function. As FPGAs are SRAM based devices, they need to be configured after every power cycle. Usually a Flash memory is used to store the configuration bitstream which is automatically loaded into the FPGA after power-up. Once the design is ready, testing on the actual hardware begins. Any error observed has to be isolated and rechecked in simulation so as to be fixed.

To summarize, FPGAs are excellent medium for designing and prototyping digital logic into medium-volume, medium-density applications. Their flexibility and fieldprogrammability results in a simplified design cycle, ease of making modifications and adding features to an already deployed product, faster time-to-market. Also, there are no upfront non-recurring expenses (NRE) associated as with FPGAs making it an ideal medium for

implementing Carrier-Ethernet solutions which are yet in their starting stage and are witnessing new developments and advances continuously.