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Principles of Digital Sys tems Des ign and VHDL

Principles of Digital Systems Design and VHDL

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This book is a res ult of many years of teachinga senior course in digital systems design atthe Univers ity of Texas at Aus tin. Intended fora senior-level course, the book covers bothbasic principles of digital sys tems design andthe us e of hardware description language,VHDL, in the design proces s. Em phasis isplaced on teaching by example and for thisreason, many digital system design examples,ranging in complexity from a simple binaryadder to a microproces sor, are included CDROMin the text. All of the VHDL code in thistextbook has been tested us ing the Models imsimulator.

Becaus e s tudents typically need a review of the basics of logic design, Chapter 1 includes a review of logic design fundamentals. Most students can review this material on their own, so it is unnecess ary to devote much lecture time to this chapter * Emphas is is placed on the basic features that are necessary for digital design and omit some of the less -used features * Material is presented in a generalized fashion, with references to specific products as examples, to enhance unders tanding of the basic principles in the cons truction of programmable devices A variety of examples are pres ented s o that ins tructors can select their favorite designs for teaching

1. Review of Logic Design Fundamentals Combinational Logic / Boolean Algebra and Algebraic Simplification / Karnaugh Maps / Des igning with NAND and NOR Gates / Hazards in Combinational Circuits / Flip-Flops and Latches / Mealy Sequential Circuit Design / Des ign of a Moore Sequential Circuit / Equivalent States and Reduction of State Tables / Sequential Circuit Timing / Tris tate Logic and Busses 2. Introduction to VHDL Computer-Aided Design / Hardware Description Languages / VHDL Description of Combinational Circuits / VHDL Modules / Sequential Statements and VHDL Process es / Modeling Flip-Flops Using 3. VHDL Proces ses / Process es Using Wait Statements / Two Types of VHDL Delays : Transport and Inertial Delays / Compilation, Sim ulation, and Synthesis of VHDL Code / VHDL Data Types and Operators / Simple Synthesis Examples / VHDL Models for Multiplexers / VHDL Libraries / Modeling Registers and Counters Us ing VHDL Processes / Behavioral and Structural VHDL / Variables, Signals , and Constants / Arrays 4. Design Exam ples BCD to 7-Segment Display Decoder / A BCD Adder / 32-Bit Adders / Traffic

Light Controller / State Graphs for Control Circuits / Scoreboard and Controller / Synchronization and Debouncing / A Shift-and-Add Multiplier / Array Multiplier / A Signed Integer/Fraction Multiplier / Keypad Scanner / Binary Dividers 5. SM Charts and Microprogramming State Machine Charts / Derivation of SM Charts / realization of SM Charts / Implementation of the Dice Game / Microprogramming / Linked State Machines 6. Des igning with Field Programmable Gate Arrays Implementing Functions in FPGAs / Im plementing Functions Using Shannon s Decomposition / Carry Chains in FPGAs / Cascade Chains in FPGAs / Examples of Logic Blocks in Commercial FPGAs / Dedicated Memory in FPGAs / Dedicated Multipliers in FPGAs / Cost of Programmability / FPGAs and One-Hot State As signment / FPGA Capacity: Maximum Gates Versus Us able Gates / Design Translation (Synthesis) / Mapping, Placement, and Routing 7. Floating-Point Arithm etic Repres entation of Floating-Point Numbers / Floating- Point Multiplication / Floating-Point Addition / Other Floating- Point Operations 8. Additional Topics in VHDL VHDL Functions / VHDL Procedures / Attributes / Creating Overloaded Operators / Multi-Valued Logic and Signal Resolution / The IEEE 9-Valued Logic System / SRAM Model Us ing IEEE 1164 / Model for SRAM Read/Write System / Generics / Named As sociation / Generate Statements / Files and TEXTIO 9. Des ign of a Risc Microprocessor The RISC Philos ophy / The MIPS ISA / MIPS Ins truction Encoding / Implementation of a MIPS Subset / VHDL Model 10. Hardware Testing and Design for Testability Testing Combinational Logic / Tes ting Sequential Logic / Scan Testing / Boundry Scan / Built-In Self- Test 11. Additional Design Examples Des ign of a Wristwatch / Mem ory Timing Models / A Univers al As ynchronous Receiver Trans mitter (UART) Appendix A VHDL Language Summary Appendix B IEEE Standard Libraries Appendix C TEXTIO Package Appendix D Projects References

Charles Roth University of Texas, Austin Lizy Kurian John, University of Texas, Austin

Language English Binding Paperback Edition 1st Edition Author(s) Charles H. Roth Jr. - University of Texas, Austin, Ph.D., Standford Univers ity Lizy Kurian John ISBN-13 9788131505748 No of Pages 544 Publishing Date 2008

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