Académique Documents
Professionnel Documents
Culture Documents
V 0.3 1
Memory Vocabulary
• RAM – Random Access Memory – memory that
can be both read and written during normal
operation.
– Contents are non-volatile, will be lost on power off.
• SRAM – static RAM – has the following
characteristics:
– Read, Write operations take equal amounts of time
– Access to any ‘random’ location takes same amount of
time.
– Fastest access time of memory types.
– Basic memory cell is a latch, takes 6 transistors per
memory bit.
V 0.3 2
Static Random Access Memory (SRAM)
• The serial EEPROM had low pin count because of serial
I2C interface
– Speed was sacrificed
– Random access read took 5 bytes (3 bytes to set address, 2 bytes
for read). Total of 45 bit times (5 * 9), @400 KHz this took 2.5 µs
* 45 = 112.5 µs!
– Write speed was slow because non-volatile memory (page write
took about 6.5 ms for 64 bytes, or about 101 µ s/byte.
• An SRAM (Static Random Access Memory) has:
– equal read/write times, measured in nanoseconds
– volatile (contents not maintained when power removed)
– equal cycle time, access time
– typically has a parallel interface
V 0.3 3
Typical SRAM Control Lines
KxN
Address[log2(K)-1:0]
Data[N-1:0]
M
CS E
M Data bus is
OE
bidirectional
W
Memory
Organization
Word lines
(1 per row)
Wordline
B (bitline) BB (bitline_bar)
V 0.3 6
Cypress 8K x 8 SRAM
V 0.3 7
Read Cycle
V 0.3 9
Write Timings
Notice that
Write Cycle =
Read Cycle.
All volatile
RAM types
have this
feature.
V 0.3 10
PIC18 To SRAM ‘#’ means
low true
PIC18 8Kx8
RA[7:0] A[7:0]
RB[4:0] A[12:8]
RC[7:0] IO[7:0]
Vdd CE2
RD0 OE# CE1#
RD1 WE#
RA[7:0] A[7:0]
RB[4:0] A[12:8]
RC[7:0] IO[7:0]
RB5 CE2
RD0 OE# CE1#
PIC18 WE#
RD1
RAM0 8Kx8
RAM1 accessed A[7:0]
when RB5 = 1 A[12:8]
IO[7:0]
CE1#
RAM0 accessed OE# CE2
when RB5 = 0 WE#
V 0.3 12
More Memory RAM0 RAM1
13 A[12:0]
RB[4:0], RA[7:0] A[12:0]
8
RC[7:0] IO[7:0] IO[7:0]
RD0 OE# OE#
RD1 WE# WE#
PIC18 CE1# CE1#
RB[6:5]
V 0.3 14
External Memory Interfaces
Data written by
PIC18 to
memory
A Table Write (TBLWT) instruction is used to read data
from external memory.
V 0.3 18
Other SRAM Types
• SSRAM - Synchronous SRAM
– Has a clock input
– Address, data lines latched on clock edge
– Can perform burst cycles
• What is a burst cycle?
– After first data value is output based upon address, data
values in successive locations are output without
needing to change address bus
– Internal counter used for address value
V 0.3 19
Synchronous SRAM (SSRAM)
V 0.3 22
A Cache System
1st level
cache
Single CPU
chip
Memory (SRAM)
(die)
2nd level
Processor Memory (SSRAM) cache
Module
Casing
3rd level
Memory (SSRAM)
cache
Motherboard
Main Memory (DRAM)
V 0.3 23
What is a Cache?
• The “closer” a memory is to a CPU, the faster the
data transfer between CPU and Memory.
– Can’t get any closer than on the same chip as the CPU!
• For high performance microprocessors, need
LOTS of memory
• Don’t have enough room to put all memory on
same chip as CPU
– Put some memory on same die as CPU, will not be able
to hold all needed data/programs but will hold most
frequently used data/programs
– Will need to swap out some data if we don’t find what
we need in the cache (a miss!).
V 0.3 24
Memory Hierarchy
Cost/Bit Access/Speed
Floppy CD-ROM
Tape
Zip CD-RWR
Capacity
V 0.3 25
L1 instr. Intel 3rd
cache Generation
IA-64
IA-32 CPU
(executes
(pentium, for
new 64-bit
compatibility)
instructions)
L2 cache 0.13µ
cache and
memory
L3 cache account for
about 70% of
the die.
V 0.3 26
Main Memory and DRAM
V 0.3 27
DRAM Memory Cell
Word line
V 0.3 28
DRAM Characteristics
• Very dense (high capacity). Cheap per bit.
• Slow for Random Access (access to any location)
– Cycle time >> access time, Read Cycle time = Write cycle
time.
• Has special access modes to speed block transfers
– Important since transfers to DRAM in modern computer
system is always block-oriented for cache fills.
• Only has half the address pins that you would expect
– 1M x 8 DRAM has only 10 address pins instead of 20
– Reduces package size, can pack more DRAM chips per
unit area. Address values multiplexed between
row/column addresses
V 0.3 29
A 1M x 16 DRAM (Micron Tech.)
A0-A9 - 10 address pins
DQ1-DQ16 – 16 data pins
RAS# - row address strobe –
asserted when address pins
contain row address.
CASL#, CASH# - column
address strobe – asserted
when address pins contain
row address. Both need to be
asserted for 16 bit transfers,
only one for either high or
low byte transfers.
V 0.3 30
Address Muxing
Assume a 16-bit data wide bus (D0-D15), and 20 address
lines A20-A1 (no A0 pin since 16 bit-wide data bus).
How are addresses split between Row, Column?
A9-A0
A20-A1 DRAM RAS#
CPU Chip select controller
CASL# DRAM
Decode CASH#
V 0.3 31
DRAM Controllers
• External logic called a DRAM controller needed
to interface to DRAMs.
– DRAM interfacing more complex than SRAM
• Provides muxing of Address lines
• Assertion of RAS, CAS lines
• Also keeps DRAM contents refreshed
– Capacitors tend to leak. Memory contents needs to
continually accessed in order to keep contents valid.
– Special ‘refresh’ cycles are supported by DRAMs to
support refreshing all of bits in a row with one cycle
– DRAM controller responsible for running refresh
cycles.
V 0.3 32
RAS asserted first
V 0.3 35
DRAM Chip Generations
V 0.3 36
DRAM Modules: SIMMs and DIMMs
SIMMs/DIMMs invented to
get denser packaging for
DRAMs on motherboards.
V 0.3 38
Schematic View of 72-Pin SIMM
V 0.3 39
Memory Device Specification
• “Dimension” of Storage Cell Array
– 8 Mb – Refers to Eight Mega-bits (not Mega-Bytes!)
8 Mb (lower case ‘b’ !!)
=(8)(1024)(1024)bits
=(1)(1024)(1024)Bytes
=1MB (upper case ‘B’!!)
V 0.3 44