Layout Guideline For High Speed Designs

Purnachandar Poshala, Applications Manager - HSP

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What does Signal Integrity mean to YOU?

Ringing Overshoot/Undershoot Crosstalk Duty-cycle jitter NEXT/FEXT Eye performance Monotonicity Timing Jitter Signal-to-Noise Ratio (SNR) Impedance discontinuity Signaling Topologies

All OR Some of these! Or More??? Pk-to-pk data jitter

Return Loss Return Path discontinuity Distortion Insertion Loss

Signal Terminations Channel modeling Noise ISI degradation

Impedance control

Bit-error-rate

On-die termination (ODT)

Pre-emphasis/De-emphasis

Key points on SI
Signal Integrity (SI) ensures signals
are of sufficient quality to reliably transmit their required information, do not cause problems to themselves or to other components in the system.

SI applies to Digital, Analog and Power electronics SI issues are more common now because
electronics are more dense chips have lower voltage, higher speeds

SI is multidisciplinary;
needs knowledge of RF, digital systems, circuit design, EM modeling

SI assures the circuit design operates as intended (in the first-pass) and these principles must be designed in.

Correct design relies on experience, best practices, analysis and simulation to ensure desired signal quality!

Examples of SI issues (1/2)

Courtesy: Rajen Murugan

Transmission Line
When must we treat a trace like a transmission line? If the trace length is bigger than:

tR 6 t PR

L = trace length tR = rise time (10% to 90%) tPR = signal propagation rate. For FR4, 150ps/in < tPR < 175ps/in tR can be approximated as

tR =

2 7 f max

Under the below condition the trace needs to be considered and analyzed as transmission line

2 7 f max 6 t PR
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Transmission Line
How to treat a transmission line?

R = series resistance of the conductor per unit length L = series inductance of the conductor per unit length C= capacitance due to dielectric layer per unit length G= admittance due to dielectric layer per unit length

= ( R + jL)(G + jC ) = + j
( R + j L ) L Z0 = = (G + jC ) C
Lossless trace

Propagation Equation

Characteristic Impedance

Transmission Line: reflection

Reflection coefficient gives the ratio between the reflected voltage amplitude and the incident voltage amplitude at the receiver. Rs A
Vs

B Zo B RL

RL Z0 = RL + Z0

Rs: clock source output impedance RL: termination Z0: transmission line characteristic impedance Ideally must be 0 meaning RL=Z0. Any discontinuity in the impedance value during the signal propagation path will generate reflections.

Transmission Line: reflection

Propagation Delay: 550ps

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EMI origin
The Electric Field around a conductor is proportional to the voltage or current which flows. Single Ended Balanced Differential Ended Unbalanced Differential Ended maximum radiation (TEM) coupled electric fields are tied up and cannot escape excess in the fringing field

Single Ended

Balanced Differential

Unbalanced Differential
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EMI origin
Emissions due non-idealities

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EMI reduction: design

Field distribution in transmission line

How to further reduce?

Shield traces to GND on both sides

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EMI reduction: design

Differential signal

Minimize the imbalances between the conductors of each pair Close coupling between the conductors of each pair

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Signal Routing: coupling and crosstalk

To reduce coupling, we should: Increase Isolation between aggressor and victim Isolate the Power supplies Make sure the ground is low impedance to reduce ground bounce Trace spacing: Single Ended signals return current density drops to 4% when D/H =5 and drops to 1% when D/H = 10. Differential signals distance between two pairs should be >2S, distance between a pair and SE signal trace >3S or even better to different plane guard ground trace or ground fill distance >2S

Coupling Zones

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Signal routing: minimizing the skew

Minimize the propagation time difference between the two signals of a differential pair. A mismatch generates common mode noise that will be emitted as radiation. The propagation velocity on a board is given by:

V=
c = 0.2998 mm/ps speed velocity r = dielectric constant ( for FR-4 is 4.2)

The reciprocal will give us the propagation time for 1mm board trace. For FR-4 case this is 6.84ps Match the lengths of a pair within 1/20 of the signal rise time.

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Analog and Digital Ground

Reasons to not split the ground plane:
1. 2. Strong chance for error in making the split. Could cause a large inductive loop which gives rise to noise.

Fact:
With proper decoupling and grounding, many single GND planes perform as good as split ground planes.

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Routing Guidelines for SI

1. 2. Do not make discontinuities in the reference plane of signals. Use only straight or 45 degree bending traces. Do not use 90 degree bendings. 3. Do try to remove stubs. If unavoidable, keep the length minimum. 4. Draw same traces if possible 5. Draw traces with the same length 6. Keep the space of differential lines constant 7. Use higher Z0 traces for multi-drop systems for compensation 8. Increase spacing to reduce crosstalk 9. Place ground vias next to signal vias 10. Draw ground and power traces as wide as possible 11. Reduce the stub length of de-coupling capacitors 12. Place a ground net next to a power net

Physical Layout Considerations Cont.

The length of a trace use to connect a capacitor has a big impact on parasitic inductance and resistance of the mounting. This trace should be as short and wide as possible. Wherever possible, minimize the trace by locating vias near the solder pad landing. Further improvements can be made to the mounting by placing vias to the side of capacitor lands or doubling the number of vias as shown in Figure 11.0 below.

via

Via-in-pad pad

trace

Mounting geometry for reduced inductance

Figure 14.0: Capacitor placement geometry for improved mounting inductance

Power supply
DO NOT have vias between bypass caps and active device Visualize the high frequency current flow !!! Ensure Bypass caps are on same layer as active component for best results. Route vias into the bypass caps and then into the active component. The more vias the better. The wider the traces the better. The closer the better (<0.5cm, <0.2) Two or Multi-Layer Ceramic surface mounting capacitors in parallel should be placed at each VCC pin

Poor Bypassing

Good Bypassing

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Rule 1. Dont make discontinuities in the reference plane

s w G 3w G

s G G

There should be no discontinuities in the reference plane within 3*W

Rule 2. Use straight or 45 degree bending traces. Do not use 90 degree bendings

Use straight lines if possible If bending is really needed, use only 45 degree bending 90 degree bendings induce a parasitic capacitance of ~0.3pF

Rule 3. Do try to remove stubs. If unavoidable, keep the length minimum

Stubs create impedance discontinuities, causing mismatch, and therefore may cause reflections and degrading return-loss performance; try minimizing/eliminating them on high-speed signaling paths.

Rule 4. Draw same traces if possible

For differential lines, this is critical.

Rule 5. Draw traces with the same length

Length-matching is critical on differential interfaces to achieve good SI on differential parameters and minimize differential-to-common mode conversions.

Rule 6. Keep the space of differential lines constant

The differential Z0 can be different with a different space. Uniform spacing on differential pairs is critical for impedance uniformity along trace-length

Rule 8. Reduce crosstalk

Separate traces as far as possible

Rule 9. Place ground vias next to Signal Vias

S1 GND S2

S1 S2 GND

S1 S2

Distance between S1 via and GND via needs to be calculated to have similar Z0 as traces

Rule 10. Draw power and ground as wide as possible

vdd

vdd

gnd

gnd

Reduces Static and Dynamic IR drop impact Stitch P/G planes across layers with vias as much as possible.

Rule 11. Reduce the stub length for decoupling capacitors

Stub length increases inductance, which causes bigger power noise