Shailendra Kumar Rajput

Shailendrarajput89@gmail.com

:+91 741134 859 6

CAREER OBJECTIVE
To involve myself in cutting edge technology to deliver high-end innovation and a career in an organization having an environment that encourages continuous learning so as to achieve professional and personal growth with the organization.

PROFESSIONAL EXPERIENCE
2.5 years of experience in frontend VLSI domain as ASIC Design Verification engineer at Sasken Communication Technologies Ltd since September 2011-Present.

TECHNICAL EXPERIENCE
Assembly Language Hardware Design Language Hardware Verification Language Verification Methodology Scripting Languages Operating Systems Responsibilities : ARM and 8086 ALP. : VHDL and Verilog. : System Verilog and e-Specman. : UVM. : Perl. : Linux. : ARM SOC verification, TB/Testcase development and debugging and fixing, Functional and Code coverage analysis. : ARM architecture, System Verilog, UVM, Verilog.

Areas of Interest

EDUCATIONAL QUALIFICATION
Education B.E. (Electronics & Communication Engineering) Class 12 Class 10 College/University Cambridge Institute of Technology, Bangalore / VTU K.V ASC Center (South), Bangalore / CBSE K.V ASC Center (South), Bangalore / CBSE Year 2011 78 83 Percentage 85

2007 2005

EXPERIENCE SUMMARY
Having 2.5 years of experience as ASIC Design Verification engineer.

Experienced in System Verilog and UVM methodologies. Knowledge in Tb building, test scenario generation, debugging and coverage. SOC level verification of ARM v7 and v8 processors. IP level verification of AHB to AXI Bridge in UVM methodology. Real time exposure of Testcase writing in ARM assembly language programming. Good debugging skills at assembly level. Sound knowledge in C and C++ programming.

PROJECT DETAILS
1. Verification of AHB to AXI Bridge using UVM The main function of this bridge is to convert read/write transactions of AHB protocol into read/write transactions of AXI protocol. Bridge can be used in multi-master/multi-slave configuration with different frequencies at both sides. Duration: July 2013-January2014 Language: System Verilog Methodology: UVM Responsibilities Test plan, Assertion plan and Coverage plan creation. Coding of AXI slave UVC. Coding of Testcases and analysis of coverage reports. Coding of AXI monitor, checker and transaction class. Languages: System Verilog 2. ARM V7 SOC Verification Performed SOC level verification for ARM V7 Processor. Duration: January 2012 December 2012 Responsibilities: Effectively involved in debugging the tests cases written for various test scenarios. Writing the Perl scripts for running regressions. Efficient involvement in the final AVK Kit release including documentation of the kit. Tools: OS: VCS tool ARM validation tools. ARM assembly tools. Subversion(SVN) Unix

Languages: ARM assembly

PERL scripting

Project Description: Following points were aimed at in this project ARM V7 to be used in simple microcontroller devices. Provide highest performance at low power. Involve TrustZone and Jazellex features. Provide MMU for OS and multitasking Achieve Deterministic and predictable behavior. 3. ARM V8 SOC Verification Duration: January 2013 June 2013 This is project developing AVS suites for the v8 Architecture. AVS suites checks adherence to an architecture definition so that a. ARM cores of same architecture version are software compatible with each other. b. Cores from Architecture licensees are s/w compatible with all other cores (ARM and others) of the same Architecture version. 4. Verification of ImageStat using Specman. ImageStat is a statistics generator for review by the software to determine if the image is useable for further image processing. The project involves two protocols, OCP and Video Port Protocol. The testbench is being coded using UVM Methodology. Duration: September 2011 October 2011 Contribution:

My role in the project was to develop the OCP & Vp UVCs. Also involved in the coding Testcases and coverage. Analysis of coverage.

Language: Specman Methodology: eRM 5. GDMA (GENERAL DIRECT MEMORY ACCESS) Reference model development The General DMA works based on the concept of channel. Data transfer happens between in two phases 1. from Source to DMA. 2. from DMA to Destination Duration: November 2011 December 2011 Responsibilities: My task was to develop two modules namely CHANNEL SCHEDULER and CONTEXT MANAGER. CHANNEL SCHEDULER block is responsible for scheduling which channel is to be serviced next. A channel is granted access to read/write port by the arbitration logic. CONTEXT MANAGER block is responsible for updating next running byte address and number of elements remaining for transfer. Tools: Cadence composer

Simvision Specman Subversion(SVN)

GENERAL SKILLS & ACHEIVEMENTS

Team-Player with good communication skill. Topper of the college for 2nd, 3rd& 4th years of B.E. Awarded with gold medal for academic excellence for the year 2008-2009. Awarded with gold medal for academic excellence for the year 2009-2010. Author of the Microprocessor Textbook for VTU. Self-motivated, Adaptable, Responsible and punctual. Quick learner and goal oriented. Good Mentoring capability.

PERSONAL PROFILE
Name Nationality Date of Birth Languages : Shailendra Kumar Rajput : Indian : August 22nd, 1990 : English, Hindi.

DECLARATION
I do hereby declare that the information given above is true and correct to best of my knowledge. I also bear the responsibility for accuracy of above-mentioned particulars.

Shailendra Kumar Rajput