IDESA CMOS Physics Using MASTAR Part 2of2x

Tutorial 11
Using the System Layout Module Using the System Layout Module
For industrial feasibility evaluation
1
DESCRIPTION
Simulating propagation delay in inverter chain loaded
with capacitive and resistive systems
Calculating the Static Noise Margin of 6T-SRAM
cells
Using the randomization effects in order to evaluate
the impact of variability of device parameters on
T. Skotnicki & F. Boeuf
the impact of variability of device parameters on
electrical performance of circuits.
2
Inverter Speed Evaluation, incl. RC Line
L
G
l
int
M
X
3
Inverter 1 Inverter 2 Inverter N
Cload
Rline
Cload
Rline
Cload
Rline
Inverter 1 Inverter 2 Inverter N
Cload
Rline
Cload
Rline
Cload
Rline
Cload
Rline
Ex-1 : Computing Inverter Delay
including interconnections
Input here
1- the number of stage
2- timing information
3 the period of the input signal
4 R and C values for the BEOL
5 click compute
4
Input
signal
Signal output at stage 2
Signal output at last stage (here 4)
5
Delay at Vdd/2
extraction
Ex- 2 : Computing SRAM SNM
Click here to start the
SRAM evaluation
6
When boxes are uncheck,
only 1 SNM is computed
7
Note : to bring the Compute
Menu, just right click here in
the graph windows
Ex- 4 : Computing SRAM SNM
If none of the box are
checked 1 cell
calculation
Calculation precision
If at least one of the box
is checked several
cell calculation with
random variation on
selected parameters
If Only half
cell calculation is
checked, computation
time will be divided by 2,
but butterfly curve will
always be symetric
If Only half
cell calculation is not
checked, computation
time butterfly can be
assymetric
Check boxes to generate
variability
Choose the number of
generated SNM.
Check enable Symetrical Choose the data to display
10
Check enable Symetrical
curve to compute only a half
cell, or uncheck to generate
the whole cell variability
After calculation, statistical
data are available
Choose the data to display
Tutorial 12
Inverter Delay Inverter Delay
11
Description
Objective : evaluate the inverters delay as a function of
layout of transistors, interconnection length, and process
variability
Content
Background Elements
Parasitic Capacitances of MOSFETs
Input and Output capacitance of an Inverter chain
Input and Output capacitance of an Inverter chain
Ex-1 : Influence of N/P Ratio on Inverters delay
Ex-2 : Optimal N/P ratio in the case of a boosted PMOS transistor
Ex-3 : Impact of process variability on the worst-case
inverters speed
Ex-4 : Influence of interconnect wire length on speed
performance
12
Bibliography
An Evaluation of the CMOS Technology Roadmap From the Point of View of
Variability, Interconnects, and Power Dissipation Boeuf, F.; Sellier, M.; Farcy, A.;
Skotnicki, T.; Electron Devices, IEEE Transactions on Volume 55, Issue 6, June
2008 Page(s):1433 1440 Digital Object Identifier 10.1109/TED.2008.921274
Predictive Delay Evaluation on Emerging CMOS Technologies: A Simulation
Framework, Manuel SELLIER, Jean-Michel PORTAL, Bertrand BOROT, Steve
COLQUHOUN, Richard FERRANT, Frdric BOEUF, Alexis FARCY Quality
Electronic Design, 2008. ISQED 2008. 9th International Symposium on 17-19 March
2008 Page(s):492 497
2008 Page(s):492 497
Using MASTAR as a Pre-SPICE Model Generator for Early Technology
Assessment and Circuit Simulation Frederic Boeuf, Manuel Sellier, Fabrice Payet,
Bertrand Borot and Thomas Skotnicki , Jpn. J. Appl. Phys. 47 (2008) pp. 3384-3389
CMOS Technology Roadmap Projection Including Parasitic Effects, Lan Wei,
Frdric Boeuf, Thomas Skotnicki, H.-S. Philip Wong*, VLSI-TSA 2009
13
Capacitance definition
Cgc: on-state gate-to-channel cap
Cgb_off: off-state gate to substrate cap.
Cov: overlap cap
Cof: outer-fringe cap
Cif: inner-fringe cap
Cpcca: poly to contact plug cap.
C
pcca
C
of
C
ov
C
j
C
if
C
j
C
if
C
of
C
pcca
C
ov
C
gc
C
gb
Cpcca: poly to contact plug cap.
Cj: junction cap
Ccorner: corner cap, from the
gate overlay to S/D
Source
C
corner
C
corner
C
corner
C
corner
Drain
Top view
Ref.: Lan Wei, STMicroelectronics-STANFORD Univ. Collaboration pgm.
& Lan Wei , VLSI TSA 2009
Caps for a Single Device
Cd (on) Cg(on) Cg(off)
Cgc Gate-to-channel
Cgb_off Gate-to-sub
Cov Gate overlap
Cof Gate outerfringe
Cif Gate inner fringe
Cpcca Gate to plug
C
gb_off
and C
if
are shielded by the channel in
on-state
C
gc
is not seen by drain node in on-state, due
to pinch-off.
Ccorner Corner cap
Cj Junction cap
C
CORNER C
CORNER
C
CORNER
C
CORNER
Ref.: Lan Wei, STMicroelectronics-STANFORD Univ. Collaboration pgm.
& Lan Wei , VLSI TSA 2009
P1
IN1
V
DD
C
GDP1
C
GDN1
C
JDP1
C
JDN1
OUT1
P2
IN2
V
DD
C
GDP2
C
GDN2
OUT2
INTERCO
C
GBP2
C
GSP2
1
4
3
2
6
5
3
4
5
7
6
1
7
6
1
2
2
4 3 5
OFF-ON
ON-ON
8
8
C
GD1
x
MILLER
C
GD2
NO
MILLER
Caps for an Inverter Chain
N1 N2
C
INTERCO
C
GBN2
C
GSN2
( )
4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 2 1
4 4 4 4 4 4 4 3 4 4 4 4 4 4 4 2 1
2
2 , 2 , 2 2 2 , 2 , 2 2
interco
1
1 1 1 1
75 . 0 25 . 0 75 . 0 25 . 0
2
stage input
GSN ON GBN OFF GBN GDN GDP ON GBP OFF GBP GSP
stage output
jDN jDP Miller GDN GDP L
C C C C C C C C
C C C C C C
+ + + + + + +
+ + + + + =
ON-ON
ON-OFF
Capacitance for an Inverter Chain
( )
( )
_ _
0.25 0.75
tot
dg j g off g on interconnect
C
C Miller C C C FO C
C C C C Miller C
= + + + +
= + + + +
Cout (seen by
drain)
Cin(seen by
gate)
( )
( )
( )
0.25
0.75
ov of pcca corner j
gc ov of pcca corner
ov of pcca corner
interconnect
C C C C Miller C
C C C C C
FO
C C C C
C
= + + + +
(
+ + + +
(
+
(
+ + + +

+
With MASTAR5
MASTAR System Layout Function
Calculate
1fF
by full waveform calculation

FO1,
FO3
are estimated by
where, C
inverter_FO1(3)
is calculated by the new
_ 1(3)
1(3) _ 1
1
inverter FO
FO adjusted fF
C
fF
=
where, C
inverter_FO1(3)
is calculated by the new
models
Different design possibilities are analyzed
Wn/Wp ratios, high driving-capable PMOS
Ex-1 : N/P Ratio (1)
1. Open the system profile basline.xsy
2. Note the ratio between NMOSs Ion and PMOSs Ion : 727/396 = 1.83
3. Set Wp=720nm and Wn=360nm
4. Peformthe calculation of teh inverters delay.
5. Write down the TpFO1 value
(1)
(3)
(4)
19
(2)
(5)
Ex-1 : N/P Ratio (2)
WN WP WP/WN TpFO1 (ps)
360 180 0.5
-Calculate the delay of a FO1 inverter for the following configurations
- plot the delay as a function of WP/WN
-Q : Explain the behavior
20
360 180 0.5
360 360 1
360 720 2
240 720 3
180 720 4
Ex-1 : N/P Ratio - Answer
WN WP WP/WN TpFO1 (ps) Tp/fF Ctot (fF)
360 180 0.5 22.12 15.53 1.42
360 360 1 17.86 9.97 1.791
360 720 2 17.21 6.8 2.53
240 720 3 19.43 8.5 2.29
180 720 4 21.87 10.11 2.164
22
23
24
25
I
n
v
e
r
t
e
r

D
e
l
a
y

(
p
s
)
C at optimum speed is
2.53fF
Optimal Intrinsic delay is 6.8ps
= x
21
15
16
17
18
19
20
21
22
0 1 2 3 4
I
n
v
e
r
t
e
r

D
e
l
a
y

(
p
s
)
WP/WN
Min~1.8
Ex-2 : Boosting the PMOS
22
-Calculate the delay of a FO1 inverter for
the following configurations
- plot the delay as a function of WP/WN
-Q : Explain the behavior
Ex-2 : N/P Ratio with Boosted pMOS
WN WP WP/WN TpFO1 (ps) Tp/fF Ctot (fF)
360 180 0.5 14.2 9.97 1.42
360 360 1 12.19 6.8 1.79
360 720 2 12.62 4.99 2.53
240 720 3 14.72 6.44 2.29
180 720 4 16.92 7.82 2.16
22
24
But C at optimum speed is now
1.79fF
Intrinsic delay is still 6.8ps
23
10
12
14
16
18
20
22
0 1 2 3 4
I
n
v
e
r
t
e
r

D
e
l
a
y

(
p
s
)
WP/WN
Min~1.0
Ex-3 : Delay and Variability
Objective : Study the impact of technology variability on device
performance / speed
Context
Every technology feature intrinsic variations due to process variation or
stochastic variations
Transistor gate length , 3 = 12%*Lgate (ITRS)
Stochastic variation of electrode workfunction due to random dopant
fluctuations (in Poly-Silicon electrode) or metalic grain orientation fluctuation
fluctuations (in Poly-Silicon electrode) or metalic grain orientation fluctuation
(in metallic electrode), ~10mV
Random Fluctuation of transistors channel doping [Mizuno et al. VLSI 93]
Junction depth variation

This will impact the V
th
and the I
dsat
of transistors and therefore create
a statistical distribution of inverters delay
24
Ex-3 - Worst Case Process Simulation
(1)
(2)
25
(2)
Ex- 4 :Variability and Delay : A roadmap Analysis
Q :Use the following table to analyse the scaling of inverters
delay as well as the scaling of the worst case delay (i.e delay
+ 3)
26
After F.Boeuf et al., T-ED 2008
Ex-4 : Variability and Delay
Answer : as devices are scaled down, they are more and more
senstivite to variability sources. As a consequence, after 50nm half-
pitch generation, the worst case delay is scaling slower (4%
faster/year) than the average delay (17% faster / year)
27
After F.Boeuf et al., T-ED 2008
Ex- 5 Impact of Wire Length on Delay
(1)
L,R negligeable
28
(2)
8.72ps
30
35
P
r
o
p
a
g
a
t
i
o
n

D
e
l
a
y

a
t

S
t
a
g
e

2
L m R (Ohm) C (F) Delay (ps)
Assume R= 2.0 Ohm/m
Assume C= 200 aF/m
Q1 :Calculate the propagation delay after the stage 2 for L varying between 0 and 50m.
What is the maximum wire length possible ?
Q2 : How to go beyond this value ?
(corresponding to 2005 ITRS values)
Answer to Q1 :
29
0
5
10
15
20
25
30
0 5 10 15 20 25
P
r
o
p
a
g
a
t
i
o
n

D
e
l
a
y

a
t

S
t
a
g
e

2
Wire Length (m)
L m R (Ohm) C (F) Delay (ps)
0 0 0 8.72
1 2 2.00E-16 9.87
10 20 2.00E-15 20.28
20 40 4.00E-15 31.32
50 100 1.00E-14 N/A
L=10m
L=1m
L=20m
(Signal starts to be deformed = Lmax)
Answer to Q1 (cont)
30
L=50m
(Signal cannot propagate correctly)
Answer to Q2
Increase Wn and Wp to
achieve higher
transistors drive
current . E.g. multiply
Wn and Wp by 2.0
31
L=20m
L=40m
Wn and Wp by 2.0
New Lmax is above 40m
Ex- 6 : Inverters Delay and Metal Line Resistance accros
the Roadmap
Q :Use the following table to analyse the scaling of inverters
delay across the ITRS roadmap, for a wire length scaling
between 0.68x per year and 0.8x per year
32
Ex- 6 : Inverters Delay and Metal Line
Resistance accros the Roadmap
Answer
For 0.68x, delay is properly
For 0.8x, delay is not scaling
at all with the technology !
33
For 0.68x, delay is properly
scaling as inverter delay with a
FO1 load
Bibliography
Innovative Materials, Devices, and CMOS Technologies for Low-Power
Mobile Multimedia Thomas Skotnicki, Claire Fenouillet-Beranger, Claire
Gallon, Frederic Boeuf, Stephane Monfray, Fabrice Payet, Arnaud
Pouydebasque, Melanie Szczap, Alexis Farcy, Franck Arnaud, Sylvain
Clerc, Manuel Sellier, Augustin Cathignol, Jean-Pierre Schoellkopf, Ernesto
Perea, Richard Ferrant, and Herv Mingam, Trans. On Elec. Dev. Invited
Paper, Volume: 55, Issue: 1, page(s): 96-130 (2008)
An Evaluation of the CMOS Technology Roadmap From the Point of
An Evaluation of the CMOS Technology Roadmap From the Point of
View of Variability, Interconnects, and Power Dissipation Boeuf, F.;
Sellier, M.; Farcy, A.; Skotnicki, T.; Electron Devices, IEEE Transactions on
Volume 55, Issue 6, June 2008 Page(s):1433 1440 Digital Object
Identifier 10.1109/TED.2008.921274
Is a Power Optimized Roadmap Realistic for High Performance
Applications? Frederic Boeuf and Thomas Skotnicki, In Extented Abstracts
of SSDM 2007 (JSAP CAT AP071239), pp. 258-259
34
Tutorial 13 :
Device Scaling Device Scaling
35
DESCRIPTION
Starting from a relatively old device profile, we will carry
out a series of modifications to end up with a scaled-
down up-to-date device. The following analysis and
modifications will be considered:
Pocket implants
SCE and DIBL
Junction depth reduction
Junction depth reduction
36
Ex. 1:
STARTING DEVICE PROFILE
Analysis of problems
IDESA Start
IDESA Start
37
Starting device profile (IDESA Start)
38
Note that the channel doping is constant (2
e
17 cm-2)
The threshold voltage drops rapidly down
Already at Lgate=137nm, Vthsatoff reads at no more than
150mV that corresponds to Ioff=10nA/m
For many applications this is already difficult to tolerate
Not to mension that such long Lgate would have a detrimental
effect on the density of integration
Starting device profile analysis
effect on the density of integration
Remember that this IDESA Start profile corresponds
(except for Lgate) to a LOP 65nm CMOS, where the gate
should read at 65nm or below
The first point we will analyse is thus how to make the gate
shorter without lowering the Vthsatoff?
39
Ex. 2
USE OF POCKET IMPLANTS
%
a commonly used technique enabling
gate shortening in CMOS technologies
40
gate shortening in CMOS technologies
Implantion Ionique Implantion Ionique
dose C
poches
Energie R
p
,R
p
, R
l
Implantion Ionique Implantion Ionique
dose C
poches
Energie R
p
,R
p
, R
l
Reverse Short Channel Effect due to
POCKETS or HALLOS:
Ion Implantation Ion Implantation
Idea: instead of increasing the substrate doping uniformly, that would lead to junction
leakage (here), we increase it very locally (here) that prevents SCE and DIBL without
leading to huge junction leakage.
T.
Skot
nicki
Poches ou Halos
L
poches
L/2
Poches ou Halos
L
poches
L/2
Pockets or Hallos
USE OF POCKET IMPLANTS
Pocket implantation conditions
42
Gain in Lgate minimum thanks to pockets
Pocket implantation conditions
Vg
Note that instead of the same Vthsat, the Ioff (leakage is not the same as
without pockets.
This is because of relaxation in the Subthreshold Slope
POCKETS analysis
SS
Subthreshold
Slope
Log(Id)
+
|
|
\
|
+ + + =
d
ds
el
dep
el
j
el
ox
ox
Si
ox
dep
V
L
T
L
X
L
T
C
C
q
kT
S 2 1
4
3
1 1 ) 10 ln(

Vg
The major source of this relaxation in SS comes from the Cdep/Cox term =
[eps(Si)/eps(Ox)]x(Tox/Tdep) term
Pockets increase the doping that leads to a decrease in
( )
SB d
B
Si
dep
V
qN
T + =
2
That leads to an increase in SS (68 without pockets and 91 with)
Ex. 3
HOW TO REDUCE Lgate,min FURTHER?
%
REDUCTION OF SCE and DIBL
(note that in the last example with pockets,
SCE=135mV and DIBL=193mV, whereas
44
SCE=135mV and DIBL=193mV, whereas
before, i.e. without pockets they were
SCE=26mV and DIBL=40mV. This means that
application of pockets was not totally capable
of cancelling the relaxation in Electrostatic
Integrity of the device that is caused by the
reduction of the gate from 137 nm to 53 nm)
UNDERSTANDING SCE and DIBL UNDERSTANDING SCE and DIBL
-
Long channel
-
short
SCE Short Channel Effect
SCE
Bothe SCE and DIBL
lower the barrier that
appears to the electrons
wishing to move from
source to drain, and
therefore both lead to
more leakage current Ioff
-
SCE
DIBL
Vds
DIBL Drain Induced Barrier Lowering
chann
el
more leakage current Ioff
RSCE
SCE
(
V
)
0.3
0.4
V
V
D
=0.1V RSCE
SCE
(
V
)
0.3
0.4
V
RSCE
SCE
(
V
)
0.3
0.4
V
V
D
=0.1V
DIBL SCE RSCE V V
L th th
+ =
,
SCE, DIBL & RSCE IMPACT ON Vth-L:
T.
Skot
nicki
DIBL
V
t
h

(
V
)
0.1
0.2
0
100 10 1000
L (nm)
V
th
V
D
=V
DD
DIBL
V
t
h

(
V
)
0.1
0.2
0
100 10 1000
L (nm)
V
th
DIBL
V
t
h

(
V
)
0.1
0.2
0
100 10 1000
L (nm)
V
th
V
D
=V
DD
SCE & DIBL DEPEND ON RATIOS,
RATHER THAN ON VALUES OF PARAMETERS :
DIBL SCE V V
L th th
=
,
dep el ox j
Si
T T X
SCE
_
2
1 64 . 0
|
|
|
+ =
EI
L
SCE
DIBL
Vth,L
REF.: T. Skotnicki, invited paper
ESSDERC 2000, pp. 19-33, edit.
Frontier Group
T.
Skot
nicki
d
el
dep
el
el ox
el
j
ox
Si
L L
L
SCE
_
2
1 64 . 0
|
|
\
+ =
DS
el
dep
el
el ox
el
j
ox
Si
V
L
T
L
T
L
X
DIBL
_
2
2
1 80 . 0
|
|
\
|
+ =
B
D Si
dep
qN
T
2
=
Ex. 4
%
Via reduction of junction depth Xj
48
REDUCTION OF JUNCTION DEPTH
Xj reduced from 20nm to 12nm
Improved SCE and DIBL thanks to reduced Xj
49
Gain in Lgate minimum
thanks to Xj reduction
Xj reduced from 20nm to 12nm
Tutorial 14 :
High-K /Metal Gate Stack High-K /Metal Gate Stack
50
DESCRIPTION
Cancellation of polydepletion
Gate oxide reduction
Readjustment of pockets
New Lgate,minimum
Gate leakage
Introduction of HK gate dielectric
Introduction of HK gate dielectric
51
Ex. 1
%
Via reduction of Oxide Thickness
(note that the effective gate dielectric
52
(note that the effective gate dielectric
thickness is a summ of the physical gate
dielectric thickness, of the polydepletion
and of the so called Dark space - see
next slide)
SiO2
3D electrons
in the channel
N+Poly-gate Si-P-substrate
3D electrons
in the gate
SiO2
3D electrons
in the channel
N+Poly-gate Si-P-substrate
3D electrons
in the gate
POLYDEPLETION & DARK SPACE:
space dark
Si
SiO
poly
dep
Si
SiO
phys ox el ox
T T T T
_ _ _
2 2
+ + =
T.
Skot
nicki
in the channel
2D electrons
in the channel
Darkspace
in the channel
Polydepletion
Darkspace
in the gate
2D electrons
in the gate in
accumulation
2D electrons
in the gate in
depletion
in the channel
2D electrons
in the channel
Darkspace
in the channel
Polydepletion
Darkspace
in the gate
2D electrons
in the gate in
accumulation
2D electrons
in the gate in
depletion
( )
( )
ox
ox
ox
ox
SB d B Si
F
ox
ss
S m th
T
C
where
C
V qN
C
qN
V
=
+
+ + + =
2
2
,
IMPLICATIONS OF Tox REDUCTION
54
Note that
reduction of Tox not only leads to reduced SCE
and DIBL but also to a reduction in long-
channel thresholod voltage that therefore needs
to be compensated by increased doping or
readjusted gate work function.
IMPLICATIONS OF POLYDEPLETION (Metallic gate)
SCE and DIBL are reduced
55
Metallic gate cancels poly depletion
SCE and DIBL are reduced
Same Vth is maintained due to readjustment
of the gate workfunction
IMPLICATIONS OF Tox REDUCTION
SCE and DIBL are further reduced
56
SCE and DIBL are further reduced
Same Vth is maintained due to readjustment
of the gate workfunction
Reduced also
leads to gate
leakage
Ex. 2
READJUST POCKETS and TRADE ALL
IMPROVEMENTS in SCE and DIBL
AGAINST FURTHER REDUCTION OF
57
AGAINST FURTHER REDUCTION OF
Lgate,minimum
NEW IMPROVED TECHNOLOGY !
Ioff is back to
its initial value
58
Pocket implantation
conditions readjusted
its initial value
But Lgate is
X4 shorter !!!
Ex. 3
PROBLEM OF Igate
%
INTRODUCING H-K GATE DIELECTRIC
59
INTRODUCING H-K GATE DIELECTRIC
(note that once we have thinned Tox from1.8nm to 1.2nm, the
Igate leakage increased from1.18
e
-1nA/m to 8.33
e
+2nA/m thus
exceeding the channel leakage Ioff=1.02
e
+1nA/m. This situation
is not tolerable !)
1.E+01
1.E+03
1.E+05
1.E+07
(
A
/
c
m
2
)
2.2 nm
2 nm
1.8 nm
1.6 nm
1.4 nm
1.2 nm
Ig[A/cm2] =1.44e5*(Exp(-4.02*Ug[V]^2+13.05*Ug[V])*Exp(-1.17*Tox[])
Sim. Data
MASTAR Igate MODEL (very good :
1.E-07
1.E-05
1.E-03
1.E-01
1.E+01
0 0.2 0.4 0.6 0.8 1 1.2 1.4
Ugate (V)
I
g
(
A
/
c
m
2
)
1.2 nm
1 nm
0.8 nm
0.6 nm
0.4 nm
MASTAR
analytical model
Simulation data : Hauser, NCSU, UQUANT model
High-K PRINCIPLE :
diel
g
T
K
C
= == =
( (( ( ) )) )
b diel g
T J

exp
If K and Tdiel
increase in parallel,
Cg is conserved
but
Jg decreases rapidly
T.
Skot
nicki
In practice we always keep a
thin pedestal oxide at the
dielectric-Silicon interface.
The H-K material is deposited
on top of the pedestal oxide.
Gate
H-K
Pedestal
SiO2
Huge reduction in Igoff, from 8.33
e
2 nA/m to
1.96
e
0 nA/m thanks to HK
Gate leakage must not exceed the channel leakage
62
If EOT=constant is
selected, MASTAR
will automatically
calculate the reqired
TIF (Technology
Improvement
Factor=Igate,SiO2/Iga
te,H-K) from the
settings given by the
user
CONCLUSIONS (DEVICE SCALING & HK / Metal G)
The final device profile we have achieved presents
largely shorter gate (reduced X4)
All other parameters (SCE, DIBL, SS, Ioff, Igate,off, etc)
are however at their maximal tolerable values
This prevents further scaling down
Also Variability and Speed of the technology suffer from
these border-line values
63
these border-line values
Therefore other solutions, breakthrough like, will have to
be considered to pursue scaling
We will first explain Variability and Impact of DIBL on
performance, and next
Consider more robust device structures enabling further
scaling
Tutorial 15 :
DEVICE VARIABILITY DEVICE VARIABILITY
64
Ex. 1
Derivation of the threshold voltage
fluctuation model
And
65
And
its discussion
Vth random dopant # fluctuations
T.
Skot
nicki
After: T. Skotnicki et al. Innovative
materials, devices and CMOS
technologies for low-power mobile
multimedia, pp. 96-130, IEEE
TED, Jan. 2008
20
30
V
t
h

S
t
a
n
d
a
r
d

d
e
v
i
a
t
i
o
n

(
m
V
)
with pockets
without pockets
0.12 m 0.17 m 0.25 m 0.5 m
STRONG CHANNEL DOPING (e.g. POCKETS)
ENHANCES Vth FLUCTUATIONS
=> UNDOPED CHANNEL WITH MID-GAP GATE
(ON THIN FILM SOI/SON) MAY BE A REMEDY
Vth random dopant # fluctuations
T.
Skot
nicki
0 2 4 6 8
0
10
1 1 / ( / ) WL m
V
t
h

S
t
a
n
d
a
r
d

d
e
v
i
a
t
i
o
n

(
m
V
)
REF.: T. Cochet, T. Skotnicki et al., ESSDERC99
4
4
3
2
4
ch
el
ox
ox
F s
th
N
W L
T
q
V

=
8k-MOSFET ARRAY, Tox=11nm, Nch=7.1e16cm-3
VARIABILITY - FLUCTUATIONS:
A 4.2 nm MOSFET in production 2023
T. Mizuno et al., IEEE TED, Nov. 1994 Courtesy of A. Asenov, Glasgow Univ., UK
Electron concentration
Line Edge Roughness (LER)and Poly Grains (PGG) vs Random
Dopant Distribution (RDD) RDD is the dominant effect !
Courtesy Prof. A. Asenov Glasgow U.
A. Cathignol et al. , EDL, 2008 (ST)
Fluctuations IMPACT ON
LOGIC and on SRAM
SNM w/o process spread
Microelectronics
Journal 36 (2005)
789800
Huifang Qin
LW
A
LW
T
N q
V
vt ox
ox
d c s
th
1 1
2
0
4
3
0

SNM with process spread
Courtesy Prof. A. Asenov
Ex. 2
Device Variability as function of its size
71
The statistical distribution of Vt is narrow with Nominal MOSFETs
72
39 mV
The statistical distribution of Vt is large with Scaled Down MOSFETs
73
74 mV
Tutorial 16 :
SRAM VARIABILITY SRAM VARIABILITY
74
Ex. 1
Analysis of SRAM SNM (Static Noise
Margine) in function of Vdd (supply
voltage)
75
voltage)
VDD=1.1V
0.8
1.0
1.2
VDD=1.1V
0.8
1.0
1.2
VDD=0.9V
0.8
1.0
1.2
VDD=0.9V
0.8
1.0
1.2
VDD=0.7V
0.8
1.0
1.2
VDD=0.7V
0.8
1.0
1.2
LP IS DIFFICULT
The SNM (Static Noise Margine) vanishes when lowering the Vdd,
Thus preventing correct voltage scaling ! As a result the Vdd has
been stagnating in LP technologies around 1.1V (see next slide).
0.0
0.2
0.4
0.6
0.8
0.0 0.2 0.4 0.6 0.8 1.0 1.2
Vin (resp. Vout)
V
o
u
t

(
r
e
s
p
.

V
i
n
)
0.0
0.2
0.4
0.6
0.8
0.0 0.2 0.4 0.6 0.8 1.0 1.2
Vin (resp. Vout)
V
o
u
t

(
r
e
s
p
.

V
i
n
)

0.0
0.2
0.4
0.6
0.8
0.0 0.2 0.4 0.6 0.8 1.0 1.2
Vin (resp. Vout)
V
o
u
t

(
r
e
s
p
.

V
i
n
)
0.0
0.2
0.4
0.6
0.8
0.0 0.2 0.4 0.6 0.8 1.0 1.2
Vin (resp. Vout)
V
o
u
t

(
r
e
s
p
.

V
i
n
)
0.0
0.2
0.4
0.6
0.8
0.0 0.2 0.4 0.6 0.8 1.0 1.2
Vin (resp. Vout)
V
o
u
t

(
r
e
s
p
.

V
i
n
)
0.0
0.2
0.4
0.6
0.8
0.0 0.2 0.4 0.6 0.8 1.0 1.2
Vin (resp. Vout)
V
o
u
t

(
r
e
s
p
.

V
i
n
)
After: T. Skotnicki et al. Innovative materials, devices and CMOS technologies for low-
power mobile multimedia, pp. 96-130, IEEE TED, Jan. 2008
VARIABILITY IS BEHIND THE VDD CLUMSY SCALING
AND THUS BEHIND THE POWER CRISIS
Evolution of VDD (LSTP)
3
3,5
4
4,5
5
5V plateau
10 years of constant-field scaling
from 5V to 1.2V (x 0.7 per node)
T.
Skot
nicki
0
0,5
1
1,5
2
2,5
3
1980 1992 1995 1998 2000 2002 2004 2007 2010 2015
Year of production (ITRS)
V
o
l
t
1.2V plateau
120 90 65 32 250 350 700 45
1.1V
500 180
~1V plateau ???
CALCULATING THE EFFECT OF VANISHING SNM WITH MASTAR (1)
78
79
Ex. 2
Analysis of SRAM SNM (Static Noise
Margine) in function of the cell size
80
SMALL IS DIFFICULT
Bulk_poly_0.276m
2
PU W/L= 55/80
PD W/L=215/55
PG W/L=170/65
0.8
1.0
Bulk_poly_0.276m
2
PU W/L= 55/80
PD W/L=215/55
PG W/L=170/65
0.8
1.0
0.8
1.0
V
o
u
t

(
r
e
s
p
.

V
i
n
)
Bulk_poly_0.164m
2
PU W/L= 45/32
PD W/L=105/32
PG W/L= 90/45
0.8
1.0
V
o
u
t

(
r
e
s
p
.

V
i
n
)
Bulk_poly_0.164m
2
PU W/L= 45/32
PD W/L=105/32
PG W/L= 90/45
0.8
1.0
Bulk_poly_0.211m
2
PU W/L= 55/45
PD W/L=150/45
PG W/L=120/55
0.8
1.0
Bulk_poly_0.211m
2
PU W/L= 55/45
PD W/L=150/45
PG W/L=120/55
The SNM (Static Noise Margine) vanishes when reducing
dimensions, thus preventing technology scaling down ! As a result
the Lgate in LP technologies is relaxed w/r to the scaling theory
PG W/L=170/65
in nm
0.0
0.2
0.4
0.6
0.0 0.2 0.4 0.6 0.8 1.0
Vin (resp. Vout)
V
o
u
t

(
r
e
s
p
.

V
i
n
)
PG W/L=170/65
in nm
0.0
0.2
0.4
0.6
0.0 0.2 0.4 0.6 0.8 1.0
Vin (resp. Vout)
V
o
u
t

(
r
e
s
p
.

V
i
n
)
0.0
0.2
0.4
0.6
0.0 0.2 0.4 0.6 0.8 1.0
Vin (resp. Vout)
V
o
u
t

(
r
e
s
p
.

V
i
n
)
PG W/L= 90/45
in nm
0.0
0.2
0.4
0.6
0.0 0.2 0.4 0.6 0.8 1.0
Vin (resp. Vout)
V
o
u
t

(
r
e
s
p
.

V
i
n
)
PG W/L= 90/45
in nm
0.0
0.2
0.4
0.6
0.0 0.2 0.4 0.6 0.8 1.0
Vin (resp. Vout)
V
o
u
t

(
r
e
s
p
.

V
i
n
)
PG W/L=120/55
in nm
0.0
0.2
0.4
0.6
0.0 0.2 0.4 0.6 0.8 1.0
Vin (resp. Vout)
V
o
u
t

(
r
e
s
p
.

V
i
n
)
PG W/L=120/55
in nm
After: T. Skotnicki et al. Innovative materials, devices and CMOS technologies for low-power mobile multimedia, pp. 96-130, IEEE TED, Jan. 2008
82
Nominal
dimensions
All
dimensions
Scaled by
X0.7
All
dimensions
scaled again
by X0.7
SOLUTION FOR ENABLING FURTHER SCALING
LW
A
LW
T
N q
V
vt ox
ox
d c s
th
1 1
2
0
4
3
0
If L and W are scaled X0.7 for

Vth CONST
If L and W are scaled X0.7 for
each CMOS generation, the
Avt has also to be improved
X0.7 in order to maintain the
voltage fluctuation constant
Avt ~ X0.7 or -30% per node
Avt reduction is very difficult with Bulk
Conflict with electrostatics when
L shrink
Conflict when Area shrink
Conflict with cell-leakage
P. Stolk at al., T-ED 1998 (NXP)
Two solutions appear:
1) Tox conflict with cell leakage can be alleviated when using HK
dielectrics
2) N conflict with electrostatics can be removed when going to FDSOI
or FinFET
Ex. 3
Analysis of Vmin (SRAM sustaining
voltage) comparison between doped
channel (Bulk) and undoped channel
87
channel (Bulk) and undoped channel
(FDSOI)
2005 2007 2010 2013 2016 2019
Tolerable Die Fail 0.0001 0.0001 0.0001 0.0001 0.0001 0.0001
Memory Size(Mbits) 8 16 32 64 128 256
Tolerable Bit Fail 1.25E-11 6.25E-12 3.13E-12 1.56E-12 7.81E-13 3.91E-13
Required SNM/ SNM 6.8 6.85 6.95 7 7.15 7.25
SRAM: Minimum Operating Voltage SRAM: Minimum Operating Voltage
Vmin reduction
Ref.: Denis Flandre, UCL Louvain-La-Neuve, BE
LESS VARIABILITY W. SOI - EXPLANATION:
Vt(SOI)/ Vt(Bulk)
=(NaSOI/NaBulk)
1/4
=(1/100)
1/4
1/3
X100 reduction in doping corresponds to X3 reduction in Vth or in Avt !!!
BULK
Avt ~ 3.3
V
dd,nom
=0.9V
0
1
2
3
4
5
6
0 1 2 3 4 5 6 7 8
A
v
t

(
m
V
.
m
)
Tox (nm)
Bulk
UTB
World record by LETI !
O. Weber et al. IEDM 2008 (LETI)
Variability and LP SRAM:
Data : F. Buf
0.5
0.55
0.6
0.65
0.7
0.75
0.8
0.85
0.9
0.95
1
1 1.2 1.4 1.6 1.8 2
V
m
i
n

(
V
)
AVt (mV.m)
F
D
S
O
I
Vmin~0.6V
B
u
l
k
Vmin~0.75V
FDSOI/UTBOX
Avt ~ 1.4
V
dd,nom
=0.9V
Bulk: Avt = 2
FDSOI: Avt = 1.4
CONTINUITY OF SRAM SIZE SCALING:
F. Buf, 2009 VLSI SC
Tutorial 17 :
DEVICE SPEED IMPACT OF DIBL DEVICE SPEED IMPACT OF DIBL
92
V
DD
1
4
3
2
5

2
0
3
4
5
7
6
1
2

2
0
Effective Effective Current Current ((Ieff Ieff) as ) as metric metric of speed of speed
(performance) (performance)
SWITCHING TRAJECTORY WHEN CHARGING /DISCHARGING THE LOAD
I
DN
V =V /2
V
GS
=V
DD
2
I
on
is NOT a speed indicator
dd load
eff
V C
I
speed switching
IN
OUT
1
2
C
L
7
6
V
dd
Ref.: M.H. Na et al., IEDM 2002, p.121.
V
DS
V
DD
/2
V
GS
=V
DD
/2
0

V
DD
I
eff
IS A GOOD SPEED INDICATOR
3
(
\
|
= = +
|
\
|
= = =
2
; ;
2 2
1
dd
D dd G dd D
dd
G eff
V
V V V I V V
V
V I I
3
(
\
|
= = +
|
\
|
= = =
2
; ;
2 2
1
dd
D dd G dd D
dd
G eff
V
V V V I V V
V
V I I
3
(
\
|
= = +
|
\
|
= = =
2
; ;
2 2
1
dd
D dd G dd D
dd
G eff
V
V V V I V V
V
V I I
3
(
\
|
= = +
|
\
|
= = =
2
; ;
2 2
1
dd
D dd G dd D
dd
G eff
V
V V V I V V
V
V I I
3
(
\
|
= = +
|
\
|
= = =
2
; ;
2 2
1
dd
D dd G dd D
dd
G eff
V
V V V I V V
V
V I I
3
(
\
|
= = +
|
\
|
= = =
2
; ;
2 2
1
dd
D dd G dd D
dd
G eff
V
V V V I V V
V
V I I
3
(
\
|
= = +
|
\
|
= = =
2
; ;
2 2
1
dd
D dd G dd D
dd
G eff
V
V V V I V V
V
V I I
3
(
\
|
= = +
|
\
|
= = =
2
; ;
2 2
1
dd
D dd G dd D
dd
G eff
V
V V V I V V
V
V I I
Example of CHARGING
HOW DOES DIBL IMPACT PERFORMANCE (Ieff)
-
Long channel
-
short
SCE Short Channel Effect
SCE
94
-
SCE
DIBL
Vds
DIBL Drain Induced Barrier Lowering
-
short
chann
el
same I
on
same I
oFF
PERFORMANCE (IEFF) PERFORMANCE (IEFF) depends depends on DIBL on DIBL NEW !!! NEW !!!
I
D
V
dd
Techno w/o
DIBL
Techno w.
DIBL
V
dd
/2
Vth
Vth-DIBL
Vd
V
dd
/2 V
dd
Ieff w.DIBL
< Ieff w/o DIBL
V
dd
/2
Vd
Techno
w/o DIBL
Techno
w. DIBL
|
\
|
=
d th g d D
V V V V I
2
1
Ex. 1
Compare Ieff (speed) between two
technologies having same Ion and Ioff
but different DIBL
96
but different DIBL
Same Ion & Ioff
How much improvement due to DIBL reduction ?
97
Same Ion & Ioff
But DIBL = 142 mv in
one techno and 0 mV in
another
261
+40% in Ieff
means +40%
in speed !!!
All the same
technologies, but in one
DIBL has been artificially
cancelled. Then Ioff and
Ion have been re-
adjusted playing with
gate work-function.
186.5
dd load
eff
V C
I
speed switching
Tutorial 18 :
III-V high mobility channels III-V high mobility channels
98
DESCRIPTION
Better mobility and higher limiting velocity lead
to an increase in the transistor Ion current
However, lower density of states in the inversion
layer (larger Dark Space) leads to reduced
inversion density, and realaxed SS, SCE and
DIBL
DIBL
Also the higher dielectric constant of III-V
materials lead to an increase in SS, SCE and
DIBL
Only making a sum of these constructive and
destructive effects permits to assess the real
interest of III-V channel materials
99
High /vsat ~ Small Eg ~ High
Semiconductor
Eff.
Electr
on
mass
Bandgap
(eV) at
300K
Dielectric
constant
Electron
bulk
mobility
(cm
2
/Vs)
Saturation
velocity
(10
7
cm/s)
InSb 0.014 0.17 15.9 77000 5
InAs 0.023 0.36 12. 30000 3.5
GaSb - 0.68 14.8 5000 -
InP - 1.27 12.1 4500 -
GaAs 0.063 1.43 11.5 8000 1.2
Ge
1.59/0.081
0.66 16 3600 0.6
Si 0.98/0.19 1.12 12 1350 1
Virtual III-V (~InGaAs) : eff X10, vsat X3, X1.25, Tinv +2 upto +6.5
How do & Dark Space impact
DIBL and SS in III-Vs (1)
DS
el
dep
el
inv
el
j
ox
Si
V
L
T
L
T
L
X
DIBL
|
|
\
|
+ =
2
2
1 80 . 0
Tinv=Tox+DS.ox/s
B
D Si
dep
qN
T
2
=
el el el ox
L L L
\
( )
(
(
+
|
|
\
|
+ + + =
d
DS
el
dep
el
j
el
inv
ox
Si
dep
inv
ox
Si
V
L
T
L
X
L
T
T
T
q
kT
SS 1
4
3
1 1 10 ln
[8] T. Skotnicki et al., IEEE Trans. On Elec. Dev., Vol.55 ,Issue 1, pp 96-130, 2008
250
300
350
400
D
I
B
L

(
m
V
)
epsilon +3 (+25%)
Tinv+6.5A (+59%)
Reference (Si)
100
110
120
130
d
e
c
)
epsilon 15
(+25%)
Tinv+6.5A
How do & Dark Space impact
DIBL and SS in III-Vs (2)
(b)
0
50
100
150
200
10nA/m 100nA/m 2A/m
D
I
B
L

(
m
V
)
Ioff (nA/m)
60
70
80
90
100
S
S

(
m
V
/
d
e
c
(+59%
Reference
(Si)
(b)
Ex. 1
Estimating impact of constructive
effects on III-V MOSFET speed
103
Inspite of higher mobility, III-V may be slower !
104
X10 VsatX3
DIBLX2
SSX1.3
Readjust gate
workfunction
to same Ioff
X10
VsatX3
DIBLX2
SSX1.3
Readjust gate
workfunction
to same Ioff
Negative
Impact
on speed
Positive
Impact
on Ion
CONCLUSIONS
At low Vdd the impact of bad electrostatics is particularly
strong
III-V materials present very good transport properties,
but much relaxed electrostatics (DIBL and SS)
At nominal transistor length and low Vdd, the destructive
effects, due to electrostatics, preveil over the
constructive effects, due to better transport properties
constructive effects, due to better transport properties
Consequently, the overall impact of the replacement of
Silicon by III-V materials may be negative in terms of
speed
Still remains true, that lagging the transistor length one
node behind nominal permits higher speed than Bulk
(see biblio, next slide), but leads to lower density of
integration
105
Bibliography
How Can High Mobility Channel Materials Boost or Degrade
Performance in Advanced CMOS T. Skotnicki and F. Boeuf,
STMicroelectronics, France, Digest of Tech. Papers. Symposium on
VLSI Technology 2010 (IEEE CAT No CFP**VTS-PRT), pp.TBD
106
Tutorial 19 :
DEVICE STRUCTURS- FDSOI DEVICE STRUCTURS- FDSOI
107
DESCRIPTION
FDSOI especially with thin BOX shows much improved
SCE, DIBL and SS
Such a FDSOI on thin BOX is also called UTBB (Ultra
Thin Body and BOX) SOI
We will explain why UTBB shows better electrostatics
We will explain why UTBB shows better electrostatics
and benchmark it against BULK using MASTAR
We will also show how to transform the Bulk transistor
current model into a model valid for UTBB SOI
Comparison of current and invertor speed (via Ieff) will be
carried out with MASTAR for Bulk and UTBB SOI
108
Ex. 1
WHY DOES UTBB SOI BETTER THAN
BULK IN TERMS OF ELECTROSTATICS ?
109
FDSOI FDSOI devices devices on SOI Wafers on SOI Wafers
K. Cheng et al., VLSI 2009 (IBM)
Krivokapic et al., IEDM
2002(AMD)
M. Fujiwara et al., IEEE SOI
Conference 2005 ( Toshiba)
C. Fenouillet-Beranger
et al., unpublished
N.Sugii et al., IEDM 2008 (Hitachi)
SOTB
DST
R.Chau et al., IEDM 2001(Intel)
Hybrid FDSOI
C. Fenouillet-Beranger et al., IEDM 2009
(ST/LETIl)
et al., unpublished
(ST/LETIl)

0.
FDSOI
BULK
DS
el
dep
el
ox
el
j
ox
Si
V
L
T
L
T
L
X
DIBL
|
|
\
|
+ =
2
2
1 80 . 0
WHY DOES THE PLANAR MOSFET FAIL ?

(Ref.: T. Skotnicki, et al., Electron Device Letters, Vol 9, N 3, 1998)
Suppose : Lel=2/3Lg
REF.: T. Skotnicki, invited paper ESSDERC 2000, pp. 19-33, edit. Frontier Group
T
dep
=1/2Lg
Xj=1/2Lg
mV V 140 1
4
3

20
1

4
3
1 4 . 2
2
2
=
|
|
\
|
+
Suppose : Lel=2/3Lg
DS
el
dep
el
ox
el
j
ox
Si
V
L
T
L
T
L
X
DIBL
|
|
\
|
+ =
2
2
1 80 . 0
WHY DOES THE UTB SOI/SON DO BETTER ?

Xj=Tsi
Suppose : Tsi=1/3Lg & Lel=2/3Lg
T
dep
=Tsi
mV V 75 1
2
1

20
1

2
1
1 4 . 2
2
2
=
|
|
\
|
+
Xj=Tsi=1/3Lg
Tdep=Tsi=1/3Lg
BUT Tdep=1/3Lg is ONLY a
rough simplification. In
reality BOX thickness also
contributes to the effective
Tdep, see next slide =>
20
30
40
50
60
70
80
90
D
I
B
L
(
m
V
)
NMOS FDSOI
Tox 1nm Vdd 1V
Tsi 5nm
Lg 30nm
Lg 40nm
Closed symbol: TCAD simulation
Electrostatics Electrostatics of UTB SOI of UTB SOI
T. Skotnicki et al. IEEE EDL, March88 & IEDM1994
Xj
T
dep
Bulk
T
Si j
T T T
T X
+
DS
el
dep
el
ox
el
j
ox
Si
V
L
T
L
T
L
X
DIBL
|
|
\
|
+ =
2
2
1 80 . 0
C.Fenouillet-Beranger, et al., SOI Conference 2003

0
10
0 20 40 60 80 100 120 140 160
Tbox(nm)
Closed symbol: TCAD simulation
Open symbol: MASTAR
T
BOX
T
Si
box Si dep
T T T +
box
el
el
box
el
box
T
L
L
T
L
T
tgh
|
|
\
|
+
|
|
\
|
|
|
\
|
+ = 09 . 0 1 1 50 . 1 1 21 . 0
UTB
DS
el
box Si
el
ox
el
Si
ox
Si
V
L
T T
L
T
L
T
DIBL

+
|
|
\
|
+ =
2
2
1 80 . 0
For Tbox in the
range of 10-
50nm, 0.3
COMPARE BULK LAST POINT (HK and pockets) WITH FDSOI
Bulk our last
114
Note huge DIBL !
We will pass to FDSOI making the
following changes (next slide):
1) Replace Xj by Tsi (suppose 6nm)
2) Replace Tdep by Tsi+0.3Tbox
(suppose Tbox=10nm)
Bulk our last
optimized point
(HK and pockets)
WE CAN MIMIC FDSOI MODIFYING BULK PARAMETERS:
Tsi is set to 6nm, thus
Xj is also set to 6nm
115
Note improvement in DIBL !
Tdep=9nm (=Tsi+Tbox
=6nm+0.3x10nm) is obtained by
artificially increasing the doping Nbulk
and readjusting Workfunction
Xj is also set to 6nm
USING BUTTON TECHNOLOGY FLAVORS !
For convenience of use, all these and other changes
aiming at mimicing the FDSOI behavior with the Bulk
models, are already programmed in MASTAR
The modifications are sligthly more complex (see next
slide) and calibrated on experimental data
116
slide) and calibrated on experimental data
Nevertheless, pushing the button SOI gives results
similar to what we have obtained manipulating the Bulk
model manually
See next slide
TECHNOLOGY FLAVORS-TRANSLATION TO MASTAR:
Bulk
FDSOI USING BUTTON TECHNOLOGY FLAVORS !
118
Bulk
FDSOI
By press button SOI
FDSOI
By manual parameter manipulation
Ex. 2
INVERTOR SPEED COMPARISON BULK
AND FDSOI
119
SPEED IMPROVEMENT WITH FDSOI !
120
249
+33% in Ieff
means +33%
in speed when
passing from
BULK to
FDSOI !!
186.5
dd load
eff
V C
I
speed switching
BULK
FDSOI (directly after
push button SOI
and adjusting Tsi)
FDSOI
Adjusted to
same Ioff
FDSOI
Adjust
ed to
same
Ioff
BULK
Ex. 3
INVERTOR SPEED FDSOI with Forward
Body Bias
121
FinFETs INCOMPATIBILITY W. BODY-BIAS
whereas FDSOI with thin BOX is !
FDSOI = 2D
FinFET w.
COMMON GATE
gate
drain
Thin Silicon film
FinFET w.
SEPARATE GATES
LOST ADVANTAGE
IN DIBL !
gate
drain
Lg
gate
source
Body-Bias
As on Bulk
Body-Bias
Since
GATE=BACK-BODY
gate
source
Lg
Body-Bias
Since
Gate(N+1)=Body(N)
And NO ROOM for CONTACTS
Fin1 2 3 4
FDSOI
With FBB
340
186.5
SPEED IMPROVEMENT WITH FDSOI and Forward
Body Bias !
123
FDSOI (directly after
push button SOI
and adjusting Tsi)
FDSOI
Adjusted to
same Ioff as Bulk
BULK
With FBB
+82% in Ieff
means +82%
in speed
dd load
eff
V C
I
speed switching
FDSOI
Adjusted to
same Ioff
FDSOI
w. FBB
186.5
BULK
Tutorial 20 :
DEVICE STRUCTURS- DG / FinFET DEVICE STRUCTURS- DG / FinFET
124
DESCRIPTION
DG structures (eg FinFET) show much improved SCE,
DIBL and SS
We will explain why DG/FinFET shows better
electrostatics
current model into a model valid for DG/FinFET
Comparison of current and invertor speed (via Ieff) will be
carried out with MASTAR for Bulk and DG/FinFET
125
DOUBLE GATE DEVICES:

Source Drain
Gate
Source Drain
Gate
Source Drain
Gate
n+
SOURCE
GATE
DRAIN
n+ n+
SOURCE
GATE
DRAIN
n+

Tied gates
(number of
channel > 2)
TRIGATE
Tied Gates side-wall
conduction: DELTA,
FINFET, OMEGAFET,
126
STI
Si-substrate
STI
Si-substrate

TRIGATE
FINFET, OMEGAFET,
Tied gates planar
conduction: DG
SON
Independently
switched gates
planar conduction
Vertical
conduction
SOURCE
FinFET - STATE OF THE ART
FinFET structure in a dense array with
FinFET
Source
Drain
CPP
Fin
Pitch
IBM Allience ,
Albany 2010
FinFET structure in a dense array with
CPP=80nm and Fin pitch = 50nm
DS
el
dep
el
ox
el
j
ox
Si
V
L
T
L
T
L
X
DIBL
|
|
\
|
+ =
2
2
1 80 . 0
WHY DOES THE Double-Gate DO BETTER ?

Xj=1/2Tsi
mV V 32 1
4
1

20
1

12
3
1 4 . 2
2
2
=
|
|
\
|
+
Xj=1/2Tsi
T
dep
=1/2Tsi
Xj=1/6Lg
Tdep=1/6Lg
TECHNOLOGY FLAVORS-TRANSLATION TO MASTAR:
Ex. 1
INVERTOR SPEED COMPARISON BULK
AND DG/FinFET
130
BULK
275
186.5
SPEED IMPROVEMENT WITH FinFET !
131
+47% in Ieff
means +47%
in speed when
passing from
BULK to
FinET !!
dd load
eff
V C
I
speed switching
FinFET (directly after
push button DG )
FinFET
Adjusted to
same Ioff
FinFET
Adjuste
d to
same
Ioff
BULK
CONCLUSIONS (FDSOI & DG/FinFET)
FDSOI as well as DG structures (eg FinFET) show much
improved SCE, DIBL and SS
These features lead to very strong performance
improvement, aspecially at low Vdd (Low Power
applications)
132
Without Body Bias, FinFET gives larger improvement
than FDSOI due to better electrostatics
But FinFET is not compatible with Body Bias, whereas
FDSOI is and provides better Body Factor than Bulk
Therefore with Forward Body Bias, FDSOI gives even
better speed than FinFET !

IDESA CMOS Physics Using MASTAR Part 2of2x

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