ADS PA Workshop

Agilent EEsof EDA
Presentation on Power Amplifier Design using ADS
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Power Amplifier Design using ADS
PA Workshop
Wilfredo Rivas-Torres Technical Support Application Engineer October 12, 2004

Page 1
Outline
Introduction DC and Loadline analysis Bias and Stability LoadPull Matching using Smith Chart Utility SourcePull PA Characterization Did we meet the specification? Optimize/Fine Tune the design Test Design with real world modulated signals Layout
Page 2
ADS Power Amp Design
Why do we need a Power Amplifier?

Power Amplifiers (PA) are in the transmitting chain of a wireless system. They are the final amplification stage before the signal is transmitted, and therefore must produce enough output power to overcome channel losses between the transmitter and the receiver.
Basic Transmitter
Baseband
MOD
Driver
PA
OSC
Page 3
PA requirements
The PA is typically the primary consumer of power in a transmitter. A major design requirement is how efficiently the PA can convert DC power to RF output power. The design engineer has to often concern himself with the Efficiency of the Power Amplifier. Notice that efficiency translates into either lower operation cost (e.g. cellular basestation) or longer battery life (e.g. wireless handheld). PA linearity is another important requirement, the input/ output relationship must be linear to preserve the signal integrity. The design of PAs often involves the tradeoff of efficiency and linearity.
Page 4
PA Design Requirement
RF Output Power: 50 W PEP Input Drive Level : 1 W Output Load (RL): 50 Efficiency () > 50% Bias Voltage: 28 V Device: MRF9045M
Page 5
DC Curves
FET Curve Tracer I_Probe IDS FSL_MRF_MET_MODEL VJ MRF1 MODEL=MRF9045M
V_DC SRC1 Vdc=VDS

Var Eqn
VAR VAR1 VDS =0 V VGS =0 V
V_DC SRC2 Vdc=VGS
PARAMETER SWEEP
ParamSweep Sweep1 SweepPlan="SwpPlan1" Start=2.5 Stop=5.0 Step=0.1
DC
DC DC1 SweepVar="VDS" Start=0 Stop=28*2 Step=0.1 Set drain and gate voltage sweep limits as needed.
Disp T emp
FSL_TECH_INCLUDE FSL_TECH_INCLUDE FTI
DisplayTemplate disptemp1 "FET_curve_tracer"
Page 6
DC Curves
5 4 Load_Line IDS.i, A 3 2
VDsat 1
0 0 5 10 15 20 25
IQ m3
30 VDS 35 40 45 50 55 60
VDsat VDS=0.600 IDS.i=0.562 VGS=3.800000
IQ VDS=28.000 IDS.i=0.717 VGS=3.800000
m3 VDS=33.400 IDS.i=0.004 VGS=2.500000

Page 7
Bias and Stability

MLIN T L20 Subst="MSub1" W=63.668898 mil L=100 mil MLIN TL21 Subst="MSub1" W=63.668898 mil L=100 mil Port P3 Num=3 sc_spr_293D_A025_X9_19960828 C19 PART _NUM=293D474X9025A2 0.47uF sc_mrt_MC_GRM40C0G050_D_19960828 C20 PART_NUM=GRM40C0G100D050 10pF sc_mrt_MC_GRM40C0G050_J_19960828 C25 PART _NUM=GRM40C0G330J050 33pF MLIN T L1 Subst="MSub1" W=63.670079 mil L=2194.444882 mil
MRF9045M_AMP X2
sc_mrt_MC_GRM40C0G050_J_19960828 C8 PART_NUM=GRM40C0G330J050 33pF sr_avx_CR_10_K_19960828 R13 PART _NUM=CR10-150K 15 Ohm VD
Port P2 Num=2
VG Port P1 Num=1 sc_mrt_MC_GRM40C0G050_J_19960828 C7 PART _NUM=GRM40C0G330J050 33pF sc_mrt_MC_GRM40C0G050_J_19960828 C3 PART_NUM=GRM40C0G330J050 33pF
VJ
sr_avx_CR_10_K_19960828 R12 PART_NUM=CR10-680K 68 Ohm
FSL_MRF_MET_MODEL MRF1 MODEL=MRF9045M T SNK=25 RTH=-1 CTH=-1
MSub
sl_tok_LL2012-F_J_19960828 L2 PART_NUM=LL2012-F82NJ 82 nH MSUB MSub1 H=33.6 mil Er=4.2 Mur=1 Cond=5.8E+08 Hu=3.9e+034 mil T =2.8 mil T anD=0.002 Rough=0 mil
MLIN T L22 Subst="MSub1" W=63.668898 mil L=100 mil
MLIN TL23 Subst="MSub1" W=63.668898 mil L=100 mil
Port P4 Num=4
sc_spr_293D_A025_X9_19960828 C24 PART_NUM=293D474X9025A2 0.47uF
sc_mrt_MC_GRM40C0G050_D_19960828 C23 PART_NUM=GRM40C0G100D050 10pF
sc_mrt_MC_GRM40C0G050_J_19960828 C17 PART _NUM=GRM40C0G330J050 33pF
Page 8
Stability Analysis
VDD
P_1Tone PORT1 Num=1 Z=50 Ohm P=polar(dbmtow (-60),0) Freq=fss
VGG MRF9045M_AMP X1
Term R3 Num=2 Z=50 Ohm
S-PARAMETERS
S_Param SP2 Start=1 MHz Stop=3000 MHz Step=1.0 MHz
VDD I_Probe IDD
VGG I_Probe IGG

Var Eqn
StabFact
StabMeas
Mu
MuPrime
V_DC SRC1 Vdc=VDS
V_DC SRC2 Vdc=VGS
VAR VAR3 VDS =28 V VGS =3.8 V
StabFact StabFact1 StabFact1=stab_fact(S)
StabMeas StabMeas1 StabMeas1=stab_meas(S)
Mu Mu1 Mu1=mu(S)
MuPrime MuPrime1 MuPrime1=mu_prime(S)
Page 9
Stability Analysis
3E4 1E4
StabFact1
1E3 1E2 1E1 1 0.0 0.5 1.0 1.5 2.0 2.5 3.0
freq, GHz
Page 10
Impedance Matching
The need for matching circuits is because amplifiers, in order to perform in a certain way(e.g. maximize output power), must be presented with a certain impedance at both the load and the source ports. For example in order to deliver maximum power to the load RL the transistor must have termination Zs and ZL. The input matching network is designed to transform the generator impedance Rs to the optimum source impedance Zs. The output matching network transform the load termination RL (50 ) to the optimum load impedance ZL. A LoadPull measurement will help the designer determine the optimum load impedance ZL.
Page 11
LoadPull Setup
PARAMETER SWEEP ParamSw eep Sw eep2
I_Probe Is_high
Vs_high
V_DC SRC1 Vdc=Vhigh
HARMONIC BALANCE HarmonicBalance HB1 Freq[1]=RFfreq Order[1]=15 P_1Tone PORT1 Num=1 Z=Z_s P=dbmtow (Pavs) Freq=RFfreq
MRF9045M_AMP X2
I_Probe v load Iload S1P_Eqn S1 S[1,1]=LoadTuner Z[1]=Z0
Set Load and Source impedances at harmonic frequencies

Var Eqn
I_Probe Is_low
Vs_low
VAR VAR2 Z_l_2 =Z0 + j*0 Z_l_3 = Z0 + j*0 Z_l_4 = Z0 + j*0 Z_l_5 = Z0 + j*0 Z_s_fund =1.0 + j*0 Z_s_2 = Z0 + j*0 Z_s_3 = Z0 + j*0 Z_s_4 = Z0 + j*0 Z_s_5 =Z0 + j*0
Set these values:

Var Eqn
VAR STIMULUS Pavs=30 _dBm RFfreq=760 MHz Vhigh=28.0 Vlow =3.8
V_DC SRC2 Vdc=Vlow
Var Eqn
VAR Sw eepEquations s11_rho =0.75 s11_center =-0.6 +j*0.1 pts=100 Z0=50
Examples Search
Page 12
LoadPull Contours
PAE_contours_p Pdel_contours_p
m2 indep(m2)=6 Pdel_contours_p=0.914 / 171.170 level=44.195857, number=1 impedance = 2.265 + j3.852
m1 indep(m1)=6 PAE_contours_p=0.914 / 171.180 level=47.552308, number=1 impedance = 2.265 + j3.848
indep(Pdel_contours_p) (0.000 to 46.000) indep(PAE_contours_p) (0.000 to 18.000)

Page 13
Matching using Smith Chart Utility
Page 14
Matching using Smith Chart Utility
Page 15
Output Match
C C1 C=12.975203 pF
Port P1 Num=1
TLIN TL1 Z=50 Ohm E=8.891 F=760 MHz
C C2 C=2.307137 pF
TLIN TL2 Z=50 Ohm E=32.25 F=760 MHz
C C3 C=27.689016 pF
TLIN TL3 Z=22.85 Ohm E=25.92 F=760 MHz
Port P2 Num=2
DA_SmithChartMatch1_output_match_design DA_SmithChartMatch1 F=760 MHz Zs=50 Ohm Zl=(2.300-j*3.800) Ohm Z0=50 Ohm
Page 16
SourcePull Contours
Pdel_contours_p PAE_contours_p
m2 indep(m2)=4 Pdel_contours_p=0.960 / 174.023 level=46.038749, number=1 impedance = 1.016 + j2.609
m1 indep(m1)=4 PAE_contours_p=-0.952 + j0.100 level=58.130703, number=1 impedance = 1.096 + j2.618
indep(PAE_contours_p) (0.000 to 77.000) indep(Pdel_contours_p) (0.000 to 66.000)
Page 17
Matching Circuits
MLIN TL9 Subst="MSub1" W=63.670079 mil L=216.786614 mil MLIN TL8 Subst="MSub1" W=63.670079 mil L=786.342520 mil MLIN TL7 Subst="MSub1" W=199.971654 mil L=596.716535 mil
Output Match
Port P2 Num=2
sc_mrt_MC_GRM40C0G050_C_19960828 C21 PART_NUM=GRM40C0G020C050 2pF
Port sc_mrt_MC_GRM40C0G050_J_19960828 P1 Num=1 C22 PART_NUM=GRM40C0G150J050 15pF
Input Match
Port P1 Num=1
MLIN TL16 Subst="MSub1" W=63.670079 mil L=205.546063 mil
sc_mrt_MC_GRM40C0G050_C_19960828 C25 PART_NUM=GRM40C0G020C050 2pF
sc_mrt_MC_GRM40C0G050_J_19960828 C26 PART_NUM=GRM40C0G220J050 22pF
Port P2 Num=2
Page 18
Complete Design Power Sweep
V_DC SRC1 Vdc=VDS
Vin I_Probe Iin P_1Tone PORT1 Num=1 Z=50.0 Ohm P=dbmtow(Pin) Freq=fo Vdc= input_match X5 output_match MRF9045M_AMP X3 X4 V_DC SRC2 Vdc=VGS I_Probe Iload Vload R R1 R=50 Ohm
Var Eqn
VAR VAR2 fo=760.0 MHz
Var Eqn
VAR VAR1 VDS =28 V VGS =3.8 V Pin=30
HARMONIC BALANCE
FSL_TECH_INCLUDE FSL_TECH_INCLUDE FTI HarmonicBalance HB1 Freq[1]=fo Order[1]=15 SweepVar="Pin" Start=-30 Stop=40 Step=1
Page 19
Power Compression Curve

Output Pin=30.000 Pdel_dBm=45.570
60
Output
40
Pdel_dBm
20
-20
-30
-20
-10
0 Pin
10
20
30
40
Page 20
Gain Compression Curve

LinearGain GainComp Pin=-30.000 ind Delta=60.00 Gp=17.341 dep Delta=-1.771 delta mode ON LinearGain
18 16 14
GainComp
Gp
12 10 8 6 -30 -20 -10 0 10 20 30 40
Pin
Page 21
Power Added Efficiency

60 50 40
m1
m1 Pin=30.000 PAE=49.618
PAE
30 20 10 0 -30 -20 -10 0 10 20 30 40
Pin
Page 22
Getting ready to Optimize the PA

The next step is to optimize the design to meet the requirements. The Designer can take the opportunity to see if other requirements, such as layout will require any changes before proceeding to optimize. Example: we notice that the transistor pads are rather wide and the Tlines leading up to it are not the same width. Since the Tlines are much narrower, we could add a taper so we have a nice transition. We included a MTAPER at the input and output side
MTAPER Taper2 Subst="MSub1" W1=199.971654 mil W2=63.670079 mil L=100.0 mil
dBm(Vload[1]) 41.549
Page 23
Optimization Setup
OPTIM
Optim Optim1 OptimType=Gradient MaxIters=25 DesiredError=0.0 FinalAnalysis="None" NormalizeGoals=no SetBestValues=yes SaveSolns=yes SaveGoals=yes SaveOptimVars=no UpdateDataset=yes SaveNominal=no SaveAllIterations=no UseAllOptVars=yes UseAllGoals=yes SaveCurrentEF=no
GOAL
Goal Goal1 Expr="dBm(Vload[1])" SimInstanceName="HB1" Min=47.0 Max= Weight= RangeVar[1]= RangeMin[1]= RangeMax[1]=
GOAL
Goal Goal2 Expr="dBm(Vload[2])-dBm(Vload[1])" SimInstanceName="HB1" Min= Max=-40 Weight= RangeVar[1]= RangeMin[1]= RangeMax[1]=
Page 24
Optimization Results
InitialEF 67.187 optIter 10 FinalEF 0.000 Goal1 47.003 Goal2 -40.017
MLIN TL39 Subst="MSub1" W=63.670079 mil L=2194.444882 mil opt{ 250 mil to 3500 mil }
Before
M L IN T L39 S u b s t= "M S u b 1 " W = 6 3 .6 7 0 0 7 9 m il L = 5 5 1 .5 9 1 m il o p t{ 2 5 0 m il to 3 5 0 0 m il }
After
Page 25
Optimization Values
TL39.L*1e5/2.54 551.591 TL15.L*1e5/2.54 247.144 TL7.L*1e5/2.54 320.449 TL8.L*1e5/2.54 622.341
TL30.L*1e5/2.54 814.900
TL31.L*1e5/2.54 202.643
TL9.L*1e5/2.54 248.635
TL32.L*1e5/2.54 184.709
TL10.L*1e5/2.54 244.711
Page 26
PA Results
60
m1
40
m1 Pin=30.000 Pdel_dBm=47.003
Pdel_dBm
20
-20 -30 -20 -10 0 10 20 30 40
Pin
Page 27
Power Added Efficiency

80
m3
60
m3 Pin=30.000 PAE=56.736
PAE
40
20
0 -30 -20 -10 0 10 20 30 40
Pin
Page 28
Gain Compression Curve

0 -2
m4 m4 Pin=30.000 Gp-Gp[0]=-0.728
Gp-Gp[0]
-4 -6 -8 -10 -30 -20 -10 0 10 20 30 40
Pin
Page 29
Complex Modulated Signal

16 QAM Spectrum (dBm) 40 20 0 -20 -40 -60 -80 -100 759.50 759.75 760.00 Frequency (MHz) 760.25 760.50
Page 30
16 QAM Modulated Source

SymbolConverter S3 SymbolTime=2/bit_rate Delay=0 sec CodeIn=nrzIn CodeOut=pam4Out LPF_RaisedCosineTimed L4 Loss=0.0 CornerFreq=bit_rate/8 ExcessBw =0.5 Type=Model w ith pulse equalization SquareRoot=Yes Delay=16/bit_rate
Data D1 TStep=Tstep BitTime=1/bit_rate UserPattern="" Type=Prbs SequencePattern=23 Repeat=Yes
SymbolSplitter S1 SymbolTime=1/bit_rate Delay=-1
SymbolConverter S4 SymbolTime=2/bit_rate Delay=0 sec CodeIn=nrzIn CodeOut=pam4Out
QAM_Mod Q1 FCarrier=Fc Pow er=Pc VRef=1.0 V LPF_RaisedCosineTimed Phase=0 GainImbalance=0 L5 PhaseImbalance=0 Loss=0.0 CornerFreq=bit_rate/8 ExcessBw =0.5 Type=Model w ith pulse equalization SquareRoot=Yes Delay=16/bit_rate
SpectrumAnalyzer S9 Plot=None RLoad=DefaultRLoad Start=DefaultTimeStart Stop=DefaultTimeStop Window =none Window Constant=0.0
Page 31
DSP and Analog Circuits Setup

Create a subcircuit with your analog design. You need to add either Circuit Envelope or Transient controller to the analog circuit. We use Circuit Envelope specifically with our PA since we have a Modulated Carrier. Circuit Envelope will also allow the use of Fast Cosim (Automatic Verification Modeling AVM). This will dramatically increase the simulation speed. In the DSP schematic we will create the Modulated Carrier, feed it to the PA and collect the signal samples and spectrum. The DSP schematic contains a Envelope Output Selector component used for interfacing between circuit subnetwork output and the signal processing components.
Page 32
Ptolemy Cosim Schematic
SpectrumAnalyzer S9 Plot=None RLoad=DefaultRLoad Start=DefaultT imeStart Stop=DefaultT imeStop Window=none WindowConstant=0.0
PA
T imedSink RF_in Plot=Rectangular Start=DefaultT imeStart Stop=DefaultT imeStop ControlSimulation=YES
TimedSink Qout Plot=Rectangular Start=DefaultT imeStart Stop=DefaultT imeStop ControlSimulation=YES
QAM_src X2 Pc=Pow
SplitterRF S10
MRF9045M_AMP_CE2 EnvOutShort X1 O1 OutFreq=Fc
SplitterRF S7
PhaseShiftRF P1 PhaseShift=360-168
MatchedLoss M1 Loss=17.0
QAM Source
TimedSink RF_out Plot=Rectangular Start=DefaultT imeStart Stop=DefaultT imeStop ControlSimulation=YES
QAM_Demod Q2 RefFreq=Fc Sensitivity=0.1*(10**((25-Pow)/20)) Phase=0.0 GainImbalance=0.0 PhaseImbalance=0.0
T imedSink Iout Plot=Rectangular Start=DefaultT imeStart Stop=DefaultT imeStop ControlSimulation=YES
SpectrumAnalyzer S8 Plot=None RLoad=DefaultRLoad Start=DefaultT imeStart Stop=DefaultT imeStop Window=none WindowConstant=0.0
Page 33
Fast Cosim Improvements
Simulation Time Benchmark: Total bits: 1024 bits AVM disabled : 410 sec AVM enabled: 13 sec AVM data reuse: 5.5 sec -------------AVM data reuse (16 Kbits): 17.5 sec
Page 34
Cosimulation Results - Spectrum

Carrier Power 25 dBm
20 0 -20 -40 -60 -80 -100 759.0 759.5 760.0 760.5 761.0

20 0 -20 -40 -60 -80 -100 759.0 759.5 760.0 760.5 761.0
freq, MHz
freq, MHz
Page 35
Cosimulation Results - Constellation

1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5
1.5 1.0 0.5

0.0 -0.5 -1.0 -1.5 -1.5 -1.0
-0.5
0.0
0.5
1.0
1.5
Page 36
Cosimulation Results
peakP_in 32.163 peak_avg_in 4.951 avgPin 27.212
peakP_out 47.969
peak_avg_out 3.516
avgPout 44.453
peakP_in 30.000
peak_avg_in 7.788
avgPin 22.212
peakP_out 44.715
peak_avg_out 4.832
avgPout 39.883
Page 37
Cosimulation Results CCDF

9E-1
9E-1
1E-1
1E-1
1E-2
1E-2
1E-3
1E-3
1E-4
1E-4
1E-5 -8 -6 -4 -2 dB 0 2 4 6
1E-5 -8 -6 -4 -2 dB 0 2 4 6
Page 38
EVM vs. Power Measurement

Var Eqn
VAR VAR3 Tstep=1/(bit_rate*oversample) Tstop=num_bits/bit_rate Fc=760 MHz Pow=30 _dBm
Var Eqn
VAR VAR2 bit_rate=1.0 MHz oversample=4 num_bits=4096*4
RES R2 R=50 Ohm
Ref
tes t
EVM Ref
QAM_src X2 Pc=Pow
SplitterRF S7
MRF9045M_AMP_CE2 EnvOutShort X1 O1 OutFreq=Fc
PARAMETER SWEEP
ParamSweep Sweep1 SweepVar="Pow" SimInstanceName[1]="DF1" SimInstanceName[2]= SimInstanceName[3]= SimInstanceName[4]= SimInstanceName[5]= SimInstanceName[6]= Start=18 Stop=30 Step=1 DF DF1 DefaultNumericStart=0 DefaultNumericStop=100 DefaultTimeStart=0 DefaultTimeStop=Tstop SavedEquationName[1]="Tstep"
EVM_WithRef E2 StartSym=10 SymBurstLen=1024 SampPerSym=16 SymDelayBound=-1 NumBursts=2 MeasType=EVM_rms SymbolRate=0.25 MHz RES R1 R=50 Ohm
Page 39
EVM vs. Power Results

EVM vs. Carrier Power
5 4
EVM (%)
3 2 1 0 18 20 22 24 26 28 30
Power (dBm)
Page 40
ADS to VSA link

VSA
MRF9045M_AMP_CE2 Env OutShort X1 O1 OutFreq=Fc
QAM_src X2 Pc=Pow

Var Eqn
VSA_89600_1_Sink RES V1 R1 R=50 Ohm VSATitle="Simulation output" TStep=Tstep SamplesPerSy mbol=16 SetupFile="C:\Program Files\Agilent\89600 RestoreHW=NO SetFreqProp=Y ES
VAR VAR3 Tstep=1/(bit_rate*oversample) Tstop=num_bits/bit_rate Fc=760 MHz Pow=30 _dBm VAR VAR2 bit_rate=1.0 MHz oversample=4 num_bits=1024*16
DF DF1 DefaultNumericStart=0 DefaultNumericStop=100 DefaultTimeStart=0 DefaultTimeStop=Tstop SavedEquationName[1]="Tstep"
Var Eqn
Page 41
VSA Spectrum from ADS Cosim
Page 42
VSA Constellation from ADS Cosim

Page 43
VSA Constellation from ADS Cosim

Page 44
VSA EVM from ADS Cosim

Page 45
PA Layout
MC U R VE2 M LI N TL20 Subst =" M Sub1" W=63. 668898 m l i L=225 m l i M LI N TL21 Subst =" M Sub1" W=63. 668898 m l i L=200 m l i Cur ve2 Subst =" M Sub1" W=63. 668898 m l i Angl e=90 Radi us=100. 0 m l i Nm ode=2
Por t P3 N um =3
M LI N TL42 Subst =" M Sub1" W=63. 668898 m l i L=440 m l i
sc_spr _293D _A025_X9_19960828 C 19 PAR T_NU M =293D 474X9025A2 0. 47uF
sc_m r t _M C _G R M 40C 0G 050_D _19960828 C 20 PAR T_N U M =G R M 40C 0G 100D 050 10pF
M LI N TL41 Subst =" M SU B1" W=63. 6689 m l i L=253. 4234 m l i
sc_m r t _M C _G R M 40C 0G 050_J_19960828 C 17 M LI N TL39 Subst =" M Sub1" M TAPER PART_N U M =G RM 40C 0G 330J050 33pF M LI N TL7 Taper 2 Subst =" M Sub1" W1=199. 971654 m l i W2=63. 670079 m l i L=100. 0 m l i M LI N TL8 Subst =" M Sub1" W=63. 670079 m l i L=622. 343 m l i opt { 100 m l i t o 750 m l i} M LI N TL9 Subst =" M Sub1" W=63. 670079 m l i L=248. 635 m l i opt { 75 m l i t o 500 m l i} M LI N TL10 Subst =" M Sub1" W=63. 670079 m l i L=244. 711 m l i opt { 50 m l i t o 500 m l i}
W=63. 670079 m l i Subst =" M Sub1" L=551. 591 m l i opt { 250 m l i t o 3500 W=199. ml i} 971654 m l i L=320. 449 m l i opt { 75 m l i t o 500 m l i}
M TEE_AD S M TAPER M LI N TL15 Subst =" M Sub1" W=63. 670079 m l i L=247. 144 m l i opt { 50 m l i t o 500 m l i} M LI N TL32 Subst =" M Sub1" W=63. 670079 m l i L=184. 709 m l i opt { 100 m l i t o 500 m l i} M LI N TL30 Subst =" M Sub1" W=63. 670079 m l i L=814. 898 m l i opt { 250 m l i t o 1000 m l i} Taper 1 Subst =" M Sub1" W1=199. 971654 m l i W2=63. 670079 m l i L=100. 0 m l i M LI N TL31 Subst =" M Sub1" W=199. 971654 m l i L=202. 643 m l i opt { 75 m l i t o 750 m l i} sr _avx_C R _10_K_19960828 R 13 PART_N U M =C R 10- 150K 15 O hm M TEE_AD S Tee1 Subst =" M Sub1" W1=199. 971654 m l i W2=199. 971654 m l i W3=63. 668898 m l i sc_m r t _M C_G R M 40C 0G 050_C _19960828 Tee2 Subst =" M Sub1" W1=199. 971654 m l i W2=199. 971654 m l i W3=63. 670079 m l i sc_m r t _M C _G R M 40C 0G 050_J_19960828 C 24 PAR T_N U M =G R M 40C 0G 150J050 15pF C25 PAR T_N U M =G R M 40C 0G 020C 050 2pF
sc_m r t _M C _G R M 40C 0G 050_D_19960828 C 26 PAR T_N U M =G R M 40C0G 090D 050 9pF
Por t P2 N um =2
Por t P1 N um =1
sc_m r t _M C _G R M 40C 0G 050_D _19960828 C 27 PAR T_NU M =G R M 40C 0G 090D 050 9pF sc_m r t _M C _G R M 40C 0G 050_C_19960828 C 28 PAR T_N U M =G R M 40C0G 020C 050 2pF sc_m r t _M C _G R M 40C 0G 050_J_19960828 C 18 PAR T_NU M =G R M 40C 0G 220J050 22pF
sc_m r t _M C_G R M 40C 0G 050_J_19960828 C3 PAR T_N U M =G R M 40C 0G 330J050 33pF
MR F9045_ar t Q1 sr _avx_CR _10_K_19960828 R 12 PAR T_N U M =C R 10- 150K 15 O hm
M LI N TL43 Subst =" M SU B1" W=40 m l i L=90 m l i
sl _t ok_LL2012- F_J_19960828 L2 PAR T_N U M =LL2012- F82N J 82 nH
M Sub
M LI N TL1 Subst =" M SU B1" W=63. 668898 m l i L=100 m l i
SM T_Pad
SM T_Pad Pad1 W=50. 0 m l i L=40. 0 m l i PadLayer =" cond" SM O =5. 0 m l i SM _Layer =" sol der _m ask" PO =0 m l i
SM T_Pa d
M SU B SM T_Pad Pad2 W=70. 0 m l i L=40. 0 m l i PadLayer =" cond" SM O =5. 0 m l i SM _Layer =" sol der _m ask" PO =0 m l i R ough=0 m l i M Sub1 H =33. 6 m l i Er =4. 2 M ur =1 C ond=5. 8E+08 H u=3. 9e+034 m l i T=2. 8 m l i TanD =0. 002
sc_m r t _M C _G R M 40C 0G 050_J_19960828 M LI N TL44 M LI N TL40 Subst =" M Sub1" W=63. 668898 m l i L=200 m l i Subst =" M SU B1" W=63. 668898 m l i M LI N TL23 Subst =" M Sub1" W=63. 668898 m l i L=350 m l i M LI N TL22 Subst =" M Sub1" W=63. 668898 m l i L=200 m l i L=315. 0248 m l i C 21 PART_N U M =G RM 40C 0G 330J050 33pF
SM T_Pad
SM T_Pad
Por t P4 N um =4 sc_m r t _M C _G R M 40C 0G 050_D_19960828 C 22 PAR T_N U M =G R M 40C0G 100D 050 10pF
MC U RVE2 C ur ve1 Subst =" M Sub1" W=63. 668898 m l i Angl e=90 R adi us=100. 0 m l i N m ode=2
Pad3 W=30. 0 m l i L=30. 0 m l i PadLayer =" cond" SM O =5. 0 m l i SM _Layer =" sol der _m ask" PO =0 m l i
sc_spr _293D _A025_X9_19960828 C 23 PAR T_N UM =293D 474X9025A2 0. 47uF
Page 46
PA Layout Generated from Schematic
Page 47
PA Layout Ground Fill
Page 48
Other Possibilities
Run an EM Cosimulation include layout effects in the simulation. Optimize design if necessary. Run Loadpull for IP3 or ACPR. The optimum load would then be a compromise between all the requirements. Use Connection Manager and real PA to validate design and compare vs. simulated results. Create a behavioral data model that can be used to protect you IP yet give access to your design results.
If there is any topic about PA Design and ADS you wish to discuss email me: wilfredo_rivas-torres@agilent.com
Page 49
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ADS PA Workshop

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Agilent EEsof EDA

Presentation on Power Amplifier Design using ADS

Power Amplifier Design using ADS

Wilfredo Rivas-Torres Technical Support Application Engineer October 12, 2004

ADS Power Amp Design

Why do we need a Power Amplifier?

ADS Power Amp Design

ADS Power Amp Design

ADS Power Amp Design

V_DC SRC1 Vdc=VDS

VAR VAR1 VDS =0 V VGS =0 V

V_DC SRC2 Vdc=VGS

FSL_TECH_INCLUDE FSL_TECH_INCLUDE FTI

DisplayTemplate disptemp1 "FET_curve_tracer"

ADS Power Amp Design

VDsat VDS=0.600 IDS.i=0.562 VGS=3.800000

IQ VDS=28.000 IDS.i=0.717 VGS=3.800000

m3 VDS=33.400 IDS.i=0.004 VGS=2.500000

ADS Power Amp Design

Bias and Stability

sc_mrt_MC_GRM40C0G050_J_19960828 C8 PART_NUM=GRM40C0G330J050 33pF sr_avx_CR_10_K_19960828 R13 PART _NUM=CR10-150K 15 Ohm VD

VG Port P1 Num=1 sc_mrt_MC_GRM40C0G050_J_19960828 C7 PART _NUM=GRM40C0G330J050 33pF sc_mrt_MC_GRM40C0G050_J_19960828 C3 PART_NUM=GRM40C0G330J050 33pF

sr_avx_CR_10_K_19960828 R12 PART_NUM=CR10-680K 68 Ohm

FSL_MRF_MET_MODEL MRF1 MODEL=MRF9045M T SNK=25 RTH=-1 CTH=-1

MLIN T L22 Subst="MSub1" W=63.668898 mil L=100 mil

MLIN TL23 Subst="MSub1" W=63.668898 mil L=100 mil

sc_spr_293D_A025_X9_19960828 C24 PART_NUM=293D474X9025A2 0.47uF

sc_mrt_MC_GRM40C0G050_D_19960828 C23 PART_NUM=GRM40C0G100D050 10pF

sc_mrt_MC_GRM40C0G050_J_19960828 C17 PART _NUM=GRM40C0G330J050 33pF

ADS Power Amp Design

P_1Tone PORT1 Num=1 Z=50 Ohm P=polar(dbmtow (-60),0) Freq=fss

Term R3 Num=2 Z=50 Ohm

FSL_TECH_INCLUDE FSL_TECH_INCLUDE FTI

VDD I_Probe IDD

VGG I_Probe IGG

V_DC SRC1 Vdc=VDS

V_DC SRC2 Vdc=VGS

VAR VAR3 VDS =28 V VGS =3.8 V

StabFact StabFact1 StabFact1=stab_fact(S)

StabMeas StabMeas1 StabMeas1=stab_meas(S)

MuPrime MuPrime1 MuPrime1=mu_prime(S)

ADS Power Amp Design

ADS Power Amp Design

ADS Power Amp Design

V_DC SRC1 Vdc=Vhigh

I_Probe v load Iload S1P_Eqn S1 S[1,1]=LoadTuner Z[1]=Z0

Set Load and Source impedances at harmonic frequencies

FSL_TECH_INCLUDE FSL_TECH_INCLUDE FTI

Set these values:

VAR STIMULUS Pavs=30 _dBm RFfreq=760 MHz Vhigh=28.0 Vlow =3.8

V_DC SRC2 Vdc=Vlow

VAR Sw eepEquations s11_rho =0.75 s11_center =-0.6 +j*0.1 pts=100 Z0=50

ADS Power Amp Design

m2 indep(m2)=6 Pdel_contours_p=0.914 / 171.170 level=44.195857, number=1 impedance = 2.265 + j3.852

m1 indep(m1)=6 PAE_contours_p=0.914 / 171.180 level=47.552308, number=1 impedance = 2.265 + j3.848

indep(Pdel_contours_p) (0.000 to 46.000) indep(PAE_contours_p) (0.000 to 18.000)

ADS Power Amp Design

Matching using Smith Chart Utility

ADS Power Amp Design

Matching using Smith Chart Utility

ADS Power Amp Design

TLIN TL1 Z=50 Ohm E=8.891 F=760 MHz

TLIN TL2 Z=50 Ohm E=32.25 F=760 MHz

TLIN TL3 Z=22.85 Ohm E=25.92 F=760 MHz