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Internal Use Only

Internal Use Only Service Manual LG-P925 Date: November, 2011 / Issue 1.0

Service Manual

LG-P925

Table Of Contents

1.

INTRODUCTION

3

4.4 Checking WCDMA Block

4.10

4.11

4.1

78

1.1

Purpose

3

4.5 Checking GSM Block

85

1. Regulatory Information

3

4.6 GPS/WIFI/BT RF components

9

1.3

Abbreviations

5

4.7 GPS/WIFI/BT SIGNAL PATH

94

 

4.8 Power ON Troubleshooting

96

2.

PERFORMANCE

7

 

4.9 Charger Troubleshooting

101

.1 Product Name

7

 

USB Trouble shooting

104

.

Supporting Standard

7

Audio trouble

107

.3

Main Parts : GSM Solution

7

 

Camera trouble(5M/VGA)

118

.4 HW Features

8

 

4.13 Main LCD trouble

1

.5 SW Features

10

.6 HW

13

4.14 SIM detect Trouble shooting

17

.7 P95 Figures

3

4.15 Vibrator Troubleshooting

19

 

4.16 HDMI Troubleshooting

13

3.

TECHNICAL BRIEF

24

4.17 Motion Sensor on/off trouble

134

3.1

Radio Part General

5

4.18 Gyro/Compass sensor troubleshooting

137

3. Radio Part Rx Section

6

4.19 Proximity Sensor on/off trouble

140

3.3 Radio Part Tx Section

7

4.0 Ambient Light Sensor on/off trouble

14

3.4 Radio Part Interfaces

8

4.1

Touch trouble

144

3.5 Digital Baseband (OMAP4430)

9

5. DOWNLOAD

148

3.6 Hardware Architecture

31

3.7 Subsystem (PMB9811_X-GOLDTM66)

3

6. BLOCK DIAGRAM

170

3.8 Power Block

45

 

7. CIRCUIT DIAGRAM

174

3.9 External memory interface

5

3.10 Audio and sound

53

8. BGA PIN MAP

191

3.11 Main (5M pixels) & Sub (VGA) Camera

58

3.1 Display

60

9. PCB LAYOUT

200

3.13 Vibrators

64

10.

10.1

10.

CALIBRATION

213

3.14 HDMI

65

Configuration of Tachyon

13

3.15 Compass Sensor

66

How to use Tachyon

15

3.16 Motion Sensor

67

3.17 Gyro Sensor

68

11.

HIDDEN MENU

218

3.18 Ambient Light & Proximity Sensor

69

12.

DISASSEMBLE GUIDE

240

3.19 Touch Module

70

3.0 Main Features

71

13.

13.1

13.

EXPLODEDVIEW & REPLACEMENT PART LIST

243

 

EXPLODED VIEW

43

4.

TROUBLE SHOOTING

72

Replacement Parts

44

4.1

RF Component

7

13.3

Accessory

78

4. SIGNAL PATH

73

4.3

Checking TCXO Block

76

LGE Internal Use Only

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Copyright © 011 LG Electronics. Inc. All right reserved. Only for training and service purposes

1. INTRODUCTION

1. INTRODUCTION

1.1 Purpose

This manual provides the information necessary to repair, calibration, description and download the features of this model.

1.2 Regulatory Information

A. Security

Toll fraud, the unauthorized use of telecommunications system by an unauthorized part (for example, persons other than your company’s employees, agents, subcontractors, or person working on your company’s behalf) can result in substantial additional charges for your telecommunications services. System users are responsible for the security of own system. There are may be risks of toll fraud associated with your telecommunications system. System users are responsible for programming and configuring the equipment to prevent unauthorized use. The manufacturer does not warrant that this product is immune from the above case but will prevent unauthorized use of common-carrier telecommunication service of facilities accessed through or connected to it.

The manufacturer will not be responsible for any charges that result from such unauthorized use.

B. Incidence of Harm

If a telephone company determines that the equipment provided to customer is faulty and possibly

causing harm or interruption in service to the telephone network, it should disconnect telephone service until repair can be done. A telephone company may temporarily disconnect service as long as repair is not done.

C. Changes in Service

A local telephone company may make changes in its communications facilities or procedure. If these

changes could reasonably be expected to affect the use of the this phone or compatibility with the network, the telephone company is required to give advanced written notice to the user, allowing the user to take appropriate steps to maintain telephone service.

D. Maintenance Limitations

Maintenance limitations on this model must be performed only by the manufacturer or its authorized agent. The user may not make any changes and/or repairs expect as specifically noted in this manual. Therefore, note that unauthorized alternations or repair may affect the regulatory status of the system and may void any remaining warranty.

LGE Internal Use Only

and may void any remaining warranty. LGE Internal Use Only - 3 - Copyright © 011

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Copyright © 011 LG Electronics. Inc. All right reserved. Only for training and service purposes

1. INTRODUCTION

E. Notice of Radiated Emissions

This model complies with rules regarding radiation and radio frequency emission as defined by local regulatory agencies. In accordance with these agencies, you may be required to provide information such as the following to the end user.

F. Pictures

The pictures in this manual are for illustrative purposes only; your actual hardware may look slightly different.

G. Interference and Attenuation

Phone may interfere with sensitive laboratory equipment, medical equipment, etc.Interference from unsuppressed engines or electric motors may cause problems.

H. Electrostatic Sensitive Devices

ATTENTION

Boards, which contain Electrostatic Sensitive Device (ESD), are indicated by the sign. Following information is ESD handling:

by the sign. Following information is ESD handling: • Service personnel should ground themselves by using

Service personnel should ground themselves by using a wrist strap when exchange system boards.

When repairs are made to a system board, they should spread the floor with anti-static mat

which is also grounded.

Use a suitable, grounded soldering iron.

Keep sensitive parts in these protective packages until these are used.

When returning system boards or parts like EEPROM to the factory, use the protective

package as described.

LGE Internal Use Only

protective package as described. LGE Internal Use Only - 4 - Copyright © 011 LG Electronics.

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Copyright © 011 LG Electronics. Inc. All right reserved. Only for training and service purposes

1. INTRODUCTION

1.3 Abbreviations

For the purposes of this manual, following abbreviations apply:

APC

Automatic Power Control

BB

Baseband

BER

Bit Error Ratio

CC-CV

Constant Current – Constant Voltage

DAC

Digital to Analog Converter

DCS

Digital Communication System

dBm

dB relative to 1 milli watt

DSP

Digital Signal Processing

EEPROM

Electrical Erasable Programmable Read-Only Memory

ESD

Electrostatic Discharge

FPCB

Flexible Printed Circuit Board

GMSK

Gaussian Minimum Shift Keying

GPIB

General Purpose Interface Bus

GSM

Global System for Mobile Communications

IPUI

International Portable User Identity

IF

Intermediate Frequency

LCD

Liquid Crystal Display

LDO

Low Drop Output

LED

Light Emitting Diode

OPLL

Offset Phase Locked Loop

LGE Internal Use Only

OPLL Offset Phase Locked Loop LGE Internal Use Only - 5 - Copyright © 011 LG

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Copyright © 011 LG Electronics. Inc. All right reserved. Only for training and service purposes

1. INTRODUCTION

PAM

Power Amplifier Module

PCB

Printed Circuit Board

PGA

Programmable Gain Amplifier

PLL

Phase Locked Loop

PSTN

Public Switched Telephone Network

RF

Radio Frequency

RLR

Receiving Loudness Rating

RMS

Root Mean Square

RTC

Real Time Clock

SAW

Surface Acoustic Wave

SIM

Subscriber Identity Module

SLR

Sending Loudness Rating

SRAM

Static Random Access Memory

PSRAM

Pseudo SRAM

STMR

Side Tone Masking Rating

TA

Travel Adapter

TDD

Time Division Duplex

TDMA

Time Division Multiple Access

UART

Universal Asynchronous Receiver/Transmitter

VCO

Voltage Controlled Oscillator

VCTCXO

Voltage Control Temperature Compensated Crystal Oscillator

WAP

Wireless Application Protocol

LGE Internal Use Only

WAP Wireless Application Protocol LGE Internal Use Only - 6 - Copyright © 011 LG Electronics.

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2. PERFORMANCE

2. PERFORMANCE

2.1 Product Name

LG-P925 : WCDMA 850/1900/2100+GSM850/EGSM/DCS/PCS

(HSUPA 5.8Mbps(cat6)/HSDPA 14.4Mbps(cat10)/GPRS Class10/EDGE Class10)

2.2 Supporting Standard

Item

 

Feature

Comment

Supporting Standard

WCDMA(FDD1,2,8)/EGSM/GSM850/DCS1800/PCS1900

 

with seamless handover Phase 2+(include AMR)

SIM Toolkit

: Class 1, 2, 3, C-E

Frequency Range

WCDMA(FDD1) TX : 1920 – 1980 MHz WCDMA(FDD1) RX : 2110 – 2170 MHz

 

WCDMA(FDD2) TX : 1850 – 1910 MHz WCDMA(FDD2) RX : 1930 – 1990 MHz WCDMA(FDD5) RX : 824 – 849 MHz WCDMA(FDD5) TX : 869 – 894 MHz

EGSM TX

: 880 – 915 MHz

EGSM RX : 925 – 960 MHz

GSM850 TX

: 824 – 849 MHz : 869 – 894 MHz : 1710 – 1785 MHz : 1805 – 1880 MHz : 1850 – 1910 MHz : 1930 – 1990 MHz

GSM850 RX

DCS1800 TX

DCS1800 RX

PCS1900 TX

PCS1900 RX

Application Standard

   

2.3 Main Parts : GSM Solution

Item

Part Name

Comment

AP Chip

OMAP4430 : TI

 

CP Chip

XMM6260 : IMC

 

LGE Internal Use Only

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Copyright © 011 LG Electronics. Inc. All right reserved. Only for training and service purposes

2. PERFORMANCE

2.4 HW Features

Item Feature Comment Form Factor DOP type Battery 1) Capacity Standard : Li-Ion Polymer, 1500mAh
Item
Feature
Comment
Form Factor
DOP type
Battery
1) Capacity
Standard : Li-Ion Polymer, 1500mAh
2) Packing Type : Soft Pack
Size
Standard :
128.8 x 68 x 11.9mm
Weight
162g
With Battery
PCB
Full Layer type, 10 Layers , 0.75t
Stand by time
2G Up to 330 hrs
3G Up to 330 hrs
@
Paging Period 5 (2G)
@
DRX 7 (3G)
Charging time
3 hrs
@
Power Off / 1500mAh
Talk time
2G Up to 260 min
3G Up to 300 min
@
Tx=Max(2G)
@
Tx = 12dBm (3G)
RX sensitivity
WCDMA(FDD1) : -106.7 dBm
WCDMA(FDD2) : -106.7 dBm
WCDMA(FDD5) : -106.7 dBm
EGSM
GSM850
DCS 1800
PCS 1900
: -105 dBm
: -105 dBm
: -105 dBm
: -105 dBm
TX output power
WCDMA/
WCDMA
:
GSM/
24dBm/3.84MHz,+1/-3dBm
GPRS
EGSM
GSM850
DCS 1800
PCS 1900
: 33dBm
: 33 dBm
: 30 dBm
: 30 dBm
EDGE
GSM 900
: 27 dBm
: 26 dBm
: 26 dBm
Class3(WCDMA)
GPRS
DCS 1800
Class4 (EGSM)
compati
PCS 1900
Class4 (GSM850)
bility
Class1 (PCS)
Class1 (DCS)
GPRS
E2 (GSM900)
Class 10
E2 (PCS)
E2 (DCS)
EDGE compatibility
EDGE Class 10
SIM card type
Plug-In SIM
2.85V /1.8V

LGE Internal Use Only

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2. PERFORMANCE

Display

Main LCD (WVGA) TFT Main LCD(4.3”, 480X800)

 

Built-in Camera

3D Camera, VGA secondary

5M AF CMOS CAM 2EA

Status Indicator

No

 

Keypad

Function Key : 4

Function Key:

Side Key

: 4

Home,Back, menu, serach Side Key :

 

Volume up,down, power key, 3D key

ANT

Main : LDS(Laser Direct Structure) type Sub : DPA type(Directed Print Antenna)

 

System connector

5 Pin Micro USB

2.0 HS

Ear Phone Jack

3.5Phi, 4 Pole, Stereo

 

PC synchronization

Yes

 

Memory(AP)

eMMC : 8GB LP-DDR2 : 512MB

 

Speech coding

FR, EFR, HR, AMR

 

Data & Fax

Built in Data & Fax support

 

Vibrator

Built in Vibrator

 

BlueTooth

V2.1 + EDR

 

MIDI(for Buzzer

72 Poly, MP3 Ringtone

 

Function)

Music Player

MP3/ WMA/AAC/AAC+/WAV/AC3

 

Video Player

MPEG4, H.263, H.264 @ Full HD 30fps/ Divx HD

 

Camcorder

MPEG4, H.264, H.263 @ 3D : 720p 2D : 1080p

 

30pfs

Voice Recording

Yes

 

Speaker Phone mode Support

Yes

 

Travel Adapter

Yes

 

CDROM

Yes

 

Stereo Headset

No

 

Data Cable

Yes

 

T-Flash

Yes

Upto 32GB

(External Memory)

 
 

LGE Internal Use Only

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2. PERFORMANCE

2.5 SW Features

Item Feature Comment RSSI 0 ~ 5 Levels Battery Charging 0 ~ 6 Levels Key
Item
Feature
Comment
RSSI
0
~ 5 Levels
Battery Charging
0
~ 6 Levels
Key Volume
0
~ 7 Level
Audio Volume
1
~ 15 Level
Time / Date Display
Yes
Multi-Language
Yes
English, Espanol, Franch, Korean,
Chinese
Quick Access Mode
Phone / Contacts / Messaging /
Menu
PC Sync
Yes
No
Speed Dial
Yes
Voice mail center -> 1 key
Profile
Yes
not same with feature phone setting
CLIP / CLIR
Yes
Phone Book
Name / Number / Email / Chat Id /
Website / Postal addresses /
Organizations / Groups /
BirthdayNotes / Ringtone
There is no limitation on the number
of items.
It depends on available memory
amount.
Last Dial Number
Yes
There is no limitation on the number
of items.
It depends on available memory
amount.
Last Received
Yes
Number
There is no limitation on the number
of items.
It depends on available memory
amount.
Last Missed Number
Yes
There is no limitation on the number
of items.
It depends on available memory
amount.
Search by Number
/ Name
Name / Number
Name / N
Group
Yes
There is no limitation on the number
of items.
It depends on available memory
amount.
Fixed Dial Number
Yes
Service Dial Number
No
Own Number
Yes
Read only

LGE Internal Use Only

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2. PERFORMANCE

   

(add/edit/delete are not supported)

Voice Memo

Yes

Support voice recorder

Call Reminder

No

Yes

Missed call popup

Network Selection

Automatic

 

Mute

Yes

 

Call Divert

Yes

 

Call Barring

No

Yes

 

Call Charge (AoC)

No

Yes

 

Call Duration

Yes

 

SMS (EMS)

There is no limitation on the number of items. It depends on available memory amount.

EMS does not support.

SMS Over GPRS

No

 

EMS Melody / Picture Send / Receive / Save

No

 

No

MMS MPEG4 Send / Receive / Save

Yes

 

Yes

Long Message

MAX 765 characters

MAX 1000 characters

SMS 5 concatenated

SMS 10 concatenated

Cell Broadcast

No

Yes

 

Download

No

Over the Web

 

Game

Yes

 

Calendar

Yes

 

Memo

Yes

There is no limitation on the number of items. It depends on available memory amount.

World Clock

Yes

 

Unit Convert

No

 

Stop Watch

Yes

 

Wall Paper

Yes

 

WAP Browser

No

WAP stack and wml are not supported.

Download Melody / Wallpaper

Yes

Over web browser

SIM Lock

Yes

Operator Dependent

SIM Toolkit

Class 1, 2, 3, C, D

 

MMS

Yes

 

EONS

Yes

 

CPHS

Yes

V4.2

ENS

Yes

 

LGE Internal Use Only

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Copyright © 011 LG Electronics. Inc. All right reserved. Only for training and service purposes

2. PERFORMANCE

Camera

Yes

5M AF / Digital Zoom : x8

JAVA

No

Android do not support JAVA

Voice Dial

No

Yes

 

IrDa

No

 

Bluetooth

Yes

Ver. 2.1+EDR (GAP, A2DP, AVRCP, DUN, FTP, GAVDP, GOEP, HFP, HSP, OPP, SDAP, SPP)

FM radio

Yes

No

 

GPRS

Yes

Class 10

EDGE

Yes

Class 10

Hold / Retrieve

Yes

 

Conference Call

Yes

Max. 7

Max. 6

DTMF

Yes

 

Memo pad

Yes

Rich Note

TTY

Yes

No

 

AMR

Yes

 

SyncML

Yes

 

IM

Yes

Gtalk

Email

Yes

 

LGE Internal Use Only

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Copyright © 011 LG Electronics. Inc. All right reserved. Only for training and service purposes

2. PERFORMANCE

2.6 HW SPEC.

1) GSM transceiver specification

 

Item

 

Specification

Phase Error

Rms : 5° Peak : 20 °

 

Frequency Error

GSM : 0.1 ppm DCS/PCS : 0.1 ppm

EMC(Radiated Spurious Emission Disturbance)

GSM/DCS : < -28dBm

Transmitter Output power

GSM850, EGSM : 5dBm ~ 33dBm ± 3dB DCS/PCS : 0dBm ~ 30dBm ± 3dB

Burst Timing

<3.69us

 

Spectrum due to modulation out to less than 1800kHz offset

200kHz : -36dBm 600kHz : -51dBm/-56dBm

 

GSM850, EGSM :

Spectrum due to modulation out to larger than 1800kHz offset to the edge of the transmit band

1800-3000kHz :< -63dBc(-46dBm) 3000kHz-6000kHz : <-65dBc(-46dBm) 6000kHz < : < -71dBc(-46dBm) DCS, PCS :

1800-3000kHz :< -65dBc(-51dBm) 6000kHz < : < -73dBc(-51dBm)

Spectrum due to switching transient

400kHz : -19dBm/-22dBm(5/0), -23dBm 600kHz : -21dBm/-24dBm(5/0), -26dBm

Reference Sensitivity – TCH/FS

Class II(RBER) : -105dBm(2.439%)

Usable receiver input level range

0.012(-15 - -40dBm)

Intermodulation rejection – Speech channels

±

800kHz, ±

1600kHz

: -98dBm/-96dBm (2.439%)

AM Suppression GSM : -31dBm

-98dBm/-96dBm (2.439%)

-

DCS : -29dBm

Timing Advance

±

0.5T

LGE Internal Use Only

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2. PERFORMANCE

2) WCDMA transmitter specification

Item

 

Specification

Transmit Frequency

BD1: 1920MHz ~ 1980 MHz BD2: 1850~1910 MHz BD5: 824 MHz ~849 MHz

Maximum Output Power

+24 dBm / 3.84 MHz, +1 / -3 dB

Frequency Error

within ±0.1 PPM

Open Loop Power Control

Normal Conditions : within ±9 dB, Extreme Conditions : within ±12 dB

Minimum Transmit Power

< -50 dBm /3.84 MHz

Occupied Bandwidth

< 5 MHz at 3.84 Mcps (99% of power)

Adjacent Channel Leakage Power Ratio (ACLR)

> 33 dB @ ±5 MHz,

> 43 dB @ ±10 MHz

Spurious Emissions |f-fc| > 12.5 MHz

< -36 dBm / 1 kHz RW

@ 9 kHz ≤ f < 150 kHz

< -36 dBm / 10 kHz RW @ 150 KHz ≤ f < 30 MHz

 

< -36 dBm / 100 kHz RW

@ 30 MHz ≤ f < 1 GHz

< -30 dBm / 1 MHz RW

@ 1 GHz ≤ f < 12.75 GHz

< -60 dBm / 3.84 MHz RW @ 869 MHz ≤ f ≤ 894 MHz

< -60 dBm / 3.84 MHz RW @ 1930 MHz ≤ f ≤ 1900 MHz

< -60 dBm / 3.84 MHz RW @ 2110 MHz ≤ f ≤ 2155 MHz

< -67 dBm / 100 kHz RW @ 925 MHz ≤ f ≤ 935 MHz

< -79 dBm / 100 kHz RW

@ 935 MHz < f ≤ 960 GHz

< -71 dBm / 100 kHz RW

@ 1805 MHz ≤ f ≤ 1880 MHz

< -41 dBm / 300 kHz RW

@ 1884.5 MHz < f < 1919.6 MHz

Transmit Intermodulation

< -31 dBc @ 5 MHz & < -41 dBc @ 10 MHz

when Interference CW Signal Level = -40 dBc

Error Vector Magnitude

< 17.5 %, when Pout ≥ -20 dBm

Peak Code Domain Error

< -15 dB at Pout -20 dBm

LGE Internal Use Only

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2. PERFORMANCE

3) WCDMA receiver specification

Item

 

Specification

 

Receive Frequency

BD1: 2110 MHz ~2170 MHz BD2: 1850~1910 MHz BD5: 869 MHz ~ 894 MHz

 

Reference Sensitivity Level

Band1 : BER < 0.001 when Band2 : BER < 0.001 when Band5 : BER < 0.001 when

Îor = -106.7 dBm / 3.84 MHz Îor = -106.7 dBm / 3.84 MHz Îor = -106.7 dBm / 3.84 MHz

Maximum Input Level

BER < 0.001 when

Îor = -25 dBm / 3.84 MHz

Adjacent Channel Selectivity (ACS)

ACS > 33 dB where BER < 0.001 when Îor = -92.7 dBm / 3.84 MHz

&

Ioac = –52 dBm / 3.84 MHz @ ±5 MHz

Blocking Characteristic

BER < 0.001 when Îor = -103.7 dBm / 3.84 MHz

&

Iblocking = -56 dBm / 3.84 MHz @ Fuw(offset) = ±10 MHz

or Iblocking = -44 dBm / 3.84 MHz @ Fuw(offset) = ±15 MHz

Spurious Response

BER < 0.001 when Îor = -103.7 dBm / 3.84 MHz

&

Iblocking = -44 dBm

Intermodulation

BER < 0.001 when Îor= -103.7 dBm / 3.84 MHz

& Iouw1 = -46 dBm @ Fuw1(offset) = ±10 MHz

& Iouw2 = -46 dBm / 3.84 MHz @ Fuw2(offset) = ±20 MHz

Spurious Emissions

< -57 dBm / 100 kHz BW @ 9 kHz ≤ f < 1 GHz

< -47 dBm / 1 MHz BW @ 1 GHz ≤ f ≤ 12.75 GHz

 

Adjust output(TPC command)

 

cmd

1dB

2dB

3dB

+1

+0.5/1.5

+1/3

+1.5/4

Inner Loop Power Control In Uplink

0

-0.5/+0.5

-0.5/+0.5

-0.5/+0.5

-1

-0.5/-1.5 -1/-3

-1.5/-4

 

group(10equal command group)

+1

+8/+12

+16/+24

LGE Internal Use Only

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2. PERFORMANCE

4) HSDPA transmitter specification

Item

Specification

 

Transmit Frequency

BD1: 1920MHz ~ 1980 MHz BD2: 1850~1910 MHz BD5: 824 MHz ~ 849 MHz

 

Maximum

Output

Sub-Test

 

Power

1=2/15,

25.7~20.3dBm / 3.84 MHz 25.7~20.3dBm / 3.84 MHz 25.7~19.8dBm / 3.84 MHz 25.7~19.8dBm / 3.84 MHz

 

2=12/15

3=15/8

4=15/4

 

Sub-Test : 1=2/15, 2=12/15, 3=15/8, 4=15/4

 

Frequency offset from carrier f

 

Measurement

Minimum requirement

Bandwidth

Spectrum

2.5

~ 3.5 MHz

-35-15×( f-2.5)dBc

30 kHz

Emission Mask

3.5

~ 7.5 MHz

-35-1×( f-3.5)dBc

1 MHz

7.5

~ 8.5 MHz

-35-10×( f-7.5)dBc

1 MHz

8.5

~ 12.5 MHz

-49dBc

1 MHz

Adjacent Channel Leakage Power Ratio (ACLR)

Sub-Test : 1=2/15, 2=12/15, 3=15/8, 4=15/4

 

> 33 dB @ ±5 MHz

 

> 43 dB @ ±10 MHz

Error

Vector

< 17.5 %, when Pout ≥ -20 dBm

 

Magnitude

LGE Internal Use Only

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2. PERFORMANCE

5) HSDPA receiver specification

Item

Specification

Receive Frequency

BD1: 2110 MHz ~2170 MHz BD2: 1850~1910 MHz BD5: 869 MHz ~ 894 MHz

Maximum Input Level (BLER or R), 16QAM Only

Sub-Test : 1=2/15, 2=12/15, 3=15/8, 4=15/4

BLER < 10%

or

R >= 700kbps

6) HSUPA Tx, Rx specification

Item

Maximum

Output

Power

Spectrum

Emission

Mask

Adjacent

Channel

Leakage

Power Ratio

(ACLR)

Specification

Sub-Test

1=11/15

25.7~17.3dBm / 3.84 MHz

2=6/15

25.7~16.8dBm / 3.84 MHz

3=15/9

25.7~17.8dBm / 3.84 MHz

4=2/15

25.7~16.8dBm / 3.84 MHz

5=15/15

25.7~20.3dBm / 3.84 MHz

Sub-Test : 1=11/15,

2=6/15, 3=15/9, 4=2/15, 5=15/15

Frequency offset from carrier f

Minimum requirement

Measurement Bandwidth

2.5

~ 3.5 MHz

-35-15×( f-2.5)dBc

30 kHz

3.5

~ 7.5 MHz

-35-1×( f-3.5)dBc

1

MHz

7.5

~ 8.5 MHz

-35-10×( f-7.5)dBc

1

MHz

8.5

~ 12.5 MHz

-49dBc

1

MHz

Sub-Test : 1=11/15,

2=6/15, 3=15/9, 4=2/15, 5=15/15

> 33 dB @ ±5 MHz

> 43 dB @ ±10 MHz

LGE Internal Use Only

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2. PERFORMANCE

7) WLAN 802.11b transceiver specification

Item

 

Specification

Transmit Frequency

2400 MHz ~ 2483.5 MHz ( CH1~CH13 )

Tx Power Level

20dBm under (Europe), ≤ 30dBm under (USA)

Frequency Tolerance

within ±25 PPM

Chip clock Frequency Tolerance

within ±25 PPM

Spectrum Mask

≤ -30 @ fc-22MHz< f <fc-11MHz and fc+11MHz< f <fc+22MHz

≤ -50 @ f < fc-22MHz and f > fc+22MHz

Power ramp on/off time

 

≤ 2us

Carrier Suppression

 

≤ -15dB

Modulation Accuracy (Peak EVM)

 

≤ 35%

Spurious Emissions

< -36 dBm @ 30MHz ~ 1GHz

< -30 dBm above @ 1GHz ~ 12.75GHz

< -47 dBm @ 1.8GHz ~ 1.9GHz

< -47 dBm @ 5.15GHz ~ 5.3GHz

Rx Min input Sensitivity

≤ -76dBm(1Mbps,2Mbps,5.5Mbps,11Mbps) @ FER ≤ 8%

Rx Max input Sensitivity

≥ -10dBm(1Mbps,2Mbps,5.5Mbps,11Mbps) @ FER ≤ 8%

Rx Adjacent Channel Rejection

≥ 35dB @FER ≤ 8%,

interference input signal -70dBm@fc±25MHz(11Mbps)

LGE Internal Use Only

- 18 -

Copyright © 011 LG Electronics. Inc. All right reserved. Only for training and service purposes

2. PERFORMANCE

8) WLAN 802.11g transceiver specification

Item

 

Specification

Transmit Frequency

2400 MHz ~ 2483.5 MHz ( CH1~CH13 )

Tx Power Level

20dBm under (Europe), ≤ 30dBm under (USA)

Frequency Tolerance

within ±25 PPM

Chip clock Frequency Tolerance

within ±25 PPM

Spectrum Mask

≤ -20 @ ±11MHz offset (9Mhz ~ 11MHz)

≤ -28 @ ±20MHz offset (11MHz ~ 20Mhz)

≤ -40 @ ±30MHz offset (20MHz ~ 30Mhz)

Transmitter constellation error (rms EVM)

≤ -5dB@6Mbps, ≤ -8dB@9Mbps, ≤ -10dB@12Mbps,

≤ -13dB@18Mbps, ≤ -16dB@24Mbps, ≤ -19dB@36Mbps,

 

≤ -22dB@48Mbps, ≤ -25dB@54Mbps

Spurious Emissions

< -36 dBm @ 30MHz ~ 1GHz

< -30 dBm above @ 1GHz ~ 12.75GHz

< -47 dBm @ 1.8GHz ~ 1.9GHz

< -47 dBm @ 5.15GHz ~ 5.3GHz

Rx Min input Sensitivity

PER ≤ 10% -82dBm@6Mbps, -81dBm@9Mbps, -79dBm@12Mbps -77dBm@18Mbps, -74dBm@24Mbps, -70dBm@36Mbps -66dBm@48Mbps, -65dBm@54Mbps

Rx Max input Sensitivity

≥ -20dBm(6,9,12,18,24,36,48,54Mbps) @ PER ≤ 10%

Rx Adjacent Channel Rejection

PER ≤ 10%, ACR ≥ 16dB@6Mbps, ACR ≥ 15dB@9Mbps, ACR ≥ 13dB@12Mbps, ACR ≥ 11dB@18Mbps, ACR ≥ 8dB@24Mbps, ACR ≥ 4dB@36Mbps ACR ≥ 0dB@48Mbps, ACR ≥ -1dB@54Mbps

ACR shall be measured by setting the desired signal's strength 3 dB above the rate-dependent sensitivity specified in min input sensitivity

LGE Internal Use Only

- 19 -

Copyright © 011 LG Electronics. Inc. All right reserved. Only for training and service purposes

2. PERFORMANCE

9) WLAN 802.11n transceiver specification

Item

 

Specification

Transmit Frequency

2400 MHz ~ 2483.5 MHz ( CH1~CH13 )

Tx Power Level

20dBm under (Europe), ≤ 30dBm under (USA)

Frequency Tolerance

within ±25 PPM

Chip clock Frequency Tolerance

within ±25 PPM

Spectrum Mask

≤ -20 @ ±11MHz offset (9Mhz ~ 11MHz)

≤ -28 @ ±20MHz offset (11MHz ~ 20Mhz)

≤ -45 @ ±30MHz offset (20MHz ~ 30Mhz)

Transmitter constellation error (rms EVM)

≤ -5dB@6.5Mbps, ≤ -10dB@13Mbps, ≤ -13dB@19.5Mbps,

≤ -16dB@26Mbps, ≤ -19dB@39Mbps, ≤ -22dB@52Mbps,

 

≤ -25dB@58.5Mbps, ≤ -28dB@65Mbps

Spurious Emissions

< -36 dBm @ 30MHz ~ 1GHz

< -30 dBm above @ 1GHz ~ 12.75GHz

< -47 dBm @ 1.8GHz ~ 1.9GHz

< -47 dBm @ 5.15GHz ~ 5.3GHz

Rx Min input Sensitivity

PER ≤ 10% -82dBm@6.5Mbps, -79dBm@13Mbps, -77dBm@19.5Mbps -74dBm@26Mbps, -70dBm@39Mbps, -66dBm@52Mbps -65dBm@58.5Mbps, -64dBm@65Mbps

Rx Max input Sensitivity

≥ -20dBm(6.5,13,19.5,26,39,52,58.5,65Mbps) @ PER ≤ 10%

Rx Adjacent Channel Rejection

PER ≤ 10%, ACR ≥ 16dB@6.5Mbps, ACR ≥ 13dB@13Mbps, ACR ≥ 11dB@19.5Mbps, ACR ≥ 8dB@26Mbps, ACR ≥ 4dB@39Mbps, ACR ≥ 0dB@52Mbps ACR ≥ -1dB@58.5Mbps, ACR ≥ -2dB@65Mbps

ACR shall be measured by setting the desired signal's strength 3 dB above the rate-dependent Sensitivity specified in min input sensitivity

LGE Internal Use Only

- 0 -

Copyright © 011 LG Electronics. Inc. All right reserved. Only for training and service purposes

2. PERFORMANCE

10) GPS receiver specification

Item

Specification

Receive Frequency

1574.42 MHz ~ 1576.42 MHz

Minimum Sensitivity

1 satellite

≥-142dBm, 7 satellites ≥ -147dBm at coarse time aiding

11) Current consumption

   

Stand by

     
 

Bluetooth Off

Bluetooth Connected

 

Voice Call

VT

WCDMA

4.5

mA under

6

mA under

270

mA under

NA

Only

(DRX=1.28)

(DRX=1.28)

(Tx=12dBm)

GSM

4.5

mA under

6

mA under

340

mA under

 

Only

(Paging=5 period)

(Paging=5 period)

(Tx=Max)

** Test condition for Standby current consumption should be as below.

: Measurement time 1hr, with Agilent & CMT JIG

12) Battery life time

 

Stand by

Voice Call

VT

   

330

min over

 

WCDMA

330

(DRX = 1.28)

hours over

(TX = 12dBm, Low Pwr mode)

NA

 

330

hours over

260

min over Level = Max)

 

GSM

(Paging Period = 5)

(TX

LGE Internal Use Only

- 1 -

Copyright © 011 LG Electronics. Inc. All right reserved. Only for training and service purposes

2. PERFORMANCE

13) Charging hour

3.5hour under (1500mAh battery, 1A TA)

13) Charging hour 3.5hour under (1500mAh battery, 1A TA) 14) RSSI indicator (Based on Cell power)

14) RSSI indicator (Based on Cell power)

BAR

WCDMA

GSM/DCS/PCS

 

5

> -74 dBm

> -78 dBm

5

4

-76 ±2dBm

-80 ±2dBm

4

3

-86 ±2dBm

-89 ±2dBm

3

2

-96 ±2dBm

-98 ±2dBm

2

1

-102 ±2dBm

-104 ±2dBm

 

0

< -110 dBm

< -110 dBm

LGE Internal Use Only

- -

Copyright © 011 LG Electronics. Inc. All right reserved. Only for training and service purposes

2. PERFORMANCE

15) Battery indicator

Battery

Bar

Specification

 

BAR 6 (Full)

90% over

 

BAR 6 --> 5

90% 89%

BAR 5 --> 4

70% 69%

BAR 4 --> 3

50% 49%

BAR 3 --> 2

30% 29%

BAR 2 --> 1

15% 14%

remain%

BAR 1 --> 0

5% 4%

Low Battery Pop-up

4% ~ 15% : One Time popup (No call)

Critical Low Battery Pop-up

0% ~ 3% : Every Level change popup (No call)

POWER OFF

0%

2.7 P925 Figures

change popup (No call) POWER OFF 0% 2.7 P925 Figures LGE Internal Use Only -

LGE Internal Use Only

- 3 -

Copyright © 011 LG Electronics. Inc. All right reserved. Only for training and service purposes

3. TECHNICAL BRIEF

3. TECHNICAL BRIEF

The LG-P95 supports UMTS-850, UMTS-1900, UMTS-100, GSM-850, GSM-900, GSM-1800, and GSM-1900 based

GSM/GPRS/EDGE/UMTS. All receivers and the UMTS transmitter use the radio One Zero-IF architecture to eliminate intermediate frequencies, directly converting signals between RF and baseband. The quad-band GSM transmitters use a baseband-to-IF up-conversion followed by an offset phase-locked loop that translates the GMSK-modulated or 8-PSK-modulated signal to RF.

PMU RF6590 GPS IN 1V2 1V8 2V852V65 VCTCXO Filter RD_H Diplexer B946 9 26MHz R
PMU
RF6590
GPS IN
1V2
1V8
2V852V65
VCTCXO
Filter
RD_H
Diplexer
B946 9
26MHz
R D_HX
AFC_DAC XO
VCONT
PAM DCDC
RF6560
VOUT FB
_
GSM_LB_TX
CP_OUT
VCC
GSM_HB_TX
Ant B8
_
B7953
B8_TX
PM_L
TRX4
B8 DPX
Ant_B5
TRX5
B7671
B5_TX
MMMB
Transceiver
B5 DPX
Ant_B2
B7955
B2_TX
PM_H
PMB5712
TRX3
RF6260
B2 DPX
Ant_B1
B7696
B1_TX
TRX2
B1 DPX
Ant B4
_
B7959
B4_TX
TRX6
B4 DPX
XMM6260
Ant_B3
TRX1
DCS
SAW filter
SYS_CLK
SYS_CLK
RX_L1X
RX_L1
SYS_CLK_EN
SYSCLKEN
ST8T
RX_L2X
REF_CLK_EN
REF_CLK_EN
RX L2
_
BGSF18D
DI3_TX_DAT
Di3_TX_DAT
RX_M2X
DI3_TX_DATX
Di3_TX_DATX
RX_M2
RX_H2X
DI3_RX_DAT
Di3_RX_DAT
RX_H2
DI3_RX_DATX
Di3_RX_DATX
RX_H1X
RX_H1
RX M1X
_
RX_M1
[Figure 3-1] Total Block diagram of RF part

LGE Internal Use Only

- 4 -

Copyright © 011 LG Electronics. Inc. All right reserved. Only for training and service purposes

3. TECHNICAL BRIEF

3.1 Radio Part General

SMARTi™ UE2 is a highly integrated UMTS/GSM-transceiver, with all necessary features to enable multi mode,

multi band mobile cellular devices. It incorporates a fully integrated dual mode receiver with main and diversity

chains, 2 multi band TX outputs, control, Digitally controlled crystal support, a measurement interface,

DigRFV3.09 compliant high speed data and control interface, a multi mode timer unit and all necessary front end

signals for the complete RF Engine control. Overall the IC directly supports RF engines with up to 4 GSM bands

and typical 4 UMTS (can be less or more depending on engine setup) bands without additional discrete RF path

switches.

W1 Power GW PMU Control GW5 GW6 W1 Xtal GW Main Receiver G1300 GW5 GW6
W1
Power
GW
PMU
Control
GW5
GW6
W1
Xtal
GW
Main
Receiver
G1300
GW5
GW6
DigRF 3G
FE CTRL
V3_09
(GPO/SPI)
Ctrl
Lo band
Det
Hi band
Ctrl
DC/DC

[Figure 3-2] SMARTi UE2 main feature

-. 3GPP release 7 (HSPA+)

-. Up to 5 UMTS-FDD / 4 EDGE Bands

* Band I ~ VI, VIII ~ X

* 28Mbps DL / 11.5Mbps UL (HSPA+ 64 / 16QAM)

* EGPRS MSC 33 / 34

* 14.4Mbps HSDPA / 5.76Mbps HSUPA (cat 10 / 6)

-. Standard DigRF V3.09 interface to Digital BB

-. Multi-Mode / Multi-Band Single-Chain Tx Concept

LGE Internal Use Only

- 5 -

Copyright © 011 LG Electronics. Inc. All right reserved. Only for training and service purposes

3. TECHNICAL BRIEF

3.2 Radio Part Rx Section

For the RX section the IC features 6 RX inputs, 4 of those might be used for multi mode receive, this means they can be used for GSM and UMTS (the IC can be reconfigured to achieve in spec performance) operation. The highband input are for UMTS operation only. The multi mode inputs include first LNA (for GSM and UMTS) without and additional external LNA and inter-stage filter. The receiver structure is optimized for compressed mode operation, thus only a single base band chain is used, saving area and optimizes power consumption. The receiver AGC can be aligned to the UMTS frame structure. Additionally to the normal receiver the IC contains a diversity receiver part, enabling up to 4 band Rx diversity for GSM and UMTS mode without external LNA’s and inter-stage filters.

RD_L1 S&H RD_L1X G Mode RD_L ADC S&H RD_LX LPF FIR MUX MUX RD_M ADC
RD_L1
S&H
RD_L1X
G Mode
RD_L
ADC
S&H
RD_LX
LPF
FIR
MUX
MUX
RD_M
ADC
RD_MX
LPF
HPF
FIR
3G Mode
0/90°
RD_H
RD_HX
HPF
RX_L1
RX synthesizer
DigRF
RX_L1X
RX_L
S&H
RX_LX
0/90°
G Mode
RX_M1
ADC
S&H
RX_M1X
LPF
FIR
MUX
MUX
RX_M
ADC
RX_MX
LPF
HPF
FIR
3G Mode
RX_H1
RX_H1X
HPF
RX_H
RX_HX

LGE Internal Use Only

[Figure 3-3] 2G / 3G Rx Block Diagram

- 6 -

Copyright © 011 LG Electronics. Inc. All right reserved. Only for training and service purposes

3. TECHNICAL BRIEF

3.3 Radio Part Tx Section

The TX features 2 RF outputs, which are directly matched to 50 impedance for easy connection to external power amplifiers, which reduces significantly external component count. Those 2 outputs are high power, small signal polar modulated outputs for the GSM and UMTS system, with low sensitivity to PA harmonics. They are capable to perform GMSK or 8-PSK as well as UMTS modulation signals with excellent noise performance, thus no inter-stage filter in between transceiver and PA is required. The transmitter outputs are broadband, one

covers all low bands (Band V, VI, and VII), the higher band output covers all GSM and UMTS bands Band I, II, III, IV,

IX and X. The output driver is capable to support high output powers to enable low cost single chain PA’s.

The IC features additionally closed loop power control for GSM and for UMTS, thus supporting TRP requirements

in cooperation with the power amplifier and the antenna design. There is one input ball for the power detector

voltage coming from the PA, and one input ball for the RF signal fed back to the TRX. The complete loop circuits are implemented in the digital domain, which enables a high reliability of the loop performance for both

standards. 1C HIP AM-Path 1 bit sign DIG RF TX-Disruptor 3G 0C HIP PM-Path 1
standards.
1C HIP
AM-Path
1 bit
sign
DIG RF
TX-Disruptor
3G
0C HIP
PM-Path
1 bit
sign
AM-Path
PM-Path
Feedback RX
to signal
chain
Detector ADC
[Figure 3-4] Single Chain PA’s Tx Architecture
FIFO
G
Modulator
I/Q-Chain
I/Q-Chain
I/Q to R/Phi
I/Q to R/Phi
Feedback Sifnal
Processing

LGE Internal Use Only

- 7 -

Copyright © 011 LG Electronics. Inc. All right reserved. Only for training and service purposes

3. TECHNICAL BRIEF

3.4 Radio Part Interfaces

The base band is connected via a DigRF V3.09 high speed data interface with a maximum clock frequency of 312 MHz. The pure digital interface enables the digital baseband to shrink efficiently, as all the analog functionality is within the RFIC. All data and control traffic is multiplexed via the RX and TX interface lines. The IC features a high level programming model enabling the complete compressed mode operation of the device in an RF engine environment. It handles RX and TX power control, also incorporating the calibration data. The complete timing is optimized for compressed mode operation of the transceiver, it controls the front end components of the engine (PA´s, switches, Antenna switches etc…). Additionally a SPI control bus for front end component control is available on the IC, which also enables the read back of data from external components, thus the handling of functions like PA saturation, mismatch detection, overheating (incorporated in the closed loop power control) can be adopted.

Data DI3_RX_DAT RLVDS P/S DI3_RX_DATX Framer Driver Converter Control SYS_CLK SysClk Driver SYS_CLK_EN
Data
DI3_RX_DAT
RLVDS
P/S
DI3_RX_DATX
Framer
Driver
Converter
Control
SYS_CLK
SysClk
Driver
SYS_CLK_EN
Digital
RF IC
Baseband IC
31 MHz
PLL
Control
Retimed
Retimed
DI3_TX_DAT
Data
Data
RLVDS
Phase
S/P
DI3_TX_DATX
Deframer
Receiver
Correlator
Converter
Data

[Figure 3-5] DigRF Architecture

Table 3-1. DigRF I/F path’s Data Rates

DigRF Architecture Table 3-1. DigRF I/F path’s Data Rates LGE Internal Use Only -  8

LGE Internal Use Only

- 8 -

Copyright © 011 LG Electronics. Inc. All right reserved. Only for training and service purposes

3. TECHNICAL BRIEF

3.5 Digital Baseband (OMAP4430)

The OMAP4430 high-performance multimedia application device is based on enhanced OMAP TM architecture and used 45-nm technology. The device is associated with power and audio integrated circuits(ICs) that is called TWL6030 and TWL6040.

Handset

Ear

HF speakers

microphones x2 speaker x2 Headset Vbat Backup battery Micro Speakers Hands -free Boost Buck- a
microphones x2
speaker
x2
Headset
Vbat
Backup
battery
Micro
Speakers
Hands -free
Boost
Buck-
a
mplifier
Power
boost
Vibrator/
Main
Gas
Vibrators
a
ctuator
battery
gauge
x2
Charger
TWL6030
TWL6040
interface
Keypad
USB
Headset
*
0
#
charger
WL1283 BT/FM/GPS/WLAN
7
8
9
4
5
6
1
2
3
DVFS Ctrl
I2C Ctrl
I2C Ctrl
Audio
AC
charger
BQ24156
S/PDIF
SR
I2C1
MCASP
MCPDM
DMIC
KEYBOARD
SLIMBUS1
SDMMC5
Micro USB
USBA0-
MCBSP2
MCBSP1
MCSPI2
OTG
UART2
I2C2
Other flash
memory
eMMC
(JC64)
SDMMC2
GPMC
(Nor, Nand,
OneNand,
)
SDMMC4
MCSPI4
Mobile TV
2 or 4x
NVM LPDDR 2
LPDDR2
memory
LPDDR21
SDRAM
LPDDR22
C2C
MCSPI3
OMAP4430
USBB1-
MCBSP2
HSI
3G
ULPI/HSIC
UART3
SD/MMC
SDMMC 1
MCBSP2
IrDA
UART3
NFC
NFC
I2C4
MCSPI
DISPC2
DISPC2
RFBI
CVIDEO
CCP2
MCSPI1
RFBI
I2C2
DSI1
I2C2
DSI2
HDMI
CSI2-A
I2C3
CSI2-B
HDMI companion
(LS+ESD+StepUp)
Fingerprint
TVout
Primary
Secondary
Touchscreen
Main display
Touchscreen
Subdisplay
/ Slide pad
camera
camera
PicoDLP®

OMAP4430 Block Diagram (Typical Connections Shown)

LGE Internal Use Only

- 9 -

Copyright © 011 LG Electronics. Inc. All right reserved. Only for training and service purposes

3. TECHNICAL BRIEF

Cortex-A9 MPU Subsystem Two ARM Coretex-A9 MPCore

IVA-HD Subsystem The IVA-HD subsystem is a set of video encoder/decoder hardware accelerators. It supports up to 1080p x 30 fps, slow-motion camcorder, triple play (HD and SD capture and JPEG capture), real-time transcoding of up to 720p, and video conferencing up to 720p. The IVA-HD supports:

MPEG-1/2/4, Divx 5.02, H.263 P0 (encode/decode) and P3 (decode), H.264 Annex G (scalable baseline profile up to 720p), H.264 BL/MP/HP, H.264 Annex H(partial), Stereoscopic video, JPEG(encode/decode), VC-1 SP/MP/AP, AVS-1.0, RealVideo 8/9/10 (decode only), On2 VP6.2/VP7 (decode only) Display Subsystem Display controller

: Three video pipelines, one graphic pipelines, and write-back pipeline. Two LCD outputs, One TV output. Remote frame buffer interface (RFBI) module Two MIPI display serial interface (DSIs) High-definition multimedia interface (HDMI) encoder

: HDMI 1.3, HDCP 1.2, and DVI 1.0 compliant

Deep-color mode support (10-bit for up to 1080p and up to 12-bit for 1080i/720p) NTSC/PAL video encoder ABE (Audio Back End) Subsystem The ABE subsystem handles audio processing for the application. It manages the audio and voice streams between the Cortex-A9 MPU subsystem and/or DSP, and the physical interfaces. Imaging Subsystem (ISS) The ISS processes data coming from the image, memory, and IVA-HD subsystem. The ISS is responsible for multimedia applications such as : camera viewfinder, video record with up to 1080p at 30 fps with digital zoom and still image processing, such as image capture up to 16 Mp with digital zoom and rotation. The ISS supports a pixel throughput of up to 200Mp/s. It assures good performance with sensors up to 16 Mp and more (higher resolution can be achieved through multiple passes). 2D/3D Graphics Accelerator The 2D/3D graphics accelerator subsystem in based on POWERVR SGX540 core from Imagination Technologies. The SGX can process different data types simultaneously.

In addition to its processing elements, an extensive set of peripheral interfaces enables communication with all necessary external devices.

LGE Internal Use Only

- 30 -

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3. TECHNICAL BRIEF

3.6 Hardware Architecture

<System HW Block>

FM_ANT LCD 4.3” EAR_PIECE(RCV) EARO . DSI McBSP1(PCM) FM_L/R LCD SPK SPK FM AUXLR BT/WLAN/FM
FM_ANT
LCD 4.3”
EAR_PIECE(RCV)
EARO
.
DSI
McBSP1(PCM)
FM_L/R
LCD
SPK
SPK
FM
AUXLR
BT/WLAN/FM
(480x800)
McBSP3(I2S)
MIC1
MIC1
UART2
(WL1271)
TWL6040
Touch
MIC2
I2C2
MIC2
SDIO
LED
5
HiFi & PCM Voice
HS_MIC
3.5
pi Ear MIC(Ear_Jack)
Backlight
I2C2
McPDM
PDM
Driver IC
HSOLR
Compass
I2C4
3.5
pi Ear_Jack
I2C4
Proximity
MCLK
FM_ANT
OMAP4430
38.4MHZ
Light Sensor
2Gb-2ch
POP
SDRC
LPDDR2
GPIO_2
Motor
TCXO Driver
DMTIMER8_PWM_EV5
3D CAMERA
e
MMC 8Gb
(
)
SDMMC2
T
I2C1
5M AF
GPIO
Fuel gauge
MIPI(P)
VT
CSI1
0.3M
PMB5712
FEM
UART3
A-GPS
5M AF
LNA
MIPI
CSI2
MIPI(S)
HDMI
McSPI4
USIF3
DigRF
MCP
IPC_SRDY
Keypad
5M CAM Flash
I2C2
1Gb
GPIO_119
GPIO_34
IPC_MRDY
NAND
NAND
GPIO_120
GPIO_35
512Mb
MCSPI2(PCM)
I2S2
XMM6260
DDR
SDMMC1
DDR
MIPI_HSI
MIPI_HSI
KB_COL/ROW
UART1
Gyro
I2C4
GPIO_82
USB
Key LED
I2C
I2C3
UART4 USB
I2C1
JTAG
JTAG
USIM1
Accelerometer
USIF1
JTAG
JTAG
I2C PMIC_AP 32.768KHz (TWL6030) VCHG PWR-ON KEY Charge r MUIC Coin cell Battery VBAT Figure.
I2C
PMIC_AP
32.768KHz
(TWL6030)
VCHG
PWR-ON KEY
Charge
r
MUIC
Coin cell
Battery
VBAT
Figure. Block Diagram
32.768KHz
32.768KHz

LGE Internal Use Only

- 31 -

Copyright © 011 LG Electronics. Inc. All right reserved. Only for training and service purposes

3. TECHNICAL BRIEF

3.7 Subsystem (PMB9811_X-GOLD TM 626)

The X-GOLD™ 626 is a 3GPP Release 7 dual-mode baseband modem which is expected to connect to an application processor in order to create a high-end smartphone solution. It can be used to create a data-card solution as well. This section provides a high-level view of the chip architecture. More details can be found in the sections that follow. The X-GOLD™ 626 can be broken into 6 major subsystems: Backbone, Connectivity, Audio, 2GL1, 3GL1, and PMU. Each of these subsystems play important roles for operation of the modem.

Audio Backbone Audio 6 I2S1 DSP1 6 ARM11 CAPCOM0 Audio I2S2 32kB I-Cache DSP2 32kB
Audio
Backbone
Audio
6
I2S1
DSP1
6
ARM11
CAPCOM0
Audio
I2S2
32kB I-Cache
DSP2
32kB D-Cache
8kB I-TCM
ABW
SCU
CAPCOM1
8kB D-TCM
DSP
DSP
Interrupt
Timer
STM
CEU
CGU
GPTU0
DMA1
DMA2
L2 Cache
RTC
SPCU
GPTU1
8-ch
2-ch
256kB
Shared Mem
CPU XBAR
Bridge
Peripheral XBAR
GUCIPH
LMU
Connectivity
RAM
GSI
Shared
62
1
EBU
LMU
Mem
FCDP
ROM
3
(+2)
USIM
2
USB-FS
(+4)
3GL1
2GL1
ICU
GSM
3GCU
USI
COMRAM
2G DSP1
2G DSP2
6
Cipher
USB-HS
5
GSM
Channel
Equalizer
MCU
ORX
USIF1
HSDPA
Timer
Decoder
Accelerator
R99ORX
ARM7
ETM7
2
HSIRX
USB-HSIC
ICU
HSORX
SYNC_TX
DSP
DSP
USIF5
8
TxBitProc
Timer
Interrupt
MIPI HSI
TxMod
DPE
MACPHY
Rake
(+5)
USIF3
Searcher
IR
DL-MACPHY
Rake
OLP
RF IF
UL-MACPHY
3G DSP
Memory
MRAM
7
SD-MMC1
2
7
I2C1
DigRF 3.09
7
(+7)
MIPI PTI
PMU
2 (+10)
SD1
SD2
PCL/GPIO
POR
(VDDCore)
(VDDIO)
5
DAP
31
VANA
VUSB
VSIM
VMIPI
USIF2
VPLL
VPMU
VRTC
SSC
Measurement
Control Unit
TSMU
BB_ArchitectureOverview.vsd
Provided Under NDA
ETM11

Fig.3.7 Architecture Block Diagram of X-GOLD™ 626

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3. TECHNICAL BRIEF

3.7.1 The Backbone Subsystem

The backbone subsystem contains elements which handle the main processing in the system. The protocol stack is expected to execute here. The ARM™1176 acts as the main CPU, it is connected via the CPU XBAR with the internal memories (RAM, ROM), the external bus interface, and the 8-channel DMA (DMA1). There is level 1 cache and tightly-coupled memory incorporated within the ARM which help with the performance of the CPU. A level 2 cache is also added to this which helps even further with the system performance. Given that the modem is expected to support high data rates for HSDPA (category 14) and HSUPA (category 7), these additional elements are necessary. The ARM™1176 also has the capability of controlling the peripherals in the device that are connected to the Peripheral XBAR via a bus bridge. This 32-bit multi master AHB bus is connected to all peripherals.

The Clock and System Control Unit (CSC) consists of the system control unit (SCU), system power control unit (SPCU) and the clock generation unit (CGU). These units are responsible for the reset handling, the clock multiplexing and switching and the power control of the device.

3.7.2 The Connectivity Subsystem

There are a rich set of peripherals included in the connectivity subsystem which allow interfacing to external devices. It is required that we have connectivity for inter-process communications (IPC) with the AP, SIM card support, external interrupts, external memory cards, trace and debug, external device control (A-GPS), and general purpose I/O. For IPC there are 3 generic interfaces: USB HSIC, MIPI HSI, and USIF3 (which provides UART and SPI operation). SIM and FS-USB interfaces are dedicated to the SIM-Card. External interrupts are included for waking the modem from low power modes. There is a SD-MMC interface for utilizing memory cards in datacards applications. The USB-HS, USIF1, and MIPI PTI interfaces can be used for tracing purposes. NAND flash can be connected to the FCDP interface for supporting memory accesses. External devices can be controlled by the baseband through the I2C interface. There are also generic input/output pins that can be used to connect the baseband to external components in the system. These peripherals occupy a different number of pins as indicated in Fig.3.7. The number in parentheses refer to additional signals which are available only as alternate functions behind other functions.

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3. TECHNICAL BRIEF

3.7.3 2GL1 Subsystem

While the upper layers of the modem software stack run on the main CPU, physical layer processing takes place in the layer-1 subsystems. The 2GL1 subsystem contains 2 DSPs, which help with layer-1 processing in 2G modes. The added DSP helps with higher performance use cases such as receive diversity and multi-slot classes. It contains a set of dedicated HW peripherals (equalizer, etc) and connects to the digital RF interface.

3.7.4 3GL1 Subsystem

While in 3G modes, assistance is required from the 3GL1 subsystem. An ARM™7 CPU deals with the communication of the 3G subsystem with the stack SW running on the ARM™1176 and handles the scheduling of the different activities between the 3G HW peripherals (RAKE, DPE, Searcher, HSDPA Inner Receiver, Rel99- and HSDPA-Outer Receiver). The signal processing tasks are handled by the 3G DSP. The up-link and downlink data will be buffered in the COMRAM which connects to the ARM™1176 system via the MACPHY peripherals. Connection to the RF is managed by the DigRF peripheral.

3.7.5 The Integrated PMU Subsystem

The integrated PMU subsystem contains all of the supplies necessary for powering the baseband in the platform. There are two step down converters for the digital core voltage (SD1) and digital IO voltage (SD2). Seven linear voltage regulators provide the supply voltages for various internal and external components.

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3. TECHNICAL BRIEF

3.7.6 Audio Subsystem

An overview of the Audio Subsystem hardware architecture can be found in Figure 3.7.6. The three main entities relevant for the audio processing are

• ARM™1176 Embedded Microcontroller Unit core (ARM™1176)

• Embedded Digital Signal Processor cores (DSPs)

• 3rd Party IP CODEC

Digital Signal Processor cores (DSPs) • 3rd Party IP CODEC LGE Internal Use Only Fig.3.7.6 Audio

LGE Internal Use Only

Fig.3.7.6 Audio Subsystem Block Diagram

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3. TECHNICAL BRIEF

ABE Overview

The audio back end (ABE) module is a subsystem that manages various audio and voice uplink and downlink streams between the initiator (the Cortex™-A9 microprocessor unit [MPU], digital signal processor [DSP], or direct memory access [DMA] controller) and the peripheral physical interfaces (multichannel buffered serial port [McBSP], SLIMbus®, digital microcontroller [DMIC], multichannel pulse density modulation [McPDM], and multichannel audio serial port [McASP]). The ABE module handles the audio processing for the applications. It receives voice or audio samples from the initiator or the external audio chip (TWL6040 or other) and sends them to the peripheral interfaces or memories after processing. The ABE can perform buffering of audio samples, mix audio with a voice down stream and/or a microphone up stream (sidetone), and can apply some post-processing. The ABE integrates the following modules:

• Peripheral physical interfaces:

– Three McBSP modules

– One McASP module

– One mobile industry processor interface (MIPI) SLIMbus interface

– One DMIC module to support up to six mono and up to three stereo digital microphones

– One McPDM module to support interconnect with an external audio chip.

• Audio engine (AE):

– Performs real-time signal processing like sample rate conversion, filtering, equalizing, and side-tone

– Audio traffic controller (ATC):

• Performs data move in the ABE

• Generates interrupt requests to the DSP and Cortex-A9 interrupt controllers

– On-chip memory:

• 64KB of RAM; 32-bit data memory (DMEM)

• 6KB for coefficient memory RAM (CMEM)

• 18KB for sample memory RAM (SMEM)

• 8KB for program memory RAM (PMEM)

• Local L4 interconnect (L4_ABE) to:

– L3 interconnect

– Cortex-A9 MPU

– DSP

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3. TECHNICAL BRIEF

The Cortex-A9 MPU and the DSP have private access to the L4_ABE interconnect. All other initiators (sDMA) can access the L4_ABE only through the L3 interconnect.

• Timers:

– Four general-purpose (GP) timers

– One watchdog timer

• Clock and reset management: Receives clock and reset signals from the device PRCM module. The audio

engine operates from the DPLL_ABE, which is in the PRCM module. The ABE modules can be supplied with clock signals from the DPLL_ABE or the DPLL_PER. The ABE has its own hardware reset domain (AUDIO_RST).

• Power management: The ABE module is power-independent. It has its own dedicated power domain (PD_ABE)

and can execute audio processing with the rest of the device in retention or in off mode.

• Each peripheral in the ABE can be accessed directly by the initiator when the AE is bypassed (legacy mode, for

old software compatability). Figure 3.7.6.1 is a high-level overview of the ABE.

Figure 3.7.6.1 is a high-level overview of the ABE. LGE Internal Use Only Fig.3.7.6.1 Audio Back

LGE Internal Use Only

Fig.3.7.6.1 Audio Back End

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3. TECHNICAL BRIEF

AE Subsystem

The AE is the core of the ABE subsystem. It performs the real-time audio processing within the ABE:

mixing, muxing, volume control, smooth muting, sampling rate conversion, and side-tone equalization. The AE subsystem also processes and executes all data transfers. To optimize the global processing, the ATC moves the data. An IRQ/DMA controller controls system IRQ and DMA requests. Input DMA requests come from the ABE peripherals, and output DMA requests and IRQ are generated and sent to the system (Cortex-A9 MPU interrupt controller, DSP interrupt controller, system DMA [sDMA], and the DSP enhanced direct memory access controller [eDMA]). The AE subsystem contains:

• AE: processes and executes the micro code with its own RAMs:

– SMEM

– CMEM

– PMEM

• DMEM contains the audio buffer and communication circular buffer.

• ATC: Transfers data between all modules in the ABE

• IRQ DMA controller

For more information about the audio engine, see the Audio Back-End (ABE) and Hardware Abstraction Layer

(HAL) Addendum.

Multichannel Audio Serial Port

The multichannel audio serial port (McASP) is a GP audio serial port. It is useful for intercomponent (DIT) transmission. The McASP is intended to be flexible enough so that it may connect gluelessly to audio A/D, D/A, CODEC and SPDIF transmit physical layer components. McASP has the following features:

• 2-interconnect slave interface supports:

– One interconnect configuration slave interface

– One interconnect DMA slave interface

– 32-bit data bus width

– 16- and 32-bit access

– 10-bit address bus width

– Burst not supported

– WNP

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3. TECHNICAL BRIEF

• Supports idle request/acknowledge protocol

• Buffers for transmit/receive operations

• DMA requests (one per direction) link with the 32-bit register

• Up to four transmit channels

• Four serializers implemented

• Support of disconnect protocol

Multichannel Buffered Serial Port

There are three McBSP instantiations: McBSP1 through McBSP3. They provide a full-duplex direct serial interface between the ABE and external devices, such as other modems, BT chips, or codecs. Because of its versatility, a McBSP can accommodate a wide range of peripherals and clocked frame-oriented protocols (I2S, PCM, TDM). List of recommended usage per McBSP:

• MCBSP1: BT voice/audio data

• MCBSP2: Digital baseband (DBB) voice data

• MCBSP3: MIDI FM data

The McBSP has the following features:

• Interconnect slave interface (internal interconnect) supports:

– 32-bit data bus width

– 8-, 16-, and 32- bit access

– 10-bit address bus width

– Burst not supported

– WNP

• Buffers for transmit/receive operations: 128/128 32-bit words (McBSP1, 2, 3)

• Interrupts configurable in legacy mode (two requests) or PRCM-compliant (one request)

• DMA requests (one per direction) triggered with programmable FIFO thresholds

• Multidrop support

• Serial interface description

• Four-pin configuration (McBSP1, 2, 3)

• Full-duplex communication

• Multichannel selection modes

• Support to enable or block transfers in each channel

• Up to 128 channels for transmission and for reception

• Supported protocols

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3. TECHNICAL BRIEF

• Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially connected A/D and D/A devices:

– I2S-compliant devices

– TDM bus devices

– PCM devices

• A wide selection of data sizes: 8, 12, 16, 20, 24, and 32 bits

• Supports idle request/acknowledge protocol

• Clock generation support:

– Independent clocking and framing for reception and for transmission up to 48 MHz

– Support for external generation of clock signals and frame-synchronization (frame-sync) signals

– A programmable sample rate generator for internal generation and control of clock signals and frame-sync signals

• Support of disconnect protocol

Multichannel Pulse Density Modulation Module

The McPDM is a proprietary interface based on multichannel pulse density modulation. The module consists of five downlinks and three uplinks. Two other uplink channels are reserved for status communication. The McPDM has the following features:

• Interconnect slave interface (L4_ABE internal interconnect) supports:

– 32-bit data bus width

– 10-bit address bus width

– Burst not supported

– WNP

• Full-duplex communication:

– Five audio downstream channels

– three audio upstream channels

• RX/TX FIFO operations: 32-bit words per channels

• Complies with PRCM interrupts:

– One to the MPU subsystem

– One to the DSP subsystem

• DMA requests (one per direction) triggered with programmable FIFO thresholds; depending on the FIFO implementation, one per channel or one per direction

• Decimation filter for embedded uplink paths (five paths if two status paths)

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3. TECHNICAL BRIEF

• Oversampling for embedded uplinks (five paths)

• Sigma delta for embedded downlinks (three paths)

• Deserializers for the two status upstream channels

• Support of disconnect protocol

Interface

Phoenix audio comprehend 3 different interfaces:

1. I2C interface for the information with non-critical latency.

2. PDM interface for the audio signal and the register associated with audio path (gain, control)

3. GPO for audio IC interacting with Phoenix audio (drivers, power provider)

Some “dual access” registers (addresses 0x0A to 0x1B) can be accessed by both I2C and PDM. By default, the concurrent access is disabled and only the PDM interface can write in these registers. The R/W access can be switched to I2C only by setting bit I2CSEL. A concurrent access by both I2C and PDM interfaces is also possible by setting bit PDMI2CSEL. In this last case, Phoenix audio will not provide arbitration of simultaneous accesses and the functionality of the system will not be guaranteed if this happens. In this mode, the software must ensure that access by one interface is complete before using the other one, in order to avoid any collision

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3. TECHNICAL BRIEF

PDM Interface

The PDM interface is the over-sampled serial interface used for communication between Phoenix audio and the application processor companion chip. PDM_CLK is 19.2 MHz or 17.64 MHz and data rate represented by PDM_FRAME is respectively 1.92 MHz or 1.764 MHz. Words of data can be transmitted from OMAP to ABB chip using PDM_DN line (downlink path) but words of data can also be transmitted from ABB chip to OMAP using PDM_UP line (uplink path). Both chips are synchronized through PDM_FRAME line. By default OMAP is the owner of PDM_FRAME but during transmission, ABB chip can send back to OMAP some low-latency data by using frame line. This will be detailed later in this chapter. Phoenix audio PDM interface consists of three different modes, Normal mode, Command mode and Test mode. Normal mode and Command mode are intended to use with OMAP McPDM. Test mode is designed for evaluation and production test.

Test mode is designed for evaluation and production test. Fig.3.7.6.2 PDM Interface connectivity between Phoenix and

Fig.3.7.6.2 PDM Interface connectivity between Phoenix and OMAP4 McPDM

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3. TECHNICAL BRIEF

3.7.7 Vocoder Subsystem

FR, HR, EFR speech channels (TCH/FS, TCH/HS, TCH/EFS)

• NAMR/WAMR speech channels over GMSK and 8PSK

• Mandatory sub-functions for speech channels:

– Discontinous transmission (DTX)

– Voice activity detection (VAD)

– Background noise calculation

• Fullrate and halfrate data channels (F14.4, F9.6, F4.8, F2.4, H4.8, H2.4)

3.7.8 Memory Subsystem

The X-GOLD™626 can use the general term SDRAM as a shortcut for Mobile DDR SDRAM.

A total of up to four external memories is supported, chip selects can be dynamically allocated to one of the two

external memory controllers of X-GOLD™626. Only two memory devices can be connected to the SDRAM

controller if DDR support is required.

3.7.9 Battery Management – Hardware Configurations

The X-GOLD™626 chip has an internal PMU that will provide power supply for the chip itself, memory and the

attached RF. The X-GOLD also holds a measurement unit that can perform all necessary battery measurements

through external HW. This is sufficient for a modem only design where charging is controlled by another chip.

3.7.10 Clocking

The clocking system is based on 2 different clocks, a 26 MHz reference clock generated within the RF Engine and

a 32 kHz real-time clock (RTC) generated in the baseband. The 26 MHz clock provided by the RF engine is the

main reference clock for the RF circuit and the X-GOLD™626. Also other system components may be supplied

with 26 MHz reference clocks. A 32 kHz oscillator located at the X-GOLD™626 supplies the RTC with the reference

clock for the real time clock application, as well as provides a low power standby clock for system sleep mode

operation. This clock is available also for other system components like GPS.

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3. TECHNICAL BRIEF

3.7.11 USB

The XMM™6260 platform provides two USB interfaces compliant to the USB2.0 standard:

• High speed interface (480 Mbps) for communication with external devices acting both as host or device

• Full speed interface (12 Mbps) for communication with the UICC using the IC-USB standard acting as host

The USB solution is based on USB controller hardware IP, which is integrated in the X-GOLD™626 baseband chip including both USB transceivers for high and full speed and the USB Stack software that implements the different USB device classes and features. The HS USB component supports the following features:

• Modem connection for Dial Up Networking and AT command interface (CDC-ACM)

• Tracing over USB (CDC-ACM)

• File System Access (Mass Storage Device)

• Audio over USB

• Suspend/Resume and Remote Wakeup and selective suspend (for power saving)

• Software download

The IC-USB component supports the following features:

• UICC-Terminal USB interface according to ETSI TS 102 600 (ICCD / Mass Storage / CDC-EEM)

• Suspend/Resume and Remote Wakeup (for power saving)

The USB HSIC component supports the following features:

• Modem connection for DialUp Networking and AT command interface (CDC-ACM)

• Tracing over USB (CDC-ACM)

• Suspend/Resume and Remote Wakeup, device triggered suspend (for power saving)

• LPM according to "USB 2.0 Link Power Management Addendum", Remote Wakeup (for power saving)

• Wake-up by sideband signals (optional for optimized power consumption)

• Software download, flashless boot

The USB HSIC component supports the following features:

• Modem connection for DialUp Networking and AT command interface (CDC-ACM)

• Tracing over USB (CDC-ACM)

• Suspend/Resume and Remote Wakeup, device triggered suspend (for power saving)

• LPM according to “USB 2.0 Link Power Management Addendum”, Remote Wakeup (for power saving)

• Wake-up by sideband signals (optional for optimized power consumption)

• Software download, flashless boot

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3. TECHNICAL BRIEF

3.8 Power Block

3.8.1 General

Since P920 uses two individual chips, XMM6260 (IFX Modem) uses integrated PMIC and OMAP4430 uses

TWL6030 as a main PMIC.

P95

3.8.2 XMM6260 (IFX Modem)

X-GOLD™ 626 is a GSM/UMTS/GPRS/EDGE/HSDPA/HSUPA Baseband Controller with integrated modem power

management unit. This system on chip is designed with the latest low power CMOS process technologies which

provides significant performance to meet the ever increasing demands of the cellular subscriber market for

feature rich terminals at lowest power consumption and a very competitive cost position.

B

V

VDD_SD1

B

V

Ball FSS eFuses Digital Control MU SSC VDD_VBAT_SD1 VREF L SD1 2x SD1_SW Bandgap C
Ball
FSS
eFuses
Digital Control
MU
SSC
VDD_VBAT_SD1
VREF
L
SD1
2x
SD1_SW
Bandgap
C VREF
AGND
SD1
SD1_FB
C
C
VSD1
VSS_SD1
ANAMON
ANAMON
VDD_VSD2
VSIM
VDD_VBAT_SD2
LSIM
L
C VSIM
SD2
2x
SD2_SW
SD2
SD2_FB
VPMU
C
C
XGOLD626 PMU
VSD2
LPMU
VSS_SD2
C VPMU
VRTC
VIO_12
LRTC
LIO_12
C VRTC_BUF
C VRTC
C
VIO_12
VUSB_IO
LUSB_IO
C VUSB_IO
VPLL
LPLL
RESET_PWRDWN_N
C VPLL
POR
VUSB_ANA
OSC
LUSB_ANA
C VUSB_ANA
VUSB_PD
Battery
DCDC
LUSB_PD
C VUSB_PD
Supervision
Supervision
Battery
C VDD_VBAT
TM_EN
VSS_PMU
VDD_VBAT_PMU
TRIG_B
ON1
ON2_N
RESET_BB_N
REF_CLK_EN
M1
M2
M3
M4

VDD_SD2

Figure. LGP920 Modem Power Block Diagram

P925

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3. TECHNICAL BRIEF

3.8.3 TWL6030

The TWL6030 is an integrated Power Management IC for applications powered by a rechargeable battery. The device provides 7 configurable step-down converters with up to 1.5A capability for Memory, Processor Core, IO, auxiliary, pre-regulation for LDOs, etc. It contains also 11 LDO regulators which can be supplied either from battery or from pre-regulated supply. Power up / power down controller is configurable and can support any Power up / down sequences (EPROM based). The Real Time clock (RTC) provides 32KHz output buffer, seconds, minutes, hours, day, month, and year information as well as Alarm wake up. The TWL6030 supports 32KHz clock generation based on crystal oscillator. The device integrates also a Switch mode charger allowing faster battery charge, higher efficiency & less power dissipation. The TWL6030 generates power supplies for OMAP4 and operates together with TWL6040 which includes all audio and related detection features. For audio IC parameters, see TWL6040 Datasheet. In addition TWL6030 can be used as PMIC for several other processors, thanks to the programmable startup/shutdown controller and default supply voltage levels. The TWL6030 is available in an nFBGA package 7.0mm x 7.0mm with 0.4mm ball pitch.

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