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Prof.

Connors ECEN/CSCI 4593 Computer Organization and Design Exam-2

Practice Exam

Name:

Write your initials at the top of each page. You are allowed one 8.5X11 page of notes. No interaction is allowed between students. Do not open this booklet until you are told to do so. Show all of your work for possible partial credit.

Problem 1 Problem 2 Problem 3 Problem 4 Problem 5 Problem 6 Problem 7

30 pts 20 pts 30 pts 20 pts 15 pts 15 pts 30 pts

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Prof. Connors Question 1. (30 points)

Practice Exam

Give a concise answer to each of the following questions. Limit your answers to 20 words. (a) What is the functionality of a BTB?

(b) If a compiler could ll all the delay slots of a machine, would there be any need for branch prediction?

(c) What are the main functionalities of a page table?

(d) Why does a two-level address translation algorithm require a smaller amount of main memory than a one-level algorithm?

(e) What is set associativity?

(f) What is the purpose of dirty (modied) bit in a cache tag store entry?

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Prof. Connors

Practice Exam

(g) Describe the page faults that can potentially occur during a two-level address translation.

(h) Which cache model has the fastest HIT LATENCY (fully-associative, set-associative, directmapped)?

(i) Which cache design (write-back or write-through) uses a dirty bit?

(j) When a item of data is written repeatedly, which has better memory system utilization, writeback or write-through cache?

(k) What are the two localities (characteristics) that caches exploit?

(l) What are the three types of cache misses?

(m) True/False - Capacity misses are generally eliminated by increasing the cache associativity? (n) True/False - A 4-stage pipeline that uses a combined EXECUTE and MEMORY stage will not have a LOAD-stall.

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Prof. Connors Question 2. (20 points) This question covers cache and pipeline performance analysis.

Practice Exam

(Part A) Write the formula for the ideal number of cycles in a pipelined execution (use N for instructions and P for pipestages within one instruction):

(Part B) Write the formula for the average memory access time assuming one level of cache memory:

(Part C) For a data cache with a 80% hit rate and a 1-cycle hit latency, calculate the average memory access latency. Assume that latency to memory and the cache miss penalty together is 100 cycles. Note: The cache must be accessed after memory returns the data.

(Part D) Calculate the performance of a standard 5-stage pipeline with full register bypassing. The data cache (for loads and stores) is the same as described in Part C and 30% of instructions are loads and stores. The instruction cache has a hit rate of 90% with a miss penalty of 50 cycles. Calculate the CPI of the pipeline, assuming everything else is working perfectly. Assume the load never stalls a dependent instruction and assume the processor must wait for stores to nish when they miss the cache. Finally, assume that instruction cache misses and data cache misses never occur at the same time.

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Prof. Connors Question 3. (30 points) (Part A) Dependence detection

Practice Exam

This question covers your understanding of dependences between instructions. Using the code below, list all of the dependence types (FLOW, ANTI, OUTPUT). You should list them in the table (example INST-X to INST-Y FLOW) instead of drawing a graph. I0: I1: I2: I3: I4: I5: ADD SUB ADD MUL LDW AND R3 R0 R4 R4 R2 R2 = = = = = = R1 + R0; R3 - R4; R5 + R6; R3 + R1; MEM[R2 + 0]; R2 & R1; To Instruction Type of Dependence

From Instruction

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Prof. Connors (Part B) Forwarding logic design

Practice Exam

For this problem you are to design a forwarding unit for a 5-stage pipeline processor. The forwarding unit returns the value to be forwarding to the current instruction. There are three places that the values for register RS and register RT can come from: decode stage (register le), memory stage, and write-back stage.
DECODE STAGE INFORMATION RS INDEX(5 bits) RS REG VALUE (32bits) RT INDEX(5 bits) RT REG VALUE (32bits)

MEMORY STAGE INFORMATION REGISTER INDEX (5 bits) VALUE (32 bits) WRITE_ENABLE (1 bit) REGISTER INDEX (5 bits) VALUE (32 bits) WRITE_ENABLE (1 bit) WRITEBACK STAGE INFORMATION VALUE FOR RT FORWARDING UNIT VALUE FOR RS

The write-back and memory stage information consists of: INDEX- explaining which inight register index is to be written VALUE- the value that is to be written ENABLE- whether or not the instruction in the stage is writing. The decode stage simply states the register index (for RS and RT) and the corresponding register value from the register le.

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Prof. Connors

Practice Exam

Generally three values could exist, one of which the forwarding unit should choose for each of the RS and RT register value requests. The memory stage has value MEM, the write-back stage has value WB, and the register le has value RS-REG or RT-REG. Using the table below which contains information about all of the instruction stages, indicate which value should be forward to the current instruction: MEM, WB, RS-REG, or RT-REG. Each line represents a Forwarding unit evaluation, there is no connection between evaluation lines in the table. You do not need to worry about hazard detection, only value bypassing. Evaluation 0 1 2 3 4 Mem Stage Index Write 5 1 7 0 10 1 17 0 19 0 Write-Back Stage Index Write 23 0 16 1 10 1 12 1 19 0 Register Stage RS-Index RT-Index 6 7 16 8 11 10 12 12 19 25 RS Value RT Value

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Prof. Connors Question 4. (20 points)

Practice Exam

Question 4. (20 points) This problem covers your knowledge of branch prediction. The following gure illustrates three possible state machines.
T T T 11 N 10 T N 10 11 T

01 N 0 00 N N LAST-TAKEN UP-DOWN N

01 T 00 N

AUTOMATON-A3

NOTES: Last taken predicts taken on 1 Up-Down predicts taken on 11 and 10 Automata A3 predicts taken on 11 and 10 Fill out the tables below for each branch predictor. The execution pattern for the branch is TNNTTN.

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Prof. Connors Execution Time 0 1 2 3 4 5 Branch Outcome T N N T T N State Before 0 State After Correct or Incorrect

Practice Exam

Table 1: Table for last-taken branch predictor. Execution Time 0 1 2 3 4 5 Branch Outcome T N N T T N State Before 01 State After Correct or Incorrect

Table 2: Table for up-down branch predictor. Execution Time 0 1 2 3 4 5 Branch Outcome T N N T T N State Before 01 State After Correct or Incorrect

Table 3: Table for Automata-A3 branch predictor. Calculate the prediction rates of the three branch predictors:

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Prof. Connors Predictor Last-taken Up-Down Automata-A3 Prediction accuracy

Practice Exam

Question 5. (15 points) This problem cover physical cache design and cache access. (Part A) Design a 32KB direct-mapped data cache that uses a 16-bit address and 4 bytes per block. Calculate the following: (a) How many bits are used for the byte offset? (b) How many bits are used for the set (index) eld? (c) How many bits are used for the tag? (Part B) Cache access: Assume the following 6-bit physical address sequence generated by the microprocessor:
Time Access 0 001101 1 110010 2 111111 3 001100 4 011100 5 101001 6 111110 7 101001

The cache uses 2 bytes per block. Assume a 2-way set assocative cache design that uses the LRU algorithm. Assume that the cache is initially empty. Hint, rst determine the TAG, SET, and INDEX eld.
BLOCK 0 BLOCK 1

SET 0 SET 1

(Part C) Derive the hit ratio for the access sequence in Part B. Page 10 of ??

Prof. Connors Question 6. (30 points) The memory architecture of a machine X is summarized in the following table. Virtual space Page size PTE size 8GB space 16K bytes 4 bytes

Practice Exam

(Part A) Assume that there are 10 bits reserved for the operating system functions (protection, replacement, valid, modied, and Hit/Miss- All overhead bits) other than required by the hardware translation algorithm. Derive the largest physical memory size (in bytes) allowed by this PTE format. Make sure you consider all the elds required by the translation algorithm.

(Part B) How large (in bytes) is the page table?

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Prof. Connors

Practice Exam

(Part C) In the picture below (the algorithm for a 1-level translation scheme), place the values for the known elds of the virtual memory and physical memory in the diagram. If the value to be used in a box is known, ll in the value. Otherwise, indicate the number of bits associated with each rectangular box. Assume that you answer from Part A denes the actual physical memory for the processor. (Hint: Determine how many page frames in your memory and how to index those page frames).
VAD

x + PAPTE PTBR

access physical memory

PTE

PAD

access physical memory

D page fault OS brings data page no Data in PM

MBR

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Prof. Connors Question 7. (20 points)

Practice Exam

This question covers virtual memory access. Assume a 5-bit virtual address and a memory system that uses 4 bytes per page. The physical memory has 16 bytes (four page frames). The page table used is a one-level scheme that can be found in memory at the PTBR location. Initially the table indicates that no virtual pages have been mapped. Implementing a LRU page replacement algorithm, show the contents of physical memory after the following four virtual access: 11100, 01000, 00000, 01000. Show the contens of memory and the page table information after each access sucessfully completes in Figure A, B, C, and D. Each page table entry (PTE) is 1 byte.
virtual space 00 page 000 page 001 page 010 page 011 page 100 page 101 page 110 page 111 0 4 8 12 16 20 24 28 01 1 5 9 13 17 21 25 29 10 2 6 10 14 18 22 26 30 11 3 7 page frame 00 11 15 PTBR 19 M 23 27 31 M M M page frame 11 M M M M page frame 10 page frame 01 physical (main) memory 00 01 10 11

Figure 1: The initial contents of memory.

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Prof. Connors

Practice Exam

physical (main) memory 00 01 10 11 page frame 00 page frame 01 page frame 10 page frame 11
Figure 2: Figure A (after access 11100).

physical (main) memory 00 01 10 11 page frame 00 page frame 01 page frame 10 page frame 11
Figure 3: Figure B (after access 01000).

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Prof. Connors

Practice Exam

physical (main) memory 00 01 10 11 page frame 00 page frame 01 page frame 10 page frame 11
Figure 4: Figure C (after access 00000).

physical (main) memory 00 01 10 11 page frame 00 page frame 01 page frame 10 page frame 11
Figure 5: Figure D (after access 01000).

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