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Timing Basics and Physical Design Concepts

Prasanna Kumar

Following topics will be covered


1. 2. 3. 4. 5. 6. Types of Delays Constraints Timing Paths and how to constrain them Wire Load Models Static Timing Analysis Physical Design Flow

TYPES OF DELAYS
Intrinsic Delay

Cell Delay or Gate Delay Net Delay or Wire Delay or Interconnect Delay Transition Delay or Slew Propagation Delay

Intrinsic Delay
Ideal Gate working with zero slew or transition and zero load The delay internal to the gate. This is from the input pin of the cell to the output pin of the cell. This is due to internal capacitance of the transistors. This is largely dependent on size of the transistors, increasing the size of the transistor increases internal capacitances.

Cell Delay or Gate Delay


Gate delay =function of (input transition (slew) time, Cnet+Cpin). or Gate delay =function of (input transition (slew) time, Cload). where Cload=Cnet+Cpin Cnet-->Net capacitance Cpin-->pin capacitance of the driven cell Cell delay is also same as Gate delay

NOTE : A slow input transition time will slow the rate at which the cells transistors can change state logic 1 to logic 0 (or logic 0 to logic 1), as well as a large output load Cload (Cnet + Cpin), thereby increasing the delay of the logic gate.

Net Delay or Wire Delay


Net delay is the difference between the time a signal is first applied to the net and the time it reaches other devices connected to that net. It is due to the finite resistance and capacitance of the net. It is also known as wire delay.
Wire delay = function of (Rnet, Cnet+Cpin) This is output pin of the cell to the input pin of the next cell

Transition Delay
Transition delay or slew is defined as the time taken by signal to rise from 10 %( 20%) to the 90 %( 80%) of its maximum value.

Propagation Delay
Propagation delay of a gate or cell is the time it takes for a signal at the input pin to affect the output signal at output pin. For any gate propagation delay is measured between 50% of input transition to the corresponding 50% of output transition. Propagation delay depends on the input transition time (slew rate) and the output load

Constraints
There are 3 types of constraints 1. Design Rule Constraints 2. Optimization Constraints 3. Environmental Constraints Design rule constraints These are implicit constraints .Design rule constraints reflect technology-specific restrictions your design must meet in order to function as intended. Optimization constraints These are explicit constraints, user defines them. Optimization constraints apply to the design on represent the designs goals. They must be realistic. Environmental Constraints Defining the environment in which the design is expected to operate.

Design Rule Constraints and Optimization Constraints

Design Constraints

Design Rule Constraints


fanout_load attribute for input pins. max_fanout attribute for output pins. max_transition attribute for input or output pins. max_capacitance attribute for output or inout pins The fanout_load and max_fanout DRC attributes are related to each other,in such that the max_fanout value at the output of the driver pin cannot exceed the sum of all fanout_load values at each input pin of the driven cells Consider the cell (BUFFD0) shown in the previous example. This cell contains a max_fanout value of 4.0 associated to the output pin Z, while the fanout_load value at its input is 2.0. This cell therefore, cannot drive more than 2 of its own kind (BUFFD0) cells, since max_fanout (4) = fanout_load (2) of cell + fanout_load (2) of cell NOTE : If the DRC violations occur, then DC replaces the driving cell with another that has a higher max_fanout value.

Optimization Constraints
Optimization constraints represent speed, area, and porosity design goals Speed (timing) constraints have higher priority than area and porosity.

The optimization constraints comprise


Timing constraints (performance and speed)
Input and output delays (synchronous paths) Minimum and maximum delay (asynchronous paths)

Maximum area (number of gates) Minimum porosity (routability)

Timing Constraints

Basic Design Environment

Wire Load Models

1. For a fanout value of 4, the last fanout_length defines the wire length as 4.4, resulting in a calculated lumped net capacitance of 2.0 * 4.4 = 8.8. 2. The total net resistance is calculated by multiplication of the estimated wire length by the resistance factor, yielding a value of 4.4 * 100.0 = 440.0 3. The net area is calculated by multiplication of the estimated wire length by the area factor, yielding a value of 4.4 * .5 = 2.2

Design Rule Constraints


set_max_transition set_max_fanout set_max_capacitance set_fanout_load

Design Optimization Constraints


create_clock set_clock_latency set_propagated_clock set_clock_uncertainty set_clock_transition set_input_delay set_output_delay set_max_area

Define Design Environment


set_operating_conditions set_wire_load_model set_drive set_driving_cell set_load set_fanout_load set_min_library

Timing Paths and how to constrain them


4 types of Timing Paths 1. Primary Input to Register 2. Register to Register 3. Register to Primary Output 4. Primary Input to Primary output

A timing path is a path through logic along which signals can propagate. Paths normally start at primary inputs or clock pins of registers and end at primary outputs or data pins of registers

Primary input to register (in1 to FF1)


These paths are usually constrained by specification of the clock for the register and setting of an input delay relative to a clock on the input port.

Register to register (FF1 to FF2)


These paths are constrained by specification of the clock for the registers.

Register to primary output (FF2 to out1)


These paths are usually constrained by specification of the clock for the register and setting of an output delay relative to a clock on the output port.

Primary input to primary output (in2 to out2)


These paths are constrained by setting an input delay relative to a clock on the input port and an output delay relative to a clock on the output port.

Setup Time and Hold Time


Setup Time Setup time is a time specified in the technology library for sequential cells. Setup is the requirement that data be stable for a given time before the active clock edge. Setup time on a cell creates a maximum delay requirement for paths leading to the data pin of the cell. A setup violation occurs when a timing path is longer than its targeted maximum delay. Slack = Data Required Time Data Arrival Time Hold Time Hold time is a time specified in the technology library for sequential cells. Hold is the requirement that the signal on the data pin must remain stable for a given time after the active clock edge. Hold time on a cell creates a minimum delay requirement for paths leading to the data pin of that cell. A hold violation occurs when a timing path is shorter than its targeted minimum delay. Slack = Data Arrival Time Data Required Time

Skew Skew is the difference in arrival of clock at two consecutive pins of a sequential element. Clock skew is the difference in the arrival of clock signal at the clock pin of different flops.

Two types of skews are defined: Local skew Local skew is the difference in the arrival of clock signal at the clock pin of related flops. Global skew Global skew is the difference in the arrival of clock signal at the clock pin of non related flops. This also defined as the difference between shortest clock path delay and longest clock path delay reaching two sequential elements.

Timing diagram depicting skew, latency, jitter

Positive Skew
If capture clock comes late than launch clock then it is called +ve skew. +ve skew can lead to hold violation. +ve skew improves setup time.

Negative Skew
If capture clock comes early than launch clock it is called ve skew. -ve skew can lead to setup violation. -ve skew improves hold time.

Uncertainty
Clock uncertainty is the time difference between the arrivals of clock signals at registers in one clock domain or between domains.

Clock latency
Latency is the delay of the clock source and clock network delay. Clock source delay is the time taken to propagate from ideal waveform origin point to clock definition point. Clock network latency is the delay from clock definition point to register clock pin.

Jitter
Jitter is the short-term variations of a signal with respect to its ideal position in time. Jitter is the variation of the clock period from edge to edge. It can vary +/- jitter value.

Timing Exceptions
Multicycle Paths
The multicycle path condition is appropriate when data is not expected within a single cycle.
The -setup option of the set_multicycle_path command moves the edge used for setup checking to before or after the default edge. The -hold option of the set_multicycle_path Command launches the hold data at the edge before or after the default edge,but Design Compiler still checks the hold data at the edge used for checking setup.

False Paths

The circuit has these timing paths: 1. DATA to U1/D 2. RD to DATA 3. U1/G to CONFIG 4. U1/G to DATA 5. U1/G to U1/D The first four paths are valid paths. The fifth path (U1/G to U1/D) is a functional false path (because normal operation never requires simultaneous writing and reading of the configuration register) In this design, you can disable the false path by using this command: set_false_path -from U1/G -to U1/D

Timing Analysis
Timing Analysis is of two types. 1. Dynamic Timing Analysis (DTA) 2. Static Timing Analysis (STA)
Dynamic Timing Analysis
Dynamic timing analysis verifies functionality of the design by applying input vectors and checking for correct output vectors. Quality of the Dynamic Timing Analysis increases with the increase of input test vectors. Increased test vectors increase simulation time. Dynamic timing analysis can be used for synchronous as well as asynchronous designs. DTA is also carried out on post layout netlist to verify that functionality of the design has not changed. DTA performs full timing simulation. The problem associated with DTA is the computational complexity involved in finding the input patterns (vectors) that produce maximum delay at the output and hence it is slow.

Static Timing Analysis


Static timing analysis is a method for determining if a circuit meets timing (desired frequency) without having to simulate. In STA static delays such as gate delay and net delays are considered in each path and these delays are compared against their required maximum and minimum values. Circuit to be analyzed is broken into different timing paths constituting of gates, flip flops and their interconnections. Each timing path has to process the data within a clock period which is determined by the maximum frequency of operation

Advantages of STA
All timing paths are considered for the timing analysis. This is not the case in simulation. Analysis times are relatively short when compared with event and circuit simulation. Timing can be analyzed for worst case, best case simultaneously. This type of analysis is not possible in dynamic timing analysis. STA works with timing models. STA has more pessimism and thus gives maximum delay of the design.

Disadvantages of STA
All paths in the design may not run always in worst case delay. Hence the analysis is pessimistic. Clock related all information has to be fed to the design in the form of constraints. Inconsistency or incorrectness or under constraining of these constraints may lead to disastrous timing analysis. STA does not check for logical correctness of the design. STA is not suitable for asynchronous circuits.

Physical Design Flow

Floor Planning

Floor plan determines the size of the design cell (or die), creates the boundary and core area, and creates wire tracks for placement of standard cells. It is also a process of positioning blocks or macros on the die. Aspect Ratio= Horizontal Routing Resources / Vertical Routing Resources Core Utilization= Standard Cell Area / (Row Area + Channel Area)

Power Planning
There are two types of power planning and management. Core cell power management
VDD and VSS power rings are formed around the core and macro. In addition to this straps and trunks are created for macros as per the power requirement.

I/O cell power management.


Power rings are formed for I/O cells and trunks are constructed between core power ring and power pads.

The power information can be obtained from the front end design. The synthesis tool reports static power information. Dynamic power can be calculated using Value Change Dump (VCD) or Switching Activity Interchange Format (SAIF) file in conjunction with RTL description and test bench.

Clock Tree Synthesis

The goal of CTS is to minimize skew and insertion delay

Global skew achieves zero skew between two synchronous pins without considering logic relationship. Local skew achieves zero skew between two synchronous pins while considering logic relationship. If clock is skewed intentionally to improve setup slack then it is known as useful skew. Clock Tree Optimization is achieved by buffer sizing, gate sizing, buffer relocation, level adjustment setup slack is improved in pre-placement, and post placement optimization before CTS stage. In post placement optimization after CTS hold slack is improved. As a result of CTS lot of buffers are added. Generally for 100k gates around 650 buffers are added.

Routing
Routing is the process of creating physical connections based on logical connectivity. Signal pins are connected by routing metal interconnects. Routed metal paths must meet timing, clock skew, max trans/cap requirements and also physical DRC requirements. There are four steps of routing operations: 1. Global routing 2. Track assignment 3. Detail routing 4. Search and repair Global Route assigns nets to specific metal layers and global routing cells.Global route also avoids pre-routed P/G, placement blockages and routing blockages. Track Assignment (TA) assigns each net to a specific track and actual metal traces are laid down by it. It tries to make long, straight traces to avoid the number of vias. DRC is not followed in TA stage. TA operates on the entire design at once. Detail Routing tries to fix all DRC violations after track assignment using a fixed size small area known as SBox. Detail route traverses the whole design box by box until entire routing pass is complete. Search and Repair fixes remaining DRC violations through multiple iterative loops using progressively larger SBox sizes.

Commands For Reference

References
Design Compiler User Guide Advanced ASIC Chip Synthesis Himanshu Bhatnagar ASIC-System On Chip (SoC)-VLSI Design http://asic-soc.blogspot.com/

Questions