San Jose State University

Department of Computer Engineering

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CMPE 140Fall 2013

Final Project Enhanced and Pipelined MIPS Processor

Submitted by: Thanh Huynh 007610265 Christopher Harris 006088043 Date Performed: 12-8-2013 Checked by: Thanh Huynh Christopher Harris

CMPE 140 Final Project

Thanh Huynh, Christopher Harris Computer Engineering Department, College of Engineering San Jose State University, San Jose, CA 95192 E-mail: hu.thanh89@yahoo.com Charris90@gmail.com Abstract The objective of this project is to utilized the skills obtained in previous lab assignment to create and enhanced and pipelined MIPS processor.
Introduction With the knowledge and skills we obtained in classroom and previous lab assignments, and based on the initial design of the single-cycle MIPS processor, we are now ready to extend the initial design to a more capable version of the MIPS processor. Specifically, we will create and enhanced single-cycle MIPS processors functionality and then pipeline that single-cycle design. Design Description

Task 1
Create an enhanced single-cycle MIPS processors functionality by extending its instruction support from the initial sub set (ADD, SUB, AND, OR, SLT, LW, SW, BEQ, J, ADDI) to cover the following additional instructions: MULTU, MFHI, MFLO, JR, and JAL.

Figure Initial Single Cycle Processor

Table1 - Control Unit for Main Decoder (Single Cycle Design)

Table1 Control Unit for R Type Functions

Figure Enhanced Single Cycle Processor

Task 2
Pipeline the enhanced single-cycle MIPS processor based on the reference design shown below.

Figure Initial Pipelined Design

Figure Revised Pipeline Design 3

Figure Revised Pipeline Design (larger) 4

For each task of our design, it will be tested via both Verilog simulation and FPGA validation. Two sample test programs (from previous lab assignments) are attached below. Test Program 1: C++ Pseudo Code.
a = 0x51; b = 0x13; Save a to memory address 0x20; Save b to memory address 0x24; x = a - b; a = a + b; // a = 0x64 if(a < 0x25){ Read the word at address 0x20 into $a0; //so a=0x51 a = a + 0x89; } else{ Read the word at address 0x20 into $a0; //so a=0x51 a = a - 0x10; } Store the value of a to memory address 0x30;

Test Program 1: Machine Code:

#$a0 = a $a1 = b $s0 = x # Variables initialization li $a0, 0x51 #a = 0x51 li $a1, 0x13 #b = 0x13 sw $a0, 0x20($0) #save a to memory address 0x20 sw $a1, 0x24($0) #save b to memory address 0x24 # Arithmetic computations sub $s0, $a0, $a1 #x=a-b add $a0, $a0, $a1 # a = a + b; #IF structure addi $t1, $0, 0x25 # temp1 = 0 + 0x25 slt $t2, $a0, $t1 # set temp2 = 1 if a < 2500 lw $a0, 0x20($0) beq $t2, $0, else # if temp2 = 0, go to else addi $a0, $a0, 137 # a = a + 0x89 j endif #else structure else: addi $a0, $a0, -16 # a = a + 0x9 #endif structure endif: 5

sw $a0, 0x30($0)

Figure Generated Machine Code from Test Program 1.

Figure Register / Memory Content from Test Program 1 after execution.

Test Program 2: Assembly Code for extended design .data .globl main .text

main: # addi $sp, $0, 48 not for SPIM addi $a0, $0, 12 # set arg jal factorial # compute the factorial add $s0, $v0, $0 # move result into $s0 j end factorial: addi $sp, $sp, -8 # make room on stack sw $a0, 4($sp) # store $a0 sw $ra, 0($sp) # store $ra addi $t0, $0, 2 # $t0 = 2 slt $t0, $a0, $t0 # a <= 1 ? beq $t0, $0, else # no - goto else addi $v0, $0, 1 # yes - return 1 addi $sp, $sp, 8 # restore $sp jr $ra # return else: addi $a0, $a0, -1 # n = n - 1 jal factorial # recursive call lw $ra, 0($sp) # restore $ra lw $a0, 4($sp) # restore $a0 addi $sp, $sp, 8 # restore $sp multu $a0, $v0 # n * factorial(n-1) mflo $v0 # mv result into $v0 jr $ra end:

Figure Generated Machine Code from test program 2.

Figure Register / Memory content from test program 2 after execution. Verification And Test

Figure ISIM (single cycle using test program 1) The figure above shows simulation of our single cycle. This simulation yields correct results. When executing on MIPS, the last instruction (ac40030) stores value 41 of register a into memory address 0x30. As shown from ISIM figure above, wave length din[31:0] and addr[31:0] of DMEM shows value 30 and 41.

Table : settings for FPGA board.

Conclusion and Discussion

References 1. Handouts from SJSU Canvas.