III B.

Tech II Semester
STUDENT HANDBOOK for

VLSI Design
Faculty: sNagas!et"a

UNIT I Sylla#us: INT$ODU%TION : Introduction to IC Technology MOS, PMOS, NMOS, CMOS & BiCMOS technologies- Oxidation, Lithogra hy, !i""usion, Ion i# lantation, Metallisation, $nca sulation, Pro%e testing, Integrated &esistors and Ca acitors,CMOS Nanotechnoology. O#&ecti'es: To ro'ide an %asic (no)ledge o" *LSI Technology+ To discuss the 'arious IC Technologies+ To discuss the 'arious ste s in'ol'ed in "a%rication o" chi + Lecture (lan: S)No To(ic , Introduction to IC Technology MOS, PMOS, NMOS, CMOS & BiCMOS technologies . PMOS, NMOS /a%rication 0 1 2 3 4 5 CMOS /a%rication BiCMOS /a%rication Oxidation, Lithogra hy !i""usion, Ion i# lantation Metallisation, $nca sulation, Pro%e testing, Integrated &esistors and Ca acitors, CMOS Nanotechnology Date No) of lectures -. -. -, -, -. -. -, -.

Assign*ents: ,+ $x lain the rocessing ste s in "a%rication o" PMOS technology )ith neat s(etches+

.+ 6hat are the additional t)o layers in BICMOS technology co# ared to other+ 0+ $x lain a%out oxidation, !i""usion and Ion I# lantation Processes o" I C /a%rication+ 1+ 6hat is a tu% tie7 $x lain this )ith an exa# le+ 2+ !ra) the circuits "or n-MOS, -MOS and C-MOS In'erter and ex lain a%out their o eration and co# are the#+ 3+ $x lain a%out the rocess ste s 8a9 Crystal :ro)th 8%9 Oxidation 8c9 !i""usion 8d9 Lithogra hy 8e9 Metalli;ation in'ol'ed in the "a%rication o" ICs+ UNIT II Sylla#us: BASI% ELE%T$I%AL +$O+E$TIES : Basic $lectrical Pro erties o" MOS and BiCMOS Circuits< Ids-*ds relationshi s, MOS transistor threshold *oltage, g#, gds, "igure o" #erit 7o= Pass transistor, NMOS In'erter, *arious ull u s, CMOS In'erter analysis and design, Bi-CMOS In'erters+ O#&ecti'es: To understand $lectrical Pro erties o" MOS and BiCMOS Circuits+ To discuss NMOS, CMOS in'erter and Bi-CMOS in'erter+ To discuss the 'arious ull u s o" an NMOS in'erter+ Lecture (lan: S)No , . 0 To(ic Ids-*ds relationshi s MOS transistor threshold *oltage g#, gds, "igure o" #erit 7o= Pass transistor Date No) of lectures -. -, -,

1 2 3

NMOS In'erter, *arious ull u s CMOS In'erter analysis and design Bi-CMOS In'erters+

-, -, -,

Assign*ents: ,+ !eri'e the relation %et)een I!S & *!S o" MOS/$T+ .+ !ra) the circuit "or NMOS in'erter and ex lain its o eration+ 0+ 8a9 !ra) the CMOS circuit to reali;e the Boolean ex ression y>?-B, and ex lain the sa#e+ 8%9 6hat is #eant %y "an in & "anout o" gate+ 1+ !eri'e the relation %et)een I!S & *!S o" MOS/$T+ 2+ !ra) the circuit "or NMOS in'erter and ex lain its o eration+ 3+ $x lain the ter#s /igure o" Merit o" MOS/$T and out ut conductance, using necessary e@uations+

UNIT III Sylla#us: VLSI %I$%UIT DESI,N +$O%ESSES : *LSI !esign /lo), MOS Layers, Stic( !iagra#s, !esign &ules and Layout, . 7# CMOS !esign rules "or )ires, Contacts and Transistors Layout !iagra#s "or NMOS and CMOS In'erters and :ates, Scaling o" MOS circuits, Li#itations o" Scaling+ O#&ecti'es: To understand the *LSI !esign /lo)+ To understand the !esign &ules and Layout+ To discuss Stic( !iagra#s and Transistors Layout !iagra#s "or NMOS and CMOS In'erters and :ates+

To discuss Scaling o" MOS circuits+ Lecture (lan: S)No To(ic , *LSI !esign /lo), MOS Layers . 0 1 2 3 Stic( !iagra#s !esign &ules and Layout . 7# CMOS !esign rules "or )ires Contacts and Transistors Layout !iagra#s "or NMOS and CMOS In'erters and :ates Scaling o" MOS circuits, Li#itations o" Scaling+ Date No) of lectures -, -0 -. -, -, -,

Assign*ents: ,+ !ra) the stic( diagra# and layout "or the "ollo)ing "unction .+ 6hat is the di""erence %et)een ABA and ABA scaling "actors7 :i'e so#e exa# les+ 0+ /or 'arious rocesses in MOS IC "a%rication, ex lain a%out !esign &ules+ 1+ !ra) the CMOS circuit to reali;e the Boolean ex ression y>?-B, and ex lain the sa#e+ 2+ $x lain a%out NO& CMOS Logic+ 3+ !ra) Stic( diagra# "or CMOS In'erter, gi'ing ex lanation+

UNIT IV Sylla#us: ,ATE LEVEL DESI,N : Logic :ates and Other co# lex gates, S)itch logic, ?lternate gate circuits, Ti#e !elays, !ri'ing large Ca aciti'e Loads, 6iring

Ca acitances, /an-in and "an-out, Choice o" layers+ O#&ecti'es: To discuss the S)itch logic+ To discuss the circuits used "or Ti#e !elays, !ri'ing large Ca aciti'e Loads+ To discuss a%out the Ti#e !elays and 6iring Ca acitances+ Lecture (lan: S)No To(ic , Logic :ates and Other co# lex gates . 0 1 2 S)itch logic, ?lternate gate circuits Ti#e !elays !ri'ing large Ca aciti'e Loads, 6iring Ca acitances /an-in and "an-out, Choice o" layers+ Date No) of lectures -. -, -, -, -,

Assign*ents: ,+ $x lain a%out sheet resistance and sheet ca acitance+ .+ 6hat are the issues in'ol'ed in dri'ing large ca acitor loads in *LSI circuit 0+ designs7 $x lain+ 1+ 6hat are the issues in'ol'ed in dri'ing large ca acitor loads in *LSI circuit 2+ designs7 $x lain 3+ 6hat are the design issues in'ol'ed in long interconnect )ires7 $x lain+

UNIT V Sylla#us:

DATA +ATH SUBS-STE S : Su%syste# !esign, Shi"ters, ?dders, ?LCs, Multi liers, Parity generators, Co# arators, DeroEOne !etectors, Counters+ O#&ecti'es: To understand the conce t o" Su%syste# !esign+ To discuss the design #ethod "or Shi"ters, ?dders, ?LCs, Multi liers, Parity generators, Co# arators, DeroEOne !etectors, Counters+ Lecture (lan: S)No To(ic , Su%syste# !esign, Shi"ters, ?dders+ . 0 1 ?LCs, Multi liers+ Parity generators, Co# arators+ DeroEOne !etectors, Counters+ Date No) of lectures -. -. -, -,

Assign*ents: ,+ !ra) the logic diagra# o" ;eroEone dectector and ex lain its o eration )ith the hel o" stic( diagra#+ .+ !ra) the sche#atic and ex lain the rinci le and o eration o" ?rray Multi lier+ 0+ !ra) the sche#atic and ex lain the )or(ing o" Tree Multi lier+

UNIT VI Sylla#us: A$$A- SUBS-STE S: S&?M,!&?M,&OM,Serial ?cess Me#ories,Content ?ddressa%le Me#ory+ O#&ecti'es: To understand the conce t o" designing S&?M and !&?Ms+

To understand the conce t o" designing Serial ?cess Me#ories and Content ?ddressa%le Me#ory+

Lecture (lan: S)No , S&?M,!&?M+ . 0 To(ic Date No) of lectures -. -, -,

&OM+,Serial ?cess Me#ories+ Content ?ddressa%le Me#ory+

Assign*ents: ,+ $x lain the rinci le o" a !&?M cell+ .+ :i'e the sche#atic o" a !&?M and ex lain ho) &$?! and 6&IT$ o erations are carried out+ 0+ $x lain the rinci les o" S&?M and !&?M+ 1+ 6hat are the ad'antages o" S&?M and !&?Ms co# are the# in all res ects+ UNIT VII Sylla#us: SE I%ONDU%TO$ INTE,$ATED %I$%UIT DESI,N : PL?s, /P:?s, CPL!s, Standard Cells, Progra##a%le ?rray Logic, !esign ? roach,Para#eters in"luencing Lo) Po)er !esign+ O#&ecti'es: To understand the %asic conce t o" PL?s, /P:?s, CPL!s+ To discuss a%out the Standard Cells, Progra##a%le ?rray Logic+ To discuss a%out 'arious !esign ? roach,Para#eters in"luencing Lo) Po)er !esign+

Lecture (lan: S)No To(ic , PL?s, /P:?s, CPL!s+ . 0 Standard Cells, Progra##a%le ?rray Logic+ !esign ? roach,Para#eters in"luencing Lo) Po)er !esign+ Date No) of lectures -. -. -,

Assign*ents: ,+ Co# are PL?s, P?Ls, CPL!s, /P:?s, and standard cells in all res ects+ .+ $x lain a%out the rinci le and o eration o" /P:?s+ 6hat are its a lications7 0+ !ra) the sche#atic "or PL? and ex lain the rinci le+ 6hat are the ad'antages o" PL?s7 1+ $x lain the structure and rinci le o" PL?+ 2+ !ra) the sche#atic and ex lain ho) /ull ?dder can %e i# le#ented usingPL?As+ 3+ $x lain a%out con"igura%le /P:? %ased IEO %loc(s+

UNIT VIII Sylla#us: % OS TESTIN, : CMOS Testing, Need "or testing, Test Princi les, !esign Strategies "or test, Chi le'el Test Techni@ues, Syste#-le'el Test Techni@ues, Layout !esign "or i# ro'ed Testa%ility+ O#&ecti'es: To understand Princi les o" testing an CMOS de'ice+ To discuss Chi le'el Test Techni@ues and Syste#-le'el Test Techni@ues+

To discuss Layout !esign "or i# ro'ed Testa%ility+ Lecture (lan: S)No To(ic , CMOS Testing, Need "or testing, Test Princi les+ . !esign Strategies "or test, Chi le'el Test Techni@ues+ 0 Syste#-le'el Test Techni@ues, Layout !esign "or i# ro'ed Testa%ility+ Date No) of lectures -, -, -,

Assign*ents: ,+ .+ 0+ 1+ 2+ 3+ 6hat are the di""erent categories o" !/T techni@ues7 $x lain+ 6hat is #eant %y signature analysis in Testing7 $x lain )ith an exa# le+ 6ith the hel o" a sche#atic ex lain a%out Me#ory-sel" Test+ 6hat are the issues to %e considered )hile i# le#enting BIST7 $x lain+ Fo) layout design can %e done "or i# ro'ing testa%ility7 $x lain+ $x lain a%out di""erent "ault #odels in *LSI testing )ith exa# les+G

4+ 6rite notes on any T6O 8a9 !:T 8%9 BIST 8c9 Boundary scan Testing