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MOS Digital Circuits Chapter 16

In the late 70s as the era of LSI and VLSI began, NMOS became the fabrication technology choice. Later the design flexibility and other advantages of the CMOS were realized, CMOS technology then replaced NMOS at all level of integration. The small transistor size and low power dissipation of CMOS circuits, demonstration principal advantages of CMOS over NMOS circuits.

NMOS Inverter
For any IC technology used in digital circuit design, the basic circuit element is the logic inverter. Once the operation and characterization of an inverter circuits are thoroughly understood, the results can be extended to the design of the logic gates and other more complex circuits.

NMOS Inverter
If VI <VNT, the transistor is in cutoff and iD =0, there is no voltage drop across RD, and the output voltage is Vo=VDD=VDS If VI >VNT, the transistor is on and initially is biased in saturation region, since
+

RD =VDD=VDS

VDS >VGS-VTN. As the input voltage increasesVGS=V (VGS) , the drain to source + voltage (VDS) decreases and the transistor inter into the non saturation region.

NMOS Inverter Transfer Characteristics with load resister (Saturation Region)


As the input is increased slightly above the VTN, the transistor turns on and is in the saturation region. The output voltage is then vo = VDD iDRD (16.6 ) where the drain current is given by iD = Kn(VGS - VTN)2 = Kn(Vi - VTN)2 ( 16.7) By substituting the value of ID from Eq. 16.7 we get , VO = VDD - KnRD(VI - VTN)2 (16.8)

NMOS Inverter Transfer Characteristics with load resister (transition Region)


As the input voltage is further increases and voltage drop across the RD become sufficient to reduce the drain to source voltage such that
+ RD =VDD=VDS

NMOS Inverter Transfer Characteristics with load resister (Nonsaturation Region)


As the input voltage becomes greater than VIt, the Q-point continues to move up the load line, and the transistor becomes biased in the nonsaturation region. The drain current is then iD = Kn[2(VGS - VTN)VDS VDS2] = Kn[2(vI - VTN)VO Vo2] (16.11) The output voltage is then determined by vo = VDD iDRD Substitute the value of ID from above equation we get the output voltage relation when the transistor is biased in nonsaturation region.
+ RD =VDD=VDS

RD =VDD=VDS

VDSVGS-VTN.
the Q-point of the transistor moves up the load line. At the transition point, we have

VGS=V
+

VGS=V
+

VGS=V
+

vot = VIt - VTN

16.9

where Vo, and VI, are the drain-to-source and gate-to-source voltages, respectively, at the transition point. By substituting Equation (16.9) into (16.8), the input voltage at the transition point can be determined as,

which relates the output and input voltages as long as the transistor is biased in the saturation region.

KnRD(VIt - VTN)2+ (VIt - VTN) - VDD = 0

VO = VDD KnRD [2(vl - VTN)vo vo2]

RD =VDD=VDS

VGS=V
+

Summary of NMOS inverter C-V relationship with the resister load


Saturation region
+

NMOS Inverter with Enhancement Load


This basic inverter consist of two enhancement-only NMOS transistors and is much more practical than the resister loaded inverter, which is thousand of times larger than a MOSFET.

VO = VDD - KnRD(VI Transition region

VTN)2
VGS=V
+

RD =VDD=VDS

iD = Kn(VGS - VTN)2 = Kn(Vi - VTN)2

Nonsaturation region
iD = Kn[2(vI - VTN)VO Vo2]

vot = VIt - VTN


KnRD(VIt - VTN)2+ (VIt - VTN) - VDD
It should be be noted that the minimum output voltage, or the logic 0 level, for a high input decreases with increasing load resistance, and the sharpness of the transition region between a low input and a high input increases with increasing load resistance.

VO = VDD KnRD [2(vl - VTN)vo - vo2]

n-Channel MOSFET connected as saturated load device


An n-channel enhancement-mode MOSFET with the gate connected to the drain can be used as load device in an NMOS inverter. Since the gate and drain of the transistor are connected, we have VGS=VDS When VGS=VDS>VTN, a non zero drain current is induced in the transistor and thus the transistor operates in saturation only. And following condition is satisfied. VDS>(VGS-VTN) VDS (sat)= (VDS-VTN) because VGS=VDS or VDS (sat)= (VGS-VTN) In the saturation region the drain current is iD=Kn(VGS-VTN)2 = Kn(VDS-VTN)2

NMOS Inverter with Enhancement Load/Saturated


In the saturation region the load drain current is iDL=KL(VGSL-VTNL)2 = KL(VDSL-VTNL)2 For VGSD<VTN ( driver transistor ) transistor is in cutoff mode and does not conduct drain current 0= iDL=KL(VGSL-VTNL)2 = KL(VDSLVTNL)2 VGSL=VTNL or VDSL=VTNL As a result the output high voltage VO is degraded by the threshold voltage or VO,, max= VOH =VDD-VTNL

NMOS inverter with Enhancement Load/Saturated (Cont.)


As the VI=>VTND A non zero drain current is induced in the transistor and thus the drive transistor operates in saturation only. As shown in the figure the following condition is satisfied iDD=iDL or KD(VGSD-VTND)2 = KL(VGSL-VTNL)2 Substituting VGSD=VI and VGSL=VDD-VO yields KD(VI - VTND)2 = KL(VDD - VO - VTNL)2 Solving for VO gives VO= VDD-VTNL- KD/KL(VI-VTND)

The iD versus vDS characteristics are shown in Figure 16.7(b), which indicates that this device acts as a nonlinear resistor.

NMOS inverter with Enhancement Load/Saturated (driver at the transition point)


As the input voltage (VGS) further increases, the drive Q-point moves up and switch into the transition region., we have VDSD(sat)= VGSD-VTND In terms of input/output transition voltages or VOt=VIt-VTND Substituting above Equation into following equation VO= VDD-VTNL- KD/KL(VI-VTND) we find the input voltage at the transition point, which is VIt= [VDDVTNL+VTND(1+ KD/KL)]/(1+ KD/KL)

NMOS Inverter with Enhancement Load/Saturated (driver at the non saturation region))
As the input voltage becomes greater than VIt the driver transistor Q- point continues to move up the load curve and the driver becomes biased in the nonsaturation region. Since the driver and load drain currents are still equal, or iDD = iDL, we now have KD[2(VGSD - VTND)VDSD - VDSD2] = KL(VDSL -VTNL)2 Substituting VGSD=VI and VDSD=VO and VDSL= VDD-VO we get KD[2(vl -VTND) Vo- VO2 ] = KL(VDD - VO - VTNL)2

Limitation of NMOS inverter Example 16.3

The ratio KDIKL is the aspect ratio and is related to the width-to-length parameters of the driver and load transistors.
The slope of the VTC curves in the saturation region is known as inverter gain and is given by dVo/dVI= - KD/KL If the inverter gain is greater then unity, the inverter logic gate is belonged to restoring logic family.

Limitation of Enhancement Load inverter

NMOS Inverter with Depletion Load


This is an alternate form of the NMOS inverter that uses an enhancementdepletion MOSFET load device with gate and source terminal connected. This inverter has the advantage of VO= VDD, as well as more abrupt VTC transition region even though the W/L ratio for the output MOSFET is small.

VO,max= VOH =VDD-VTNL the output high voltage VO is degraded by the threshold voltage.

The term depletion mode means that a channel exists even with zero gate voltage.

N-Channel Depletion-Mode MOSFET


In n- channel depletion mode MOSFET, an nchannel region or inversion layer exists under the gate oxide layer even at zero gate voltage and hence term depletion mode. A negative voltage must be applied to the gate to turn the device off. The threshold voltage is always negative for this kind of device.

NMOS Inverter with Depletion Load (saturation condition)


With the gate and source are connected, VGSL=0. Since the threshold voltage of load transistor is negative, we have VGSL=0>VTNL= -(VTNL) This implies that load MOSFET is always active. For an active device we can write VDSLVGSL VTNL= -VTNL=VTNL becauseVGSL=0.

NMOS Inverter with Depletion Load (cont.)


Case I: when VI<VTND (drive is cutoff): No drain current conduct in either transistor. That means the load transistor must be in the linear region of the operation and the output current can be expressed as fellows iDL(linear)=KL[2(VGSL - VTNL)VDSL VDSL2] Since VGSL=0, and iDL=0 0=-KL[2VTNLVDSL + VDSL2] Which gives VDSL=0 thus VO= VDD This is the advantage of the depletion load inverter over the enhancement load inverter.

NMOS Inverter with Depletion Load (Cont.)


Case II: When VI>VTND (driver turns on) and is biased in the saturation region; however, the load is biased in the nonsaturation region. Under the condition we can write iDD=IDDL

Two transition points for NMOS depletion load inverter


In the Figure the point B and C are corresponding the two transition points: one for the load and one for the driver. The transition point for the load is given by, VDSL=VDD-VOt Also VDSL=VGSL-VTNL By equating the relations we get VDD-VOt=VGSL-VTNL Since VGSL=0 V0t=VDD+VTNL As we know VTNL is negative. This implies that Vot<VDD The transition point for the driver is given by VDSD=VGSD-VTND Or in terms of input and output voltage we can write VOt=VIt-VTND

When both devices (driver and load) are in saturation region


When both devices are biased in saturation region the Q point lies between point B and C on the load curve, and

KD(VGSD-VTND) Or

= KL(VGSL-VTNL)2

KD/KL(VI-VTND)=-VTNL Implies that input voltage is constant as the Q-point passes this region. If we further increased the input voltage, the drive is biased in the nosaturation region while load is in saturation region. The Q-point moves between C and D on the load curve. For the input/output characteristics we equate two drain current equation KD[2(VGSD - VTND)VDSD - VDSD2] = KL(VDSL VTNL)2 Which becomes KD/KL[2(VI-VTND)VO-Vo2]=-(-VTNL)2 Implies that input and output voltages are not linear in this region.

KD(VGSD-VTND)2 =KL[2(VGSL - VTNL)VDSL - VDSL2]


Substituting VGSD=VI, VGSL=0, and VDSL=VDD-VO Yields KD(VI-VTND)2 =KL[2(-VTNL)(VDD -

VO)-VDD VO)2]

Which relates the input and output voltage as long as the driver is biased in saturation region and

VT Characteristics of NMOS Inverter with Depletion Load

The Figure demonstrate in present configuration more abrupt VTC transition region can be achieved even though the W/L ratio for the output MOSFET is small.

Transient Analysis of NMOS inverters

Transient Analysis of NMOS inverters (cont.)


The fall time relatively short, because the load capacitor discharges through the large driver transistor. The raise time is longer because the load capacitor is charged by the current through the smaller load transistor.
(W/L)L=1 (W/L)D=4 F-0.5pF

The source of capacitance CT2 and CT3 are the transistor input capacitances and parasitic capacitances due to interconnect lines between the inverter stages.

The constant current over a wide range of VDS provided by the depletion load implies that this type of inverter switch a capacitive load more rapidly than the other two types inverter The rate at configurations.

enhancement load

depletion load

1160W

825W

200W

NMOS NOR gate

NMOS NOR gate: Special case when all inputs are at logic 1
When A=B=logic 1 Both driver transistors are switched into nonsaturation region and load transistor is biased in saturation region. We have iDL=iDA+iDB By substituting the values of current equation we can write as,

16.2: NMOS Logic Circuit


NMOS logic circuits are constructed by connecting driver transistor in parallel, series or series-parallel combinations to produce required output logic function

NMOS NOR gate can be constructed by connecting an additional driver transistor in parallel with a depletion load inverter. The output of a NOR gate is only high when both inputs are at logic 0(low)i.e. If A=B=logic 0, Then both driver transistors MDA and MDB are in cut off mode and V0=VDD (logic 1) For all other possible inputs V0= 0 (logic 0). For example, If A=high (logic1) and B=low (logic0) Then MDB is in cut off mode and remaining circuit behave as depletion load inverter. However, when both driver transistors are in active mode the value of the output voltage logic 0) is changed.

KL(VGSL-VTNL)2 = KDA[2(VGSA - VTNA)VDSA - VDSA2] + KDB[2(VGSB -VTNB)VDSB - VDSB2]


Suppose two driver transister are identical, which implies that, KDA=KDB=KD VTNA=VTNB=VTND As we know VGSL=0 Also from figure VGSA=VGSB=VDD VDSA=VDSB=V0 By substituting all these parameters we can write above equation as, (-VTNL)2 =

2(K /K )[2(V
D L

2 DD-VTND)V0-VO )

Conclusion: The above equation suggested that when the both the driver are in conducting mode, the effective aspect ratio of the NOR gate is double. This further suggested that output voltage becomes slightly smaller when both inputs are high. Because higher the aspect ratio lower the output.

Concept of effective width to length ratios


Parallel combination Series combination

For the NOR gate the effective width of the drivers transistors doubles. That means the effective aspect ratio is increased.

For the NAND gate the effective length of the driver transistors doubles. That means the effective aspect ratio is decreased.
.

CMOS: the most abundant devices on earth


At present, complementary MOS or CMOS has replaced NMOS at all level of integration, in both analog and digital applications. The basic reason of this replacement is that the power dissipation in CMOS logic circuits is much less than in NMOS circuits, which makes CMOS very attractive. Although the processing is more complicated for CMOS circuits than for NMOS circuits. However, the advantages of CMOS digital circuits over NMOS circuits justify their use.

CMOS properties
Full rail-to-rail swing high noise margins

Logic levels not dependent upon the relative device sizes transistors can be minimum size ratio less

Always a path to Vdd or GND in steady state low output impedance (output resistance in k range) large fan-out. Extremely high input resistance (gate of MOS transistor is near perfect insulator) nearly zero steady-state input current No direct path steady-state between power and ground no static power dissipation Propagation delay function of load capacitance and resistance of transistors

16.3.1:p-Channel MOSFET Revisited


In p-channel enhancement device. A negative gate-tosource voltage must be applied to create the inversion layer, or channel region, of holes that, connect the source and drain regions. The threshold voltage VTP for p-channel enhancement load device is always negative and positive for depletionmode PMOS.
Cross-section of p-channel enhancement mode MOSFET

Simplified cross section of a CMOS inverter


In the fabrication process, a separate p-well region is formed within the starting n-substrate. The n-channel MOSFET is fabricated in the p-well region and p-channel MOSFET is fabricated in the n-substrate.

The operation of the p-channel is same as the n-channel device , except that the hole is the charge carrier, rather than the electron, and the conventional current direction and voltage polarities are reversed.

CMOS Inverter: Steady State Response


VDD VDD

Voltage Transfer Curve


VOL = 0 VOH = VDD

CMOS Inverter Load Lines


PMOS Vin = 0V

2.5 2

X 10-4

NMOS Vin = 2.5V

Rp Vout = 1 Rn Vout = 0
IDn (A)

Vin = 0.5V 1.5 Vin = 1.0V 1

Vin = 2.0V

Vin = 1.5V Vin = 2.0V

Vin = 2V 0.5

Vin = 1.5V

Vin = 1V

Vin = 1.5V

Vin = 0.5V
Vin = 1.0V Vin = 0.5V

0 0.5 1 1.5 Vout (V) 2

Vin = 0

Vin = V DD

Vin = 2.5V 0

2.5 Vin = 0V

0.25um, W/Ln = 1.5, W/Lp = 4.5, VDD = 2.5V, VTn = 0.4V, VTp = -0.4V

DC analysis of the CMOS inverter

NMOS in sat PMOS in non sat NMOS off PMOS in non sat

NMOS in sat PMOS in sat

NMOS in non sat PMOS in sat

NMOS in nonsat PMOS off

The figure shows series combination of a CMOS inverter. To form the input, gate of the two MOSFET are connected. To form the output, the drains are connected together. VI Vo The transistor KN is also known as pull down 1 0 Device, it is pulling the output voltage down towards ground. The transistor KP is known as the pull up device because it is 0 1 pulling the output voltage up towards V . This property speed
up the operation considerably.
DD

CMOS inverter in either high or low state (ideal case)


Ideally, the power dissipation of the CMOS inverter is zero. However, real CMOS inverter exhibits a very small power dissipation in the nanowatt range rather than in the milliwatt rang of NMOS inverter.

It is to be noted that the static power dissipation during both extreme cases (logic 1 or 0) is almost zero because iDp=iDn=0.

Different biasing conditions for a CMOS inverter.


Case I: when NMOS is biased in saturation region and PMOS is biased in nonsaturation region. The above condition can be achieved when NMOS just start to conduct (VI=VTN). Under this condition we can write, iDN=iDP KN[VGSN-VTN]2=KP[2(VGSP+VTP)VSDP-VSDP2)] In terms of input output voltage we can write, KN[VI-VTN]2=KP[2(VDD-VI+VTP)VDD-VO)-(VDD-VO)2]

Transition points for PMOS and NMOS


As we know transition point for the PMOS can be define as, VSDP(sat)=VSGP+VTP VOPt=VIPt-VTP VOPt=VIPt+|VTP| Similarly, the transition point for NMOS can be written as VDSN(sat)=VGSN-VTN or VoNt=VINT-VTN
Or Or

Biasing conditions for the CMOS inverter (cont.)


Case II: When both transistors are biased in the saturation region. iDN=iDP KN[VGSN-VTN]2=KP(VGSP+VTP)2 In terms of input output voltage we can write, KN[VI-VTN]2=KP(VDD-VI+VTP)2 The input voltage can be determine by simplifying above equation as,
VDD + VTP + VI = VIt = 1+ KN VTN KP KN KP

Both are in Saturation region

The above eq. can also be used to determine input voltage at the transition points.

Symmetrical properties of the CMOS inverter

CMOS inverter design consideration


The CMOS inverter usually design to have, (i)VTN =|VTP| (ii) Kn(W/L)=Kp (W/L) But Kn> Kp (because n>p) How equation (ii) can be satisfied? This can achieved if width of the PMOS is made two or three times than that of the NMOS device. This is very important in order to provide a symmetrical VTC, results in wide noise margin.

CMOS inverter VTC


VCC

kp=kn

Increase W of PMOS kp increases VTC moves to right Increase W of NMOS kn increases VTC moves to left For VTH = Vcc/2 kn = kp Wn 2Wp

Vout
kp=0.2kn

kp=5kn

VCC

Vin

Effects of VIt adjustment


Result from changing kp/kn ratio:
Inverter threshold VIt Vcc/2 Rise and fall delays unequal Noise margins not equal

Reasons for changing inverter threshold


Want a faster delay for one type of transition (rise/fall) Remove noise from input signal: increase one noise margin at expense of the other

CMOS inverter currents


When the output of a CMOS inverter is either at a logic 1 or 0, the current in the circuit is zero. When the input voltage is in the range VTN<VI<VTP Both transistors are conducting and a current exists in the inverter.

When NMOS transistor is biased in the saturation region


When NMOS transistor is biased in the saturation region, the current in the inverter is controlled by VGSN (why?). Under this condition we can write, IDN=iDP=KN[VGSN-VTN]2 By taking the square root both sides, we can write, iDM=iDP=KN(VI-VTN) The above equation showed that as long as NMOS transistor is biased in the saturation region the square root of the CMOS inverter current is linear function of the input voltage.

When PMOS transistor is biased in the saturation region


When PMOS transistor is biased in the saturation region, the current in the inverter is controlled by VSGP (why?). Under this condition we can write, IDN=iDP=KP[VGSP+VTP]2 IDN=iDP=KP[VDD-VI+VTP]2 By taking the square root both sides, we can write, iDM=iDP=KP(VDD-VI+VTP) The above equation showed that as long as PMOS transistor is biased in the saturation region the square root of the CMOS inverter current is linear function of the input voltage. At the switching point, both transistors are biased in the saturation region. It is to be noted that the actual current characteristic does not have a sharp discontinuity.

Power Dissipation
Although there isn't power dissipation in the CMOS inverter when the output is either at logic 0 or 1. However, during switching of the CMOS inverter from low logic 0 to logic 1, current flows and power is dissipated. Usually CMOS inverter and logic circuit are used to drive other MOS devices by connecting a capacitor across the output of a CMOS inverter. This capacitor must be charged and discharged during the switching cycle.

IDt =

NMOS Transistor Capacitances: Triode Region


Cox = Gate-channel capacitance per unit area(F/m2). CGC = Total gate channel capacitance. CGS = Gate-source capacitance. CGD = Gate-drain capacitance. CGSO and CGDO = overlap capacitances (F/m).

NMOS Transistor Capacitances: Saturation Region


Drain no longer connected to channel

NMOS Transistor Capacitances: Cutoff Region


Conducting channel region completely gone. CGB = Gate-bulk capacitance CGBO = gate-bulk capacitance per unit width.

CMOS Inverter: Switch Model of Dynamic Behavior


VDD VDD

CMOS inverter power


Power has three components
Static power: when input isnt switching
Vout

CMOS inverter static power


Static power consumption:
Static current: in CMOS there is no static current as long as Vin < VTN or Vin > VDD+VTP Leakage current: determined by off transistor Influenced by transistor width, supply voltage, transistor V threshold voltages V
DD DD

Rp Vout CL Rn CL

Dynamic capacitive power: due to charging and discharging of load capacitance Dynamic short-circuit power: direct current from VDD to Gnd when both transistors are on

Ileak,p
VI<VTN Vcc VDD Vo(low)

Vin = 0 through Rp (discharge CL through Rn)

Vin = V DD

Gate response time is determined by the time to charge CL

Ileak,n

Dynamic Capacitive Power and energy stored in the PMOS device


Case I: When the input is at logic 0: Under this condition the PMOS is conducting and NMOS is in cutoff mode and the load capacitor must be charged through the PMOS device. Power dissipation in the PMOS transistor is given by,

Power Dissipation and Total Energy Stored in the CMOS Device


Case II: when the input is high and out put is low: During switching all the energy stored in the load capacitor is dissipated in the NMOS device because NMOS is conducting and PMOS is in cutoff mode. The energy dissipated in the NMOS inverter can be written as, 1
EN = 2 C L V DD
2

Dynamic capacitive power


2 Pdyn = C LVDD f

Formula for dynamic power: Observations


Does not (directly) depend on device sizes Does not depend on switching delay Applies to general CMOS gate in which:
Switched capacitances are lumped into CL Output swings from Gnd to VDD Input signal approximated as step function Gate switches with frequency f

PP=iLVSDp= iL(VDD-VO) iL=CLdvO/dt


The current and output voltages are related by, Similarly the energy dissipation in the PMOS device can be written as the output switches from low to high ,
E P = PP = C L (V DD O )
0 0

d O dt , E P = C LV DD dt

V DD

d
0

C L O d O
0

V DD

The total energy dissipated during one switching 1 1 2 2 2 ET = EP + EN = C LVDD + C LVDD = C LVDD cycle is, 2 2 The power dissipated in terms pf frquency can be written as E P = fET fC LVDD ET = P t P = T t

E P = C LV DD O 1 2 E P = C LV DD 2

V DD 0

CL

O
2

2 V DD

, E P = (C LV DD V DD 0 ) (C L
0

V DD 0) 2

Above equation showed the energy stored in the capacitor CL when the output is high.

This implied that the power dissipation in the CMOS inverter is directly proportional to switching frequency and VDD2

Dynamic short-circuit power


Short-circuit current flows from VDD to Gnd when both transistors are on saturation mode Plot on VTC curve:
VCC

Inverter power consumption


Total power consumption
Ptot = Pdyn + Psc + Pstat tr + t f 2 Ptot = C LVCC f + VCC I max 2 2 Ptot ~ C LVCC f f + VCC I leak

Power reduction
Reducing dynamic capacitive power:
Lower the voltage!
Quadratic effect on dynamic power

Imax Vout ID

Imax: depends on saturation current of devices

Reduce capacitance
Short interconnect lengths Drive small gate load (small gates, small fan-out)

Reduce frequency
Lower clock frequency Lower signal activity

Vin

VCC

2 Pdyn = C LVDD f

Power reduction
Reducing short-circuit current:
Fast rise/fall times on input signal Reduce input capacitance Insert small buffers to clean up slow input signals before sending to large gate

Concept of Noise Margins

Reducing leakage current:


Small transistors (leakage proportional to width) Lower voltage
VI

NML=VIL-VOL (noise margin for low input) NMH=VOH-VIH (noise margin for high input)

NML=VIL-VOLU (noise margin for low input) NMH=VOHU - VIH (noise margin for high input)

At point VIL the NMOS is biased in the saturation region and PMOS is biased in the nonsaturation region

Noise Margins equations


(1)

At point VIH the NMOS is biased in the nonsaturation region and PMOS is biased in the saturation region

(6) Taking derivative with respect to VI yields

Noise Margins equations (cont.)

Summary of the noise margin of a symmetrical CMOS inverter


NML = VIL - VOLU (noise margin for low input)

Taking derivative with respect to VI yields (2) At VIL (3) (4) Assume CMOS is symmetrical i. e. KN=KP Substituting (5) into (1) (6) (5)

(7)

NMH = VOHU - VIH (noise margin for high input)


(8)

(9) Assume CMOS is symmetrical i. e. KN=KP (10) Substituting (10) into (6)

Summary of the noise margin of asymmetrical CMOS inverter


NML = VIL - VOLU (noise margin for low input) NMH = VOHU - VIH (noise margin for high input)

CMOS Logic Circuits


Large scale integrated CMOS logic circuits such as watched, calculators, and microprocessors are constructed by using basic CMOS NOR and NAND gates. Therefore, understanding of these basic gates is very important for the designing of very large scale integrated (VLSI) logic circuits.

CMOS NOR gate


CMOS NOR gate can be constructed by using two parallel NMOS devices and two series PMOS transistors as shown in the figure. In the CMOS NOR gate the output is at logic 1 when all inputs are low. For all other possible inputs, output is low or at logic 0.

CMOS NAND gate

How can we design CMOS NOR symmetrical gate?


In order to obtained symmetrical For asymmetrical case switching time is longer switching times for the high-to-low and low-to-high output transitions, the effective conduction (design) parameters of the composite PMOS and composite NMOS device must be equal. For the CMOS NOR gate we can write as, KCN=KCP

Concept of effective width to length ratios


Parallel combination Series combination

In CMOS NAND gate the output is at logic 0 when all inputs are high. For all other possible inputs, output is high or at logic 1.

By recalling effective channel width and effective channel length concept, the effective conduction parameter for NMOS and PMOS for a CMOS NOR can be written as, K K n 2W p W = 2 L N 2 2L p Since Kn~2Kp
2W W 2 = L N 2L p

or

W W = 8 L P L N

This implies that in order to get the symmetrical switching properties , the width to length ratio of PMOS transistor must be approximately eight times that of the NMOS device.

Fan-In and Fan-Out


The Fan-in of a gate is the number of its inputs. Thus a four input NOR gate has a fan-In of 4. Similarly, Fan-Out is the maximum number of similar gates that a gate can drive while remaining within guaranteed specifications.

Propagation Delay Definitions


The propagation delay tp of a gate defines how quickly it responds to a change at its input(s).

Vin

Vout

Switching Time and Propagation Delay Time


The dynamic performance of a logic circuit family is characterized by propagation delay of its basic inverter. The propagation delay time is define as the average of low-

Inverter Transient Response (input step pulse)


3 2.5 2

Vin
Propagation delay input waveform
50%

Vin

tp = (tpHL + tpLH)/2 tpLH


90% 50% 10%

Vout (V)

1.5 1 0.5 0

VDD=2.5V 0.25m W/Ln = 1.5 W/Lp = 4.5 Reqn= 13 k ( 1.5) Reqp= 31 k ( 4.5) tpLH tr tpHL = 36 psec tpLH = 29 psec so tp = 32.5 psec

tpHL Vout
output waveform

signal slopes

tf

tr

The propagation delay time is directly proportional to the switching time and increases as the Fan-out increases. Therefore, the maximum Fanout is limited by the maximum acceptable propagation delay time.

to-high propagation delay time and the high-to-low propagation delay time.

tpHL

tf

-0.5 0 0.5 1 1.5 2 2.5

t (sec) From simulation: tpHL = 39.9 psec and

x 10-10

Each additional load gate increases the load capacitance their must be charge and discharge as the driver gate changes state. This place a practical limit on the maximum allowable number of load gates.

tpLH = 31.7 psec

Propagation Delay Estimate

Switch-level model
Delay estimation using switchlevel model (for general RC circuit):
dV C I =C dt = dV dt I V RC I= dt = dV R V t1 t 0 = t p =
V1

Switch-level model
For fall delay tphl, V0=Vcc, V1=Vcc/2

Rn

CL

V1 1 2 VCC = t p = RC ln RC ln V V 0 CC t p = RC ln(0.5) t phl = 0.69 Rn C L t plh = 0.69 R p C L

The two modes of capacitive charging/discharging that contribute to propagation delay

V0

RC dV V

V1 t p = RC [ln(V1 ) ln(V0 )] = RC ln V 0

Standard RC-delay equations

Transmission Gates
Use of transistors as switches are called transmission gates because switches can transmit information from one circuit to another.

NMOS transmission gate as an open switch.


The figure shows NMOS transmission gate. The transistor in the gate can conduct current in either direction. The bias applied to the transistor determines which terminal acts as the drain and which terminal acts as the source. When gate voltage =0 The n-channel transistor is cut off and the transistor acts as an open switch

Characteristics of NMOS transmission gate (at high input)


If =VDD, VI=VDD, and initially, the output V0 is 0 and capacitance CL is fully discharged. Under these conditions, the terminal a acts as the drain because its bias is VDD, and terminal b acts as the source because its bias is 0. The gate to source voltage can be written as VGS=-VO or VGS= VDD-VO As CL charges up and Vo increases, the gate to source voltage decreases. When the gate to source voltage VGS become equal to threshold voltage VTN, the capacitance stop charging and current goes to zero. This implies that the VO=VO(max) when VGS=VTN Or VO(max) = VDD-VTN

This implies that output voltage never will be equal to VDD. ; rather it will be lower by VTN. This is one of the disadvantage of an NMOS transmission gate when VI=high

Characteristics of NMOS transmission gate (at low input)


When VI=0 and =VDD and VO=VDD-VTN at t=o (initially). It is to be noted that in the present case terminal b acts as the drain and terminal a acts as the source. Under these conditions the gate to source voltage is,

Why NMOS transmission gate does not remain in a static condition? The reverse leakage current due to reverse bias between terminal b and ground begins to discharge the capacitor, and the circuit does not remain in a static condition.
VDD-Vt

VDD-Vt

VGS=-VI VGS=VDD-o

source

gate

This implies that value of VGS is constant. In this case the capacitor is fully discharge to zero as the drain current goes to zero.

vGS=vDD

drain

source

gate

drain

VO=0
This implies that the NMOS transistor provide a good logic 0 when VI=low

VO(max) = VDD-VTN