EE 287

Power Consumption

Power
Limits package choices
Package must dissipate power

Impacts overall system design

Must remove heat from system Must supply required current

Active cooling adds cost

Fans, Heat pipes, Heat sinks

Battery life in portable products

EE 287 notes Morris Jones

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Basic Power equations

dv dt P = iV 1 F~ dt i ~ cdvF i=c dv ~ V i ~ cVF P ~ cV 2 F
EE 287 notes Morris Jones

We dont know the Constant of proportionality

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More basic power equations

P ~ CV F F ~V P ~ CF
EE 287 notes Morris Jones

Change V and F From the basic CMOS delay equation

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This is why you cant build A high speed part in old technology

Power examples
P( C, V, F) := C V F C := 1 Normalize C for now (C~number of gates) Ignore units, only proprotional Af := 1
2

P( C, 2.5, 100) = 625 P C, 2.5 150 100

, 150 = 2109

Af C 2.5

150 100
2

150 = 3.375 Increase the clock rate 50% Power increases by 3375%

Af C 2.5 100

EE 287 notes Morris Jones

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Full Scaling
Change both the voltage and frequency Best power savings Assume part was running at the fastest speed possible at the old voltage Scaling only works down to about 2 Vt
Any lower, and performance becomes complex function
EE 287 notes Morris Jones

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In General
We dont know the proportionality constant We dont really know C until physical design is complete Not every gate switches every clock cycle
Activity factor
Varies from a few % to several hundred %
Signals may switch once every few clocks, or many times per clock cycle (Adder carry bits)

Is a function of how the part is used!!!

Not static Simulations are seldom typical of part usage
EE 287 notes Morris Jones

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Power estimation issues

Frequency has many components
Square wave contains all odd harmonics Need to take the Fourier transform

Need to know the activity levels of each signal in the ASIC

Some cad tools exist to aid power estimation Many are off by a significant amount
EE 287 notes Morris Jones

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Activity level
Strong function of design style
Design for speed Design for power Design for cost

Many simulators report activities

Are test patterns Typical usage?

Early/late decisions impact number of gates that switch

EE 287 notes Morris Jones

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Much useful information

Most ASICs arent designed from scratch
Reuse of prior chips, or blocks Power can be measured on old chip Scale power to new design considerations Assume new design has activity levels like the reused IP
EE 287 notes Morris Jones

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Example
Assume an old chip ran at 100Mhz, in 0.25u (V=2.5) and disipated 1W. If we move the chip to .13 micron, V=1.2 what will the power become? Assume same capacitance Af := 1 C := 1 C 2.5 100 C 1.2 100
2 2

1 P

solve , P .23040000000000000000

Power reduced by a factor of 4!!!

EE 287 notes Morris Jones

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Another example
Assume an old chip ran at 100Mhz, in 0.25u (V=2.5) and disipated 1W. If we move the chip to .13 micron, V=1.2 How much more logic can the chip have at the same power?
Af := 1
2

C := 1 1 1

Assume unit capacitance

solve , G 4.3402777777777777778

C 2.5 100 G C 1.2 100

2

4x the gates for the same power !!!!

EE 287 notes Morris Jones

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Capacitance
Not easy to estimate To a 1st order, a function of the number of gates
If you increase the gates by 10%, increase the capacitance by 10%

Charts of capacitance per net go up as chip size increases

As you increase the chip size, increase the capacitance
EE 287 notes Morris Jones

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Capacitance table
1.2M gates

2.5M gates Capacitance/gate increases As chip size increases!!!

EE 287 notes Morris Jones

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Courtesy Toshiba Corporation

Lower power
Assume Frequency and gates are proportional (1st order architectural assumption) How much more logic is required to cut power to 1/2 C := 1 C V F G C 1 1.414 V F G G
2 2

V := 1 1 .5 solve , G

1.4142135623730950488 1.4142135623730950488

= 0.707

If gate count is increased 40%, then Voltage and Frequency are reduced 30%. Result 1/2 power

EE 287 notes Morris Jones

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With Capacitance growth

Assume Frequency and gates are proportional (1st order architectural assumption) How much 9.5 = 1.173 more logic is required to cut power to 1/2 8.1 C := 1
2

V := 1 C V F 1
2

G 1.173 C 1 1.414 = 0.707

F G

.5

solve , G

1.5316657598836633914 1.5316657598836633914

If gate count is increased 50%, then Voltage and Frequency are reduced 30%. Result 1/2 power

EE 287 notes Morris Jones

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Low Power design

Starts at architectural level Parts tend to be wide
Larger data paths More computation engines

Parts tend to be slower

Allows voltage scaling

Parts tend to cost about 50% more

Compensates for additional logic
EE 287 notes Morris Jones

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Low Power design

Many other low power design techniques available
Reduce F
Clock gating Quiet busses Early decision on logic trees Serial computation/decision making
Less unused calculations/decisions

EE 287 notes Morris Jones

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Performance/power tradeoff
Assume a product that has two performance goals Full speed at high power, and 1/2 power at reduced Performance. How much is performance reduced? F := 1 C V F C V
F F2 2

1 .5

F2

solve , F2

.68736481849930131 .39685026299204986869 .39685026299204986869 + .68736481849930131 .79370052598409973738

If the power is to be cut in half, then reduce the frequency and voltage by 20% Notebook computers use this to reduce power when operating on batteries

EE 287 notes Morris Jones

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Leakage
As the Vt of a transistor is reduced
Leakage increases Goes up by 10X for every 60mV decrease Transistors do not turn off as hard
Simple switch or equation model not valid
Transistor keeps conducting a little

Leakage power constant

Increases with the number of gates
EE 287 notes Morris Jones

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Leakage power issues

To reduce leakage power
Turn off voltage to sections of the chip
Requires separate power wells

Pump wells
Modifies threshold

Most chips have two types of transistors

Make FFs out of High voltage (low leakage) devices Makes gates out of fast but leaky transistors Turn off power to gates, keep power to FFs Done in custom logic. Not done much in ASICs
EE 287 notes Morris Jones

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I/O core voltages

Core voltage can Be changed Independently Of I/O voltages

EE 287 notes Morris Jones

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Courtesy Toshiba Corporation

Package Power
JA is resistance From chip to ambient

Thermal resistance getting heat from silicon to environment Silicon limited to about 100C (85 to 125 depending on reliability)
EE 287 notes Morris Jones

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Courtesy Toshiba Corporation

Temperature rise
If JA is 27/Watt If Power is 2.5W Temperature rise 27*2.5=67.5 If the die temperature is limited to 100 Max environment temp = 100-67.5
32.5 degrees

EE 287 notes Morris Jones

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Examples of thermal data

EE 287 notes Morris Jones

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Courtesy Toshiba Corporation

BGA Heat Path

Many BGA designs assume heat is carried to copper In the circuit board. Need to communicate assumptions To board designers
EE 287 notes Morris Jones

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Courtesy Toshiba Corporation

Thermal Pads
Many BGA packages have extra pads
Remove heat Underneath Die
Die placed up, not down in this case

Often connected to ground

Board has large ground plane May not be use electrically

EE 287 notes Morris Jones

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