324

Characteristics o f the Metal-Oxide-Semiconductor Transistors

c. T. SAH, MEMBER,
Summary-The theory of the MOS transistor in thegradual channel approximation is presented with the assumption of constant surface and bulk charge, and constant surface mobility. From the simple theory, the complete design equations are derived and design curvesare calculated. From the analysis, the equivalent circuit parameters of the device are related to the basic properties of the material and geometry of the device. The simple theory is then critically compared with experimental measurements of MOS transistors with circular geometry. The comparison shows good general agreement with the theory of the dc characteristics but discrepancies are found for the differential characteristics such as the transconductance and the gatecapacitance. The possible sources of the discrepancies are discussed.
IEEE

I. INTRODUCTION
HE FIRST attempts t o realize active solid state devices operating on the field effect principle appear to have been undertaken by J. E. Lilienfeld of New York whichweredisclosed in a series of three patents issued in 1930, 1932 and 1935. Another independent effort was also undertaken at aboutthis time by Oskar Heil in Germany which was recorded in a British patent issued in 1935.1dStudies of the field effect undertaken atthe Bell Telephone Laboratories after the war under the direction of Shockley2led to the discovery of the transistor effect by Bardeen and Brattain2b in 1948. The effect was first observed during a series of experiments in which they attempted to modulate the current flowing througha point contact made on germanium by controlling the electric field at the germanium surface near the contact by the use of an electrode in close proximity tothecontact.2(a) This discovery ledt o the development of the point contact transistors2(b)and subsequently the invention of the
Manuscript received January 31, 1964; revised March 24, 1964. The author was formerly with the Fairchild Semiconductor Research and Development Laboratory. He is now with the University of Illinois, Urbana, Ill. I(a) , U,. S.Patent 1745175, filed October 8,1926; granted January
Ad, I Y S V .
7

non

(b) U. S. Patent 1877140, filed December 8, 1928; granted September 13. 1932. (c) U. S. Patent 1900018, filed March 28, 1928; granted March 7, 1933. The structures proposed in these three patents were recently misinterpreted by V. E. Bottom in Invention of the solid-state amplifier, Physics Today, vol. 24, pp. 24-26; February, 1964. It is pointed out by J. B. Johnson that these structures of Lilienfeld are indeed field effect devices rather than bipolar transistors of Bardeenza), Brattainz (b) and Shockley3. See J. B. Johnson, More on the solid state amplifier, t o be published in Physics Today. (d) British Patent 439457, filed March 4, 1935; granted December 6, 1935. (a) J. Bardeen, Semiconductor research leading t o the point contact transistors, 1956 Nobel Lecture, published in Science, vol. 126, pp. 105-112; 1957. (b) 9 . Bardeen and W. E L . Brattain, The transistor: a semiconductor triode, Phys. Rev., vol. 74,p.230; July, 1948; also U. S. Patent 2524035, October, 1950.

bipolar junction transi~tors,~ all of which operate on the principle of minority injection rather than fieldeffect. At this time Pearson alzd Shockley had experimented with the fieldeffect in which modulation of the conductivity of a thin semiconductor film was achieved by an electric field applied perpendicular to thefilm ~ u r f a c e . ~ Considerable smaller conductivity modulation was found than expected, and they interpreted the discrepancy as due to a high concentration of surface states at the semiconductor surface, basedon a modelproposed by Bardee~ The ~ device geometry inthe experiments of Pearson and Shockley is similar t o those proposed by Lilienfelds and Heild which are shown im-Fig. l(a) and (b). Although these initialand the subsequent attempts to acheive a solid-state amplifier by modulating the electric field at the semiconductor surface were not too successful, this method of conductivity modulation has since been employed to the study of the electronic properties o f the semiconductor surfaces, which are generallyknown as the fieldeffectexperiments, by numerous workers. An alternative approach to an active solid-state field effect device was conceived by Shockley7 and later successfully built in which a reverse biased p n junction is used as the fieldeffect electrode. The point contact and the bipolar junction transistors have dominated the development and the progress of solid-state electronicssince their invention. In the last five years, the semiconductor technology has been refined to a state so that volume production of the junction gate field effect transistorhas alsobecomecommerciallyfeasible. The obstacles which prevent the progress towards a practical surface controlled active fieldeffect transistor seem to lie mainly in the lack of the controllability and stability of the surface although the difficulty of extremely high concentration of surface states (of the order of 1015/cmzor one monolayer), whichexisted in Pearson and Shockleys experiment14does not seem t o appear for an oxidized semiconductor surface. These fabrication problems are still not completely solved,
a W. Shockley, The theory of p-n junctions in semiconductors and p - n junction transistors, B. S. T . J., vol.28, pp. 435-489, July, 1949; also U. S. Patent 2569347, September 25, 1951. * W. Shockley and G. L. Pearson, [Modulation of conductance of thin fdms of semiconductors by surfacecharges, Phus. Rev., V O ~ .74, pp. 232-233; July, 1948. 6 J. Bardeen, Surface states and rectification at a metal semiconductor contact, Phys. Rev., vol. 71, pp. 717-727; May, 1947. W. H . Brattain and J. Bardeen, Surface properties of germamum, Bell Sys. Tech. J., vol. 32, pp. 1-41; January, 1953. See also R.H. Kingston, Ed., Semiconductor Surface Physics, University of Pennsylvania Press, Philadelphia, Pa.; 1957. 1 W. Shockley, A unipolar field-effect transistor, PROC. IRE, vol. 40,pp. 1365-1376; November, 1952.

1364
March 7.1933.

Characteristics Sah:
J. E. LILIENFELD
DEVICE FOR CONTROLLIN0 ELECTRIC CURRENT
P i l e d Marcn 28. 1928 3 ShseLs-Sbeet 1

of MOS Transistors
1.900.018

325

Fig. 1-The field effect transistor structures. ( a ) The metal-oxidesemiconductor transistor proposed by Lilienfeldl(G). (b) The proposed by metal-oxide semiconductor thin film transistor Heil*(d).

however, the solutions, being hastened bythe recent advances made in the silicon transistor fabrication technologyusingoxide surface protection techniques, seem to be just over the horizon. These technological advances have made it possible to fabricate and study the properties of useful and relatively stable surface field effectactive device structures and t o studythe surface physics of the more practical surface, the silicon-silicondioxide In the present paper, we shall study the elementary theory and the principle of operation of the semiconductor surface field effect transistor in detail. Because of the device structure, the name metal-oxidesemiconductor transistor or MOS transistor is adopted throughout this paper.

1 1 . DEVICE STRUCTURE

The MOS transistorstructuresare shown in Figs. 2-The geometry of N-channel MOS transistors. (a) Top view. 2(a)-(d). The cross-sectional viewof the circular geometry Fig. (b) Cross-sectional view. ( e ) The expanded channel region of the given in Fig. 2(a) is shown in Fig. 2(b) and the coordinate circular geometry. (d) The linear structure. axes are labled in Fig. 2(c). The linear geometry is shown in Fig. 2(d) where the coordinates are also shown. These These basic structures were first proposed by D. Kahng coordinates will be used inthe mathematical analysis and M. M. Ata1la.l The mode of operation to bedisof the device characteristics. cussed in this paper was conceived in Kallngs patent.

* For a comprehensive review of the silicon planar technology developments see G. E. Moore, SemiconductorIntegrated Circuits,: Chapter 5 of Principle of MicroelectronicEngineering, E. Keonjian, Ed., McGraw-Hill Book Co., Inc., New York, N. Y.;

10 U. S. Patent No. 3102230, Electrical Field Controlled Semiconductor Devices, filed May 31, 1960 and issued on August 27, 1963 to D. Kahng; and U. s. Patent No. 3056888, Semiconductor 1962. Triode, filed August 17, 1960 and issued on October 2,1962 to C. T. Sah, A New SemiconductorTetrode, The Surface- M. M . Atalla. Some of the materials covered in these two patents Controlled Transistors, presented at WESCON, San Fran- were presented atthe IRE-AIEE Solid State Device Research IRE, vol. Conference, Pittsburgh, Pa.; June, 1960 by these authorsin Siliconcisco, Calif.; August, 1961; publishedin PROC. 49, pp. 1623-1634; November, 1961. Silicon Dioxide Field Induced Surface Devices. (b) C. T. Sah, Effect of surface recombination and channel on l1 This mode of operation was discussed by S A g and in an p-n junctionandtransistorcharacteristics, IRE TRANS.unpublishedreport by H. K. J. Ihantola,DesignTheory of a ON ELECTRON DEVICES,vol. ED-9, p p . 94-108; January, Surface-field-Effect Transistor, StanfordElectronics Laboratory 1962. Report No. 1661-1; September, 1961.

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TRANSACTIONS IEEE

ON ELECTRON DEVICES

Jd?]

The N regions of the structures shown in Fig. 2 are obtained by high temperature diffusion of phosphorus impurityinto the P-type silicon substrate usingoxide masking techniques. One of the N-type regions labeled S for source112is electrically connected to the P-type bulk by means of a metal layer (darkarea), although this internal connection is not essential and without it the device becomes a four terminal structure. The other N region, labled D for drain, is usually employed as the output lead with the source as the common lead totheinput andoutput.Theinput electrode is the metal electrode over the oxide labled G! for gate.12 For the structures shown in Figs. 2(a)-(d) which employ a P-type substrate, if the surface region under the gate electrode in the semiconductor silicon is made N-type during the high temperature diffusion and oxidation processes, then a conduction path for electrons willbe present between the drain and the source electrodes even at zero gate voltage. Such a structure has eIectricaI characteristics very similar to the unipolar junction gate field effect tran~istor.~ This type of device is sometimes known as the depletion mode t r a n s i ~ t o r , ~ ~ t h is, a tthe current path between the source and the drain electrodes at zero gate voltage can be reduced or the electrons in the path can be depleted, however, it can also be operated in the enhancement mode in which the source to drain current is enhanced by a positive gate voltage. Structures without the built-in channel are very useful in digital integrated circuit app1i~ations.l~ Such a structure is sometimes known asthe enhancement mode transistor l 3 which appropriately describes the operational characteristics of the device since it cannot be operated in the depletion mode. The oxide under the metalgate electrode shown in Fig. 2 may be formed during the phosphorus diffusion process. Alternatively, this oxide may be stripped off and regrown either thermally a t high temperatures or anodically a t r2om temperatures. Oxide thickness of the order of 1000 A is generally used. Thick oxidereduces the transconductance, the gain and speed of the device for a given dc operating point and very thin oxide makes the reproducibility of the device difficult. The metal gate electrode and metal electrodes which form the ohmic contacts t o the N-type diffused source and drain regions are made by evaporation and photoengraving techniques. Metals such as aluminum, silver, gold, platinum, chromium and others may be used.

1 1 1 . SURFACE ENERGY B A N D DIAGRAMS The operation of MOS transistors can be understood on a quantitive and physical basis by studying the energy band diagrams under various bias conditions. In Fig. 3(a)-(f) the energy band diagrams or the variation of the electron potential energy along the x-axis is plotted for a y = constant plane in the region between the N islands for the structures shown in Fig. 2. For simplicity of preliminary discussions, the surface statesandthe difference of work functions between the metal g a b electrode andthe semiconductor are neglected inthe first four energy band diagrams. These four cases all correspond to thermal equilibrium, ie., no potential and current between the source and the drain electrodes. The equilibrium condition prevails essentially for all values of gate voltage V,, since the silicon oxide insulating layer has very high resistivity ohm-cm) at room temperatureand extremely low leakage current. At zero gate voltage, V , = 0, .the energy band is flat as indicated in Fig. 3(a) for the case of no surface states and negligible metal to semiconductor work function difference. When a small positive voltage is applied to the gate eIectrode V G > 0, the energy band bends downward as shown in Fig. 3(b). An exhaustion layer (exhausted of majority carriers, in this case holes) is formed near the silicon-silicon oxide interface. Further increase of the gate voltage results in the formation of an N-type surface layer. The on-set condition of an N-type surface is given by the condition of intrinsic surface which is shown in Fig. 3(c) in which the intrinsic Fermi level at the interface E i ( x = 0 ) coincides with the Fermi level in the bulk E , or F , which is flat and independent of position. Still further increase o f the gate voltage results in an inversion layer or an electron channel which provides the conducting path for electrons between the two N-type islands. At large positive gate voltages, the surface potential along the channel is essentially locked at Ec(N), the conduction band edges of the N islands as indicated in Fig. 3(d). This is due to the fact that the surface becomes strongly degenerate under large positive gate voltage and that there is a large source of minority carriers (in this case electrons) from the N source and drain islands which can flow into the channel. Numerical caIcuIations of the exact solutions in the gradual channel approximation have verified these energy level diagrams. (To be published by C. T. Sah and H. Pao.) The conduction of the electrons in the surface channel is perhaps more clearly shown in Fig. 4, wherethe electron energy surface corresponding tothe conduction band 12 The nomenclatures here are borrowed from those for the is drawn for various bias conditions. To simplify the drawunipolar junction gate field effect transistors adopt,ed by Shockley7 ings, the transition regions of the junctions in each of the since the functions of the corresponding electrodes for the two types graphs are shown as vertical surfaces and the surface under of field effect transistors are identical. 13 P. K. Weimer, The TFT-A new thin-film transistor, the metal gate electrode in the N regions are not bended PRac. IRE, vol. 50, pp. 1462-1469; June, 1962. by the gate vo1tage.The equilibrium energy band contour 14 F. M. Wanlass and C. T. Sah, Nanowatt logic using fieldeffectmetal-oxide-semiconductor triodes, Digest of Tech. Papers, IRE International Solid State Conf., Lewis Winner, New York, for zero gate anddrain to source voltage isshown in N. Y.; 1963; G. E. Moore, C. T. Sah and F. Wanlass, Metal- Fig. 4(a) which corresponds to Fig. 3 (a). In Fig. 4(b), for micropower logic oxide-semiconductor field effect devices a small positive gate voltage is applied but still with circuitry, Presented at the 1963 International Microwatt Circuit V, = 0. This diagram corresponds tothat shown in Symposia in Europe; July, 1963.

1964

Sah: Characteristics of MOS Transistors

327

OXIDS
WThl

SEMICONDUCTOR

4T

- E;
F m

p- type region-

depletlon region inversion layer (N-typesurface channel)

Fig. 3-The

surface energy band diagrams in the z-direction perpendicular to the channel current flow direction at (a) Vc = 0, (b) small positive V,, (e) at V , for intrinsic surface, and (d) at VQ forthe on-set: of electron surface channel. Surface energy bands including surface states and work function difference between themetaland semiconductor at (e) equilibrium and (f) nonequilibrium.

P-type S i l i c o n

.-/

Vu=O.

I )

ss #O

A-7

V
v =v
=2,

io

l4
/ /

M
Channel

byk

pinched-off region

L , '

Fig. 4-The equipotential surfaces of electrons and energy surfaces of the conduction band at various bias conditions.

328

IEEE TRANSACTIONS ON ELECTRON DEVICES

July

Fig. 3(b) where an exhaustion layer is created near the surface. Further increase of the gate voltage but still with the source to drain potential zero is shown in Fig. 4(c). It is evident that at thisgate voltage a surface channel for electrons is created since the conduction band edgebetween the source anddrain electrodes at the surface is now at the same level as those in the source and drain regions. I f the gate voltage is further increased, beyond that given in Fig. 4(c), a large channel is formed and the surface is strongly degenerate N-type. The surface potential energy of the conduction band edge is nearly 'locked' at the position given in Fig. 4(c) due to the strong degeneracy and the presence of two sources of infinite supply of electrons due t o the N' source and drain islands. This situation is illustrated in Fig. 4(d), which corresponds t o the cross-sectional view of the energy band shown in Fig. 3(d). I f the surface states and the work function differences between the metal and the semiconductor are taken into account, the energy band diagrams shown in Figs. 3(a)-(d) and Figs. 4(a)-(d) just discussed are modified. These mod5cationsare shown in Figs. 3(e) and 4(e) where the drain-to-source voltage is zero and the surface states are assumed to be donors and ionized and hence positively charged. I n Fig. 3(e) the dash line corresponds to the conduction band and the valence band edges of the insulator. I n Fig. 4(e) the energy band contours are rounded and the effect of the gate potential on the surface energy band in the N' regions is also illustrated. These are disregarded in all other diagrams. One importantparameter of a metal-insulator-semiconductor sandwich is themetal semiconductor work function difference given by the expression +Ls = + N (x + F EG/2). The various quantitiesinthis expression are shown in Fig. 3(e). +M is the work function of electrons in the metal whichis the energy required t o remove an electron at the Fermi surface of the metal t o infinity. x is the electron affinity in the semiconductor and is the barrier height of the vacuum level measured from the bottom edge of the conduction band at the surface. C#Ip E,/2 is the Fermi potential of electrons inthe semiconductor measured from the bottom edge of the conduction band. Other parameters which are necessary to describe the electrical characteristics of an MOS structure arethose which characterize the surface states and bands at the silicon and silicon dioxide interface. Fora surface band, it isnecessary t o know the density of states in the bands as a function of energy and the total surface state concentration per unit surface area in order t o establish the equilibrium energy band diagram and equipotential surfacesshown in Figs. 3(e) and 4(e). For the assumed ionized and positively charged donor states, the surface energy band ispulleddown as indicated in Fig. 3(e) from the flat band condition shown in Fig. 3(a). The amount of band bending is also dependent on the work function difference just discussed. It is evident from the energy band diagram shown in Fig. 3(e) that the energy band can be made

flat i f + p or if the impurity concentration in the P-type bulk is increased. This can also be accomplished if the metal work function C#IM is increased by selecting a different metal or an alloy for the gate electrode. The dynamic parameters of the surface states or bands are also required in order t o study the frequency dependence of the electrical characteristics of the MOS structure. These are the transition probabilities of electrons and holes between the conduction or valence band states and the surface states or the surface band states. The surface state or band parameters are one of the least known quantities in solids, especially in a situation such as the present MOS structurein which the semiconductor surface is covered with an oxide layer which is thermally grown. In this case, the number of surface states is considerably less (in fact less) than a perfect and clean surface which has about dangling bonds per cm2 and approximately l O I 5 states per cm'.On the oxidized surface obtained during high temperature processes, these bonds are mostly tiedup by the oxygen forming silicon-oxygen bonds and thus do not contribute to surface states. Generally for an oxidized silicon surface, the remaining surface states are donor type rather than the acceptor type from the dangling bonds and have a total concentration of 10" to 10" states per cm2. I f this had not been the case, neither transistors and diodes nor the MOS devices would have been useful devices. This very factor prevented Pearson and Shockley from obtaining the anticipated conductivity modulation bythe applied surface electric field in tlze first metal-insulator-semiconductor device e~periment.~ Because of the unavailability of the surface band and state parameters, we shall lump all the surface states and denote this by a h e d charge of Q s s per unit surface area in this paper. The energy band diagrams are further modified if a voltage is applied between the drain and the source electrodes. This diagram along the x axis for a small positive drain voltage (drain junction reverse biased) is shown in Fig. 3(f), which shows that next t o the highly degenerate N-type surface channel or inversion layer, there is a region which is essentially depleted of carriers and labeled as the depletion region. The energy surfaces are also sketched for three drainto-source voltages and shown in Figs. 4(f)-(h). Fig. 4(f) corresponds to a drain voltage which is small compared with the gate voltage, and the surface channel is fairly wide open along its entire length between the source and drain. I n Fig. 4(g) the drain voltage is equal t o the gate voltage in excess of the turn-on gate voltage, ie., V o = V G - V T where VT is determined by the condition shown in Fig. 4(c). Under this condition, the width of the surface channel is narrowed down t o zero at the drain electrode as indicated in Fig. 4(g) and the channel is said t o be pinched 08at the drain. At pinchoff, the channel current, which comes from electrons flowing from the source to the drain, is essentially controlled by the not-pinched-off region of the channel.

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Sah: Characteristics of M O X Transistors

329

I f the drain voltage is further increased, such as that shown in Fig. 4(h), almost all of the additional voltage increase, i.e., [V, - ( V , - V T ) ]appears , across the pinched-off region which is now extended from the drain to a point at a distance L - 4 in the channel as indicated in the figure. The drain current is essentially constant, independent of the drain voltage, when the drain voltage is increased beyond that given by Fig. 4(g). The slight increase of the drain current from the condition in Fig. 4(g) where V, = V G - V , to the condition in Fig. 4(h) where V , > V G - V r comes from the slight decrease of the channel length of the nonpinched-off region. This alsogives a finite, ratherthanan infinite, drain resistance. This channel shortening effect is very similar tothe well-known space charge layer widening effect or Early effect ina bipolar junction transistor which causes a considerable collector conductance.15 The condition shown in Fig. 4(g) where the drain voltage is equal to the excess gate voltage over the turnon gate voltage is known as the condition of saturation since the drain current is saturated and furtherincrease of the drain voltage results in very little increase of the drain current. Another important part of the energy band diagrams and surfaces is the contour of the electron and hole quasi-Fermi levels or potentials which we shall discuss next. In thelastthree energy surfaces shown in Figs. 4(f)-(h) where a finite drain voltage is applied, the electron concentration in the channel isdifferent from the equilibrium value. In terms of an electron quasiFermi level F , inthe Boltzmann factor, the electron concentration may be written as
n = ni exp (F,

and the variation of the hole concentration in lthe channel regioncomes mainly from the variation of the electrostatic potential u(x, y) in (2). The variation of the quasi-Fermi levels for electrons may now be considered. Since the electron diffusion current outside the channel regionis small compared with the generation-recombination current in wide band gap materials such as silicon, there is a corresponding change of the electron quasi-Fermi level with the 5 direction. However, since the width of the channel is usually quite small, one may assume that the electron quasi-Fermi level is essentially constant independent of the x coordinate near the surface and in the surface channel region as indicated in Figs. 3(f)-(h). The difference between P, and F, is the voltage difference between this point in the channel and the source electrode where F, = F,. One can readily make this conclusion by considering the variation of the electron quasi-Fermi level with the y coordinate along the channel. At the source electrode, the electron and the hole quasi-Fermi levels concide with the bulk Fermi level, Le., F , = F , = E F as indicated in Figs. 4(f)-(h). At the drain electrode, the electron and hole quasi-Fermi levels must differ by the amount corresponding t o the drain voltage, Le., F , - F , = -qVD. The negative signcomes from the particular sign convention chosen for the drain voltage which makes the drain junction reverse biased when V, > 0. It is thus evident that atany point in thechannel which is adistance y from the source electrode, the voltage measured relative to the source is given by - (Fn - F,)/q. Denoting the channel voltage by V(y), then

V ( Y )

- E,)/kT

pV(y)/kT
=

=
p

-(Fm- FJ/LT
= un(y)

= n,

exp (u - un)

(1)

an(y) - u

- up

where ni is the intrinsic carrier concentration, E i is the intrinsic Fermi level, . u , is the normalized electron quasi-Fermi potential given by u, = - F J k T and u is the normalized intrinsic Fermi potential given by u = -.Ei/kT. (See also the list of symbols for the definition of the notations.) Similarly, the hole concentration in the surface region also differs from that in the bulk due to the bending of the energy band. However, the hole quasi-Fermi level F, is essentially independent of distance and coincides with the equilibrium Fermi level in the bulk. This occurs because the hole current, which is proportional to the gradient of the hole quasi-Fermi potential, is small compared with the electron current in thechannel since the hole current comes almost entirely from the generation processes fromsurface states andbulk Shockley-Read-Hall centers in the inversion and the depletion regions indicated in Fig. 3(f). Thus, the concentration of holes may be written as
p = ni exp (Ei - F,)/kT
= ni exp (up - u)= ni exp

<y <

(3)

In the direction other than along the surface channel, the electron quasi-Fermi level F , near the N drain region decreases exponentially with distance away from the drain contact towards the bulk Fermi level E,. This variation of F , is also shown in Figs. 4(f)-(h).

IV. ELEMENTARY PHYSICAL THEQRY In order t o bring out some of the most important physical parameters which control the electrical characteristics of the surface channel and the MOS transistor, we shall give a mathematical analysis based on a simple physical model inthis ~ecti0n.l~ The simple physical
l6 C. T. Sah, R. N. Noyce and W. Shockley, Carrier generation and recombinationin p-n junction and p-n junction characteristics, PROC. IRE, vol. 45, pp. 1228-1243; September, 1957. l7 An elementary analysis due t o A. Many has recently been published by H. Borkenand K. Weimer in An analysis of the characteristics of insulated-gate thin-film transistors, RCA Review, vol. 24, pp. 153-165; June, 1963. This analysisextends the work of Ihnatolal-l by including the initial charge present in the semiconductor,although i t does not relateexplicitly the initial charge to the material and interface properties of the insulator and semiconductor. The analysis in this section follows essentially the same line of attack and was quoted in parts by Sahg. It, however, relates more explicitly the properties of the materials t o the device characteristics than the work given by Borken and Weimer.

(up - u)

(2)

16 J. M. Early, Effect of space-charge layer widening in junction transistors, PROC. IRE, vol. 40, pp. 1401-1406; November, 1952.

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IEEE TRANSACTIONS ON ELECTRON DEVICES 1 , =2

July

model will be based on the following assumptions: 1) The junction current flowing in the drainjunction is excluded, 2) no electron-hole recombination and generation in the channel from either the surface states or the SRH centers, 3) the variation of thewidth of the channel is small along its length, 4) the substrate is nondegenerate, 5) the diffusion currentinthe channelisnegligiblecompared with the currentdue to theelectric field along the channel, and 6) the surface states may be lumped into a fixed charge with total charge given by Q s s per unit area of surface. With reference t o Fig. 2(d), it is evident thatthe current flowing into the drain contact I , consists of two parts, the current flowing into the surface channel and thecurrent flowing into the substrateover the barrier of the NP drain junction. The surface channel current may be divided into three parts: 1) The electron current due to the electrons flowing into the channel either from the drain N* island if the drain junction is forward biased (VD< 0) or from the source N island if thedrainjunction is reverse biased (V, > 0 ) ) whichcorresponds t o the MOS transistor mode of operation. This is the dominating channel current when the MOS transistor is turned on. 2) The hole current from the holes due to ionized acceptor impurity in thesubstrate.Thiscurrentis very small compared with the electron current when the device is turned on since most o f the holes in the surface channel are pushed intothe bulk region by the electric field normal to thesurface from the large positive gate voltage. 3) The electron and hole current from carrier generation and recombination from the surface states and from the Shockley-Read-Hall centers in the channel. These contributionsare also quite small compared with the electron current when the channel is turned on,which are neglected as stated in ( 2 ) . The other part of the drain current, which comes from the drain junction current, is excluded. It can be simplyadded to the channel current t o give the total drain current. For the MOS transistor mode of operation, the drain junction is reverse biased so that this current which comes from carrier generation in thetransition region, can beneglectedcompared with the electron currentin the channel when the device isturned on. Inthe off state, however, this is the residue current which flows in the drain and must be taken into account to calculate the stand-by power in switching applicat i o n ~ In . ~ the ~ surface-potential controlled tetrode mode of ope~ation,~() the drain junction, which is connected t o the emitter junction of the tetrode, is forward biased, andthe drain junction current is appreciable. In this case, the drainjunctioncurrentmay be added to the channel current t o give the total drain current. Following from (l),(2) and ( 5 ) )the drain current may be obtained by integrating the electron current density over the cross-sectional area of the channel. Using the coordinates shown in Fig. 2(d), this gives

j J d z , Y) dx

= -2

/ unE, dx

= -2

qbn(-dV/dy) dx

= pZ(dV/dy)

pnndx.

The integration is taken over the width of the channel x, which may be defined as the equipotential line given bythe condition u ( x c , y) = qVBD/kT, where V B o is the built-in or dausion potential of the drain junction. This l i e is shown in Figs. 4(f)-(h). In the calculations in (4) the following relationships are used: Jnl(z, y) = a , $ , , ca = qp,n, and E = -dV/dy. The electron mobility p, in (4) is generally less than that in the bulk due to the additional surface scattering from the atomic discontinuities and disorders atthe semiconductor-oxide interface. Aneffective mobility-in the surface space charge layer has been calculated by Schrieffer and Green, Frankl and Zemel. It is defined b Y
pn =
p,,n dz/[

n dz

(5)

and can be used in (4). The total electron concentration in the channel J n dz which appears in (5) may be related to the charge on the surface states Q S S and the charge on the metal gate electrode CoV, using the gauss theorem of flux from electrostatics. If the channel width is fairly uniform along its length (assumption (3)), the flux lines are all nearly perpendicular to the silicon-silicon oxide interface. This is known as the gradual channel approximation which has beenemployedbyShockley to analyze the characteristics of the junction-gate field effect transistors. In this approximation, the gauss theorem reduces to a simple one-dimensional form given by

Q~~

+ cove =

= -

Pax

=-q~m@+pl--n--D-N,fN,)dl:

(6)

where C, is the capacitance per unit area of the oxide layer under the metal gate electrode which has an oxide thickness o f zo and is given by

Co = Koeo/xo.

(7)

V ois the voltage drop across the oxide layer at a distance y from the source electrode and is given by

Vo(d =

- V(Y>.

($1

l* J. R. Schrieffer, Effective carrier mobility in surface-spacecharge layer, Phys. Rev., vol. 97, pp. 641-646; February, 1955. l@ R. F. Green, D. R. Frankl and J. Zemel, Surface transport in semiconductors, Phys. Rev., vol. 118, pp. 967-975; May, 1960. R. F. Green, ,yonlocal transport and cuspidal surface mobility in semiconductors, Phys. Rev., vol. 131, pp. 592-593; July, 1963.

1964

Sah: Characteristics of MOS Transistors

the

331

Thus, thetotal electron charge per unit area in channel, obtained from (6) using (8), is given by Q

he
/-

&sa

COW, - V ) -I-

&B

(9)

where Q B is the charge per unit area in the bulk defined by

QB

= -9

( N A

p - PA

n D

- N,) d~
s m n d Z (10)
I C

+qlpndzG -4Lm(NA-p)+y

which shows that the bulk charge is equal to the total depleted hole charge in the semiconductor due to the applied positive gate voltage. The approximation in (10) follo-mrs from assumption (4) for a structure with P-type substrate. The current equation given by (4) may be written as

I D = Z(dV/&/)Lco{ [(Qss &B)/~o]$ . V c - v(Y)) (11) using (5) and (9). This differential equation can be readily integrated along the channel if it is assumed that
the average surface mobility p,, the bulk charge Q B , and the surface state charge Q S s areall independent of position along the channel y. These follow directly from the gradual channel approximation made in assumption (3) which essentially states that u(x,y) h a(.) and from assumption 6) whichassumes that Q s s is a constant. The integration over y = 0 to L gives the following drain characteristics:
I D

bulk concentration of N A = 1015/~m3 (14 ohm-em). Thus, the net turn-off voltage for this N-channel MQS transistor is V T = -5 1.5 = -3.5 volts which shows that there is an N-type conducting channel induced by the positively charged donor surface states at zero gate voltage which requires a negative gate voltage of -3.5 volts to turnit off. The drain characteristics given by (12) is valid only for gradual channels and ceases t o be a good approximation in the region of the channel where it is pinched off or nearly pinched off. As the drain voltage J7D is increased and the gate voltage is kept at some value greater than V,, the drain current increases first linearly with V Dbut the increase slows down as the drain voltage is further increased and the channel narrows down at the drain as indicated in Fig. 4(f). This is evident from the family of drain characteristics shown in Fig. 5. At the maximum of the drain current given by (12) and shown in Fig. 5, the channel is pinched off at the drain junction as indicated in the energy surface diagram in Fig. 4(g). Beyond this drain voltage, the gradual channel approximation fails and (12) ceases to be valid. This condition corresponds approximately t o the condition of maximum draincurrentfrom (12) andmay beobtained from it. Setting ( a l ~ / a V , ) = ~~ 0 using (12), the pinch-off condition is

(14) which is the condition given by Fig. 4(g).Thedrain current at the pinch-off condition is given by

V D = VD,

V Q-

v,

(t%cO/Lz)[(VG - V,) V D

V2/2] (12)

where C, = C,ZL is the total capacitance of the oxide layerunder the gate electrode and V T is the turn-on pinch-off voltage given by (14), the pinch-off region voltage if it is positive or turn-o$ voltage if it is negative. lengthens into the channel from the drain as illustrated in Fig. 4(h). Most of the additional voltage applied t o This threshold voltage is defined by the drain beyond the pinch-off voltage, i.e., V , - VDs, V T = -(Qss QB)/CO. (13) appears across the length of the pinch-off region and It is evident from the result given in (12) that if results in verylittle increase of the drain current. A slight increase of the drain current does occur which is Qss B B < 0 , V , is the minimum gate voltage required since the length of the channel L to induce a surface channel and turn on the drain current evident from (15) which corresponds t o the enhancement mode of operation. must be replaced by the effective length of the channel 8. On the other hand, if Q S s Q B > 0, for example in a An accurate calculation of the length of the pinched-off device with a donor surface state of QSs > - Q B on a region is not possible inthe gradual channel approxiP-type substrate, then an electron channel exists even mation and will be covered in a future discussion. In region at V G = 0. I n this case, V T is then the minimum gate the present analysis, thedraincurrentinthe i l l be taken as the value given by (15) and voltage required to turn off the conduction path between V , > V D S w assumed to be independent of V D . This is also illustrated the drain and the source. I n silicon MOB transistors, usually the surface state in Fig. 5. Since the draincurrentfor V , > V,, is essentially contribution Q s s dominates over the bulk charge Q B in VT for a properly made device. For silicon-silicon constant or saturated to the value I D S , this current is oxide interface, the surface states are donor like with a known as the saturationcurrent and the subscript S is total concentration of approximately Q s s / q = 5 X used which denotes saturation. The corresponding drain 1011/cm2. The turn-off voltage from this contribution voltage at which the channel is pinched off is known as for an oxide thickness of z a = 2000 A with dielectric the saturation voltage. The dc characteristics of the MOS transistors are constant of K O = 4 is about -5 volts using (7) for the oxide capacitance. The contribution from the bulk charge, plotted in Figs. 5 and 6 from (12). It is evident from the drain characteristics, I D versus V Dshown in Fig. 5 that Q B given by (lo), is of the order of +1.5 volts for P-type

I,, = Cii,Co/2L2)(Vo - V T ) ~ = (@,Co/2L2)V:s. (15) I f the drain voltage is further increased beyond the

332

IEEE TRANSACTIONS ON ELECTRON DEVICES

July

50

40

30

20

10

-10

-20

3
10

12

Fig. 5-The

drain characterjstics of an N-channel MOS transistor.

10

surface-potential controlled transistor tetrode^,"^' the channel current may be represented by a drain-voltageindependent resistance whichis a function of the gate voltage. The transfer characteristics, ID versus V G with 8, as a parameter are shown in Fig. 6. They are straight lines below saturation when the channel is not pinched off and the gate voltage satisfies V , - V,> V D . The intercepts of these straight lines are given by V G - V T= VD/2. Between V , - V , = 0 and V , - V , = VD, the drain current follows the saturation current locus given by (15). The drain current iscompletely cut off when the gate voltage is equal to the pinch-off voltage or V, = 0. A rapid experimental determination of the threshold voltage V , can be obtained from the two terminal characteristics in which the gate electrode is connected either directly t o the drain for the enhancement mode Nchannel device which has V , > O and no built-in channel, or through a battery V G G > \ V T \ (positive side tied to the drain) which has a sufficientlyhigh voltage to pinch off the built-in channel for the depletion mode N-channel device. In these connections, the device is in the saturation regionsince V D= V , V G G > V D s= V G- V , thus, the two terminal drain current may be obtained from (15) using (14) and is

v,

I D S = (LCo/2L2). ( V D - VGG - V,12

(16)

which shows that the onset of the drain current corresponds to a drain voltage of ( V , V,,). For devices of the enhancement type, the turn-off voltage V , can bedetermined readily from a display of this characteristic without the use of agatebattery since V T < 0. For the depletion type V , > 0 and a gate battery of V G G > ( V T ( must be used to determine the turn-on voltage V,. This slight additional complication comes from the fact that an N-channel MOS transistor, which has a P-type substrate,cannot be biased with a large negative drain voltage since then the drain junction would be forward biased and the large forward drain junction current would mask off the pinch-off point.

Fig. 6-The

transfer characteristics of an N-channel MOS transistor.

the MOS transistor is very similar to the junction-gate fieldeffect transistor. The dashed line in this figure is the locus of I D Sgiven by (15) which separates the region g d = (aID/aV,>v. = (ACO/L~)(VG - V F - V D ) (17) of saturation from the nonsaturated or nonpinch-off region. A small portion of the drain characteristics in the third which decreases linearly with drain voltage and becomes ,quadrant V D < 0 is alsoshown in Fig. 5 whichcorrezero at saturation, V D= V D s= V G- V T . sponds to the drain junction forward biased. This does The transconductance is not include the forwardbiased drain junction current g m = ( a T D / a v G ) V ~ = @,cO/L2)VD (18) which may be appreciable compared with the channel current shown in Fig. 5. From this figure, it is evident and its maximum, which occurs at saturation, is given by that the channel current is nearly proportional to the g m s = @aCO/L2)VDS = (~wCO/L2)(VG drain voltage when the drain junction is forward biased. Thus,inthis mode of operation which occurs in the = d2ID6,pnCO/L2. (184

V. SMALL SIGNAL EQUIVALENT CIRCUIT PARAMETERS Some of the important low frequency circuit parameters can also be obtained from the drain characteristics of (12). For example, .the drain conductance below saturation is

v,)

1964

Xah: Characteristics of MOS Transistors

Y

333

-Y

which is identical t o the ratio gn/gd. At the point of saturation VG - V T = V D the voltage amplification factor diverges due to g d = 0. In actual devices, due to the channel length shortening effect beyond the saturation point, which was discussed in the preceding section, the drain conductance is finite in the saturation region, and hence the voltage amplification factor is also finite. Other smallsignal parameterscan alsobe obtained from the model just discussed. To calculate the short circuit gate and drain capacitances, the expression C = d Q / d V can be used. For the gate capacitance, the total chargeon themetal gate electrode at anygate and drain voltage may be obtained from
QG

Kod

JL

Eo(Y) dY

= ( ~ o ~ o z / ~ o )
d0

VO(Y) dy
(20)

"83
Fig. 7-The transconductance versus the drain voltage characteristics of an N-channel MOS transistor.

CoZ

[L
JO

[VG- V(y)I dy.

In thelast step of the calculation in (20), use is made o f (7) and (8). Thisintegralcan be evaluated explicitly using the draincurrent equation (11) t o relate dy t o d V and the result is

The short circuit gate capacitance is thus

C G

(aQO/aVG)V,

Co{l
=
2

- VO2/3[2(V, - VT) - VD]'! - (V,/V,,)"(lD,/rD)'/3].

(22)
(224

1
I
L)

I
6 v

- vT

10

12

A0

Fig. 8-The

transconductance versus the gate voltage characteristics of an N-channel MOS transistor.

Use is made of (14) and (15) in the last two steps in the calculation of (1%). The maximum transconductance given by (Ma) is also approximately the transconductance &Ch = -4.z n dx dy = -Q@ c0v, of the devicewhen it is operated beyond the saturation voltage, V D > V D s .The family of transconductance characteristics is plotted as a function of the drain voltage in Fig. 7 with the gate voltage as a parameter using (18) and (Ha). It is evident from this figure that where use is made of (9) and (13) for the x integral and (20) for the y integral. The short circuit drain capacitance below saturation V D < V D s the transconductance is proportional t o thedrain voltage but independent of is thus, the gate voltage. Beyond saturation V D > Vns the transconductance is independent of the drain voltage but is proportional to the gate voltage. A similar representation with the drain and the gate voltage interchanged is shown in Fig. 8. The voltage amplification factor of the device is

Similarly, the short circuit drain capacitance may be obtained from the change of the carrier charge stored inthe channel when thedrain voltage is varied.The charge stored inthe channel may be obtained either directly by integration of the electron concentration in the channel or by the use of the gauss 'theorem (6) in conjunction with the charge on the gate given by (21). Thus,

/ J

-(aVD/aVG)I,

vD/(vf2 - VZ' - VD)

(l9)

334

IEEE TRANSACTIONS ON ELECTRON DEVICES

These short circuit capacitances are graphed in Fig. 9 and Fig. 10 from (22) and (24) as a function of either the drain or the gate voltage with the other as a parameter. It is evident from these figures that the gate capacitance decreases from the oxide capacitance Co below saturation t o a constant value of 2c0/3 in the saturation region. Similarly, the drain capacitance drops from C0/2 to zero inthesaturation region. The vanishing drain capacitance in the saturation regioncomes from the fact that when the channel is pinched off at the drain, the electron charge stored in the channel becomes independent of the drain voltage. The charge stored in the channel Q C h is plotted from (22) in Fig. 1 1 which shows this constancy. From the draincurrentequation (12) and the total charge on the gate electrode (21) it is alsopossible to calculate the open circuit gate capacitance using the relationship CGa= (aQG/aV,),, and the result is

C,o/Ca

==

1-

{v, + 2[3(V, - V,) - V,]

- v2-1 - VDl
(25)
VT)

.(V,

vr - V,)(aV,/aV,),,J/3IIa(v,
- VT)/[Z(vG VD].

= 2(vG

In the last step of the calculation the voltage amplificationfactorfrom (19) is used. Theresult of the open circuit gate capacitance given by (25) is graphed in Fig. 12 as a function of the drain voltage and gate voltage using (25). The low frequency intrinsic equivaIent circuit pararneters of the MOS transistor can now be derived from the terminal conductances and capacitances just calculated. The general equivalentcircuit is shown in Fig. 13 for the channel. This is the intrinsic equivalent circuit which does not include the stray capacitances, the capacitance of the finite drain junction area which is not connected to the channel, the lead conductances and the spreading resistance. Thevarious capacitances and conductances inthe intrinsic equivalent circuit are readily derived from the results just, obtained. Thedrain conductance gd is evidently that given by(17) and the transconductance gmis given by (18). The determination of the three equivalent circuit capacitances, C,,, Cgdand Cd,, shown in Fig. 13 from the terminal capacitances requires slightly more additional analysis. The open circuit gate capacitance given by.(25) may be related to the equivalent circuit parameters shown in Fig. 13 by direct calculation. Straightforward circuit analysis of the equivalent circuit in Fig. 13 with thedrain electrode open gives the input admittance

Fig. 9-The short circuit gate and drain capacitance of an N-channel MOS transistor versus the drain voltage.

1 . 0

0 . 9

cc
CO

0.8

0.1

0 . 5

0.4

CD

F
0 . 3

0.2

0 . 1

The low frequency open circuit gatecapacitance be obtained from (26) by letting w -+ 0.
CGO

may
(27)
Fig. 10-The short circuit gate and drain capacitance of an N-channel MOS transistor versus the gate voltage.

c g s

cd(gm

gd)/gd-

1964

Sah: Characteristics 335 of MOS Transistors

0.666

i
co
8.500

0.500

I 2

v-v

I 8

I
10

12

G T

1
0

Fig. 14-The equivalent circuit gate tosource capacitance of an N-channel MOS transistor versus drain and gate voltages.
12

-2

I
0

I
2

I
0

I
8

I
10

Fig. ll-The total charge of the current carrier stored in the channel of an N-channel MOS transistor.

It is also immediately evident from the equivalent circuit in Fig. 13 that the short circuit terminal capacitances are related t o the equivalent circuit capacitances by
and

c,

c d s

$-

Cod.

(29)

Thus, the feedthrough capacitance between the gate and drain may be obtained by eliminating C,, from (27) and (28) and using (17) for g d and (18)for gmo The result is
cod/cO

13(VG -

vT)

VDl
(30)

*2(VG - V , - VD)/3[2(VG - V,) - V,I2

which is identicalto the expression for CDgiven by (24b). Thus, from (29) one concludes that
Cd,

(31)

which is also expected from the physical model. From this simple result, one can immediately obtain the gate t o source capacitance C,, from (28) using (30) for C,, and (23) for C,.
1 . 0

I
2

I
4 VG-VT

I
6

I
8

I
10

I
12

cu3/c0 = ( 2 / 3 ) w G- vT)
.[3(vG VT)

Fig. 12-The open circuit gate capacitance of an N-channel MOS transistor versus the drain and gatevoltages.

2VD]/[2(VG -

VT)

- VDl2

(32)

is plotted in Fig. 14 as a function of the drain voltage or gate voltage. The equivalent circuit capacitances in the saturation region areobtained by setting V D = V D , = V G- V , in (30) and (32) and are given by
Cuda

(33)

and
Cgss = 2C0/3.
Fig. 13-The small signal intrinsic equivalent circuit of an N-channel MOS transistor.

(34)

The result of (33) comes from the fact that in the saturation region, the channel is pinched off at the drain elec-

336

IBEE TRANSACTIONS ON ELECTRON DEVICES

July

trode so that there is no signal path between the gate and drain electrode directly except through the modulation of the channel width by the gate voltage inthe unpinched-off region which is accounted for by the transconductance. In small signal low frequency applications of the MOS transistors, the low frequency equivalent circuit shown in Fig. 13 is quite adequate. For high frequency applications, this equivalent circuit should be slightly modified by including a cutoff frequency in the transconductance expressiongiven by (18) inthe following form

where ,g , is the low frequency expression given by (18). The exact calculation of the cutoff frequency a , , is rather complicated and requires a small signal high frequency analysis of the MOS transistorstructure. A simple chargeanalysis can be made to provide an adequate estimate of ugm. This is done by considering the change of the output short circuit current in the drain when a small pulse of charge d Q G is added to the gate electrode. The time delay of the response in the drain current is of the order
tQ%

I .2

D
1 . 0

= I

0.8

(aQQ/D)JD

(36)

em d / i )
0.6

which may be rewritten as

to, =

(aQ,/avc>.,/(ar~/av,).,
=
(c08

(37)
(374

0.4
i

= c,/gmo

cQd)/gW&o

u
0.2
1

whereuse has been made of (18) for gmo and (21) and (28) for Gc. The cutoff frequency of the transconductance may be approximated by
mom A

LO
0

I
2

I
4

I
6
V

I
-VT
0

I
10

I
12

l / t m = gmo/cc = gmo/(C,s

+ c,3
VT) - v D I 2

(38)

(b)
Fig. 15-The transconductance cut-off time constant of an N-channe1 MOS transistor (a) versus the drainvoltageand (b) the
gate voltage.

[2(vG- v,) - VD]/{2[2(V,

- v:) (38a)
frequency associated with the load resistance. The midband gain is obtained by setting u = 0 in (39) and is

where use is made of (18), (28) and (22). The reciprocal of the transconductance cutoff frequency l / u g m= t,, is plotted in Figs. 15(a)-(b) versus drain and gate voltages respectively using (38) and (38a). Another useful figure of merit for the MOS transistor in small signal high frequency applications is the midband gain times bandwidth product with two or more devices cascaded. This figure of merit can be readily obtained from the equivalent circuit shown in Fig. 13 with a load conductance G and another MOS transistor stage connected t o the output terminals D and X. The voltage gain is

A,

- grnoIzL

(401

which is normally much greater than unity, i e . , R L > > for a useful amplifier.Thus, the cutoff frequency uL = R; associated with the load is considerably lower than the transconductance cutoff frequency u,, a gmo. Hence, the frequency at which the voltage gain drops b y $ db from the midband isgiven by wL andthe gain-bandwidth product is
2a (gain-bandwidth product) = AmuL
= =

gmo/(C,,

+ CdJ -

C,d)

gmo/(C,, -

C,d)

(41)

g d ) is the total effective load rewhere RL = 1/(G ed, - C u d )is the cutoff sistance and w L = l/RL(C,,

(3/2)(/&/L2)[2(VG - v T > - vD]* ( 4 1a) This figure of merit is almost identical t o the transconductance cutoff frequency given by (38). The differ-

1964

Sah: Characteristics of MOX Transistors

337

ence comes from the feedthrough capacitance which vanishes in the saturation region. In many circuit applications, the feedthrough capacitance is neutralized so that C,, does not appear in the above expression and the figure of merit becomes gm0/C,, instead of (41). In the saturation region, the transconductance cutoff frequency and the figure of merit are identical and are obtained by using V D = V D S= V G - V T in (38a) or (41a) t o yield
w,,,

Fig. 16-Switching

transients in a p-channel MOS transistor inverter circuit.

2~ (gain-bandwidth product)
= (Pn/2L2)(Vc - VT)
=

channel charging time is then

(42) (424
This time constantis also the transit timeof the electrons across the N-type channel for the case of constant electron mobility. This is easily demonstrated by the following calculations:
P
P

d@a/2COL2)IDS

where use is made of (15) for IDS. VI. SWITCHING TIMES For switching applications, such as in the inverter circuit shown in Fig. 16, the switching times consist of both time constant of charging and discharging the channel and time constant associated with the load resistance RL and the capacitance Ci which consists of the drain junction capacitance and the stray capacitance of the device header and can and associated circuit wiring. During the turn-on transient, the channel charging time constant dominates over RLC; while during the turn-off transient, RLC; dominates. Let us first consider the turn-on transient as illustrated in Fig. 16 for a P-channel device which has no built-in channel. The deviceis initially in the off state with a negative drain voltage - V D D and zero gate voltage. At t = 0, a negative gate voltage is applied which is sufficient to induce a hole channel and cause holes t o flow down the drain from the source and discharge the capacitance C; which is initially charged up to a charge of -CiVDD. I f the timeconstant RLC; is large compared with the time constant of the channel, the discharge time of C; is essentially the time constant of the channel since during thistime the build up of charge on C; by the load current flowing through RL from the battery V,, isnegligible. The channel time constant is an intrinsic property of a given device and depends on the device geometry and material properties. It may be calculated by assuming that the charge stored in the channel and the channel currentare given by the dc value at any instant of time during the turn-on transient. The total channel turn-on time in this quasi-equilibrium situation is then the sum of the differential time dt required to add a differential charge dQ t o the channel by the channel current I . The sum extends to the time when the channel charge reaches the final value Q C h and the channel current reaches the final value I,. The time dependence of I ( t ) is not known and for a rough approximation, it may be taken as a constant given by the final value at the end of the turn-on transient, ie., I ( t ) = ID. The turn-on or

I n the last two steps of the calculation in (43a), use is made of (4) for d V / d y and (23) for &Ch. The total electron charge in the channel given by (23) and (21) may be substituted into (43) t o give

At saturation, the charge stored in the channel is

and the channel time constant is

The charnel time constant beyond the saturation point may be estimated from (46). In this region, the effective channel length is decreased and as a result I D is increased above IDS. Thus, from (46) it is evident that the channel time constant decreases slightly as the drain voltage isincreasedbeyond V D s .The reciprocal of the channel time constant obtained in (46) is almost identical t o the transconductance cutoff frequency warns or 2~ times the gain-bandwidth product given by (42a), except for a numerical factor of 4. The electron transit time or the charging and discharging time of the channel is graphed in Figs. 17(a)-(b) as a function of the drain and gate voltage, respectively, using the expression given by (44). Let us nowconsider a numerical example to get an indication of the contributions from various sources on the switching time of the turn-on transient. For a P-

338

IEEE TRANSACTIONS ON ELECTRON DEVICES

July

P
-2

I
0
2

I
6

I
v

I
10

12

(a)

The relative importance of the circuit and channel time constants is reversed during the turn-off transient. Let us assume that the turn-off transient starts at some time t, as illustrated in Fig. 16. At t,, the gate voltage returns t o zero and the channel is turned off with the channel time constant of 880 picosec for the numerical example just given. However, the drain voltage transient ud(t) decreases much moreslowly towards -VDD since the capacitance C : must be charged up to -VDDthrough RL. Thus, the turn-off timeconstant is approximately RLCl, = 5000 picosec. If the circuit time constant is comparable to the channel time constant, the total switch-off time constant would then be approximately given by the SUM of the two time constants. 0 I I I I I I I s G T 10 12 Thetotal switching time (turn-on plus turn-off) is then limited by the circuit rather than the device. This Fig. 17-The channel charge storage time constant versus (a) the slow down by the circuit capacitance loading also occurs drain voltage and (b) gate voltage of an N-channel MOS tran- in a complementary inverter circuit shown in Fig. 18 sistor. This channel timeconstant is also the electron transit whichemploys a complementary pair of enhancement time from the source to the drain. mode MOS t r a n s i s t o r ~ .Such ~ ~ a circuit has essentially
= 1
Y

Ii I\
1 . 2

channel MOB transistor switch, the following numerical values are typical: channel length L = 10 microns, channel width 2 = 250 microns, bulk resistivity = 10 ohm-emscorresponding t o a donor impurity concentration of 4 X lo1* atoms/cxn3, average surface mobility of holes p9 = 100 cm'/volt-see, oxide thickness x . = 1000 A, and oxide capacitance Co = KoeoZL/x, = 0.885 pf. Assuming that thedevice is switchedon by a gate voltage to a steady state drain current in the saturation region of I D = IDS = 10 ma, then the saturation drain voltage calculated using(15) is VDs = 6.9 volts. The charging time constant of the channel is then 880 X 10-l'see using (46). I f such a device is operated in a small signal circuit at this current level in the saturation region, the gain-bandwidth product from (41a) is 160 Me. Let us next estimate the time constant RLC; taking a load resistance of RL 1000 ohms. For this example, let us assume that the diffused drain junction is shallow and essentially a P'N junction with a capacitance of 15 pf/mm' at a reverse bias of V , = -20 v. The drain junction is assumed to have a length of 25 microns and its area is then 25 x 250 x lo-' em'. The total drain junction capacitance is then CD = 0.094 pf. The drain lead going through the package has a capacitance of the order of 0.5 pf for a TO-5 transistor header. Thus, the main contribution of ( 7 ; is the stray circuit capacitance which may be as high as 5 pf or more. Taking this number as an estimate for Cl,, the circuit time constant is RLC; = 5000X see which is considerably greater than the channel time constant of 880 X 10-l' sec. Thus, the turn-on transienthas a time constant given essentially by the channel timeconstant of 880 picosec. I f the circuit time constant is considerablyreduced by eliminating the stray capacitance, then the turn-on timeconstant. is approximately given by
5

it0

f'CA(RLCL)/[tCA

+ BLc;].

1964

#ah: Characteristics of MOA Transistors

339

are shown in Figs. 19(a)-(d) and for a N-channel device in Figs. 20(a)-(d). These characteristics are recorded directly using an X-Y recorder. I n Fig. 19(a),the drain current and the calculated from experimental curves are shown. Linear dependence of on the gate voltage is observed in the figure over a wide range of gate voltage which is in excellent agreement with the theory given by (15). The departure from linearity at large gate voltages indicated in Fig. 19(a) comes mainly from the fact that the channel potential wellbecomes deeper (see Fig. 4(h))and the electrons are more concentrated near the silicon-oxide interface. Thus, electrons suffer more surface scattering and the electron mobility decreases. In addition, there Fig. 18-Complementary inverter circuit using a P-channel and an is also a considerable temperature rise in the pinch-off N-channel MOS transistor. region due to the power dissipation at large gateand drain voltages. This is of the order of 500 milliwatts as indicated in Fig. 19(a). For the TO-5 can, the thermal zero standby power due to the power dissipation from resistance is of the order of 75"C/watt from the junction the reverse biased drain junction leakage current, making to the can for regular junction transistor such as 2N696. it particularly attractive in nanowatt logic circuit applications. In these and other switching circuits, the princi- Although the geometry is considerably different here for ple speed limitation from the stray circuit wiring capaci- a MOS transistor where the pinch-off region is probably tance may be largely overcome using integrated circuit heated to a much higher temperature due t o higher techniques to limit the size of the drain junction area power density, the drain current is mainly controlled by the non-pinch-off region for this long channel device and the interconnection where the gradual channel approximation is valid. Thus, VII. COMPARISON OF THE ELEMENTARY THEORY the temperature dependence of 1 , comes mainly from WITH EXPERIMENTS the channel outside of the pinch-off regionwhere the temperature rise at 500 Mw is approximately 75'C/watt I n this section, the elementary physical theoryjust f the temperature presented and the characteristics calculated from it are giving a temperature rise of 37.5"C. I critically compared with experimental data taken on dependence of the mobility is taken to be T-3/2then a the circular device structure. The surprisingly good 15 per cent mobility drop will result which accounts for observed in Fig. 19(a). general agreement of the theory with experiments and almost the entire drop in From the intercept of the line in the vs V Gplot some of its inadequacies will be discussed in detail and it willbe the basis of an improved analysis t o be pre- with the ID, = 0 axis, the threshold voltage may be obtained and is V T 5 - 12.2 volts as indicated in thefigure. sented in a subsequent paper. The agreement between the ideal theory and the For an experimental test of the simple t<heory, we shall measurement on the transconductance is less satisemploy both the enhancement-mode P-channel and the depletion-mode N-channel silicon MOS transistors of factoryas one can observe in Figs. 19(b)-(c). In Fig. the circular geometry shown in Figs. 2(a)-(c). The di- 19(b), the theoretical curves are drawn in as heavy l i e s using(18) and (19). The evidence of mobility decrease mensions are:drain diameter d = 310microns,source diameter s = 450 microns, channel length L = 70 microns, due to surface scatteringand heating is again evident gate electrode width L , = 127 microns, drain and source at high gate voltage. The slope of the saturation transcontactjunctiondepth xN+ = 3 microns. From these conductance line dgms/dVcmay be evaluated near gms= 0 dimensions, it is evident that the circular geometry can and its intercept again gives -12.2 volts for the threshbe accurately approximated by the linear geometry old voltage. It is evident in Fig. 19(b) that the agreement is poor shown in Fig. 2(d) with the effective width of the gate between theory and experiment in the nonpinch-off electrode given by 2 = a ( d s)/2 = 1200 microns. Thetotal gatearea is then A , = Z L = 1.53 x IO5 region. The transconductance rises above that predicted and has a maximum near the microns2 and the active gatearea over the channel is by the simple theory saturationgate voltage. A similar disagreement isalso A , = ZL = 8.4 X lo4 microns'. The experimental data are obtained for the following indicated in the g, vs V , plot in Fig. 19(c) which occurs characteristics: I D versus V , with V , asa parameter, in the region where g, is proportional to V,. I n the ideal not drawn into Fig. gmversus V Gwith V , as a parameter, g, versus V , with theory shown in Fig. 7,whichis V , as a parameter, and CGversus V , with V , as aparam- 19(c), to avoidconfusion the g, lines corresponding t o eter. Typical set of characteristics for a P-channel device various values of ViCdo not cross each other. The dis-

+"DEI

dz

' I
1

340

IEEE T R A N S A C T I O N S ON ELECTRON DEVICES

(dl
Fig. 19-The experimental characteristics of a circnlar P-channel silicon-silicon oxide MOS t,ransistor. (a) The Gransfer characteristics. (b) The transconductance versus the gate voltage. ( e ) The transconductance versus the drain voltage. (d) The short circuit gate capacitance versus the gate voltage.

1964

Sah: Characteristics of MOS Transistors

341

(dl Fig. 20-The experimental characteristics of a circular N-channel silicon-silicon oxide MOS transistor. (a) The transfer characteristics. (b) The transconductance versus the gate voltage. ( e ) The transconductance versus the drain voltage. (d) The short circuit gate capacitance versus the gate voltage.

342

IEEE TRANSACTIONS ON ELECTRON DEVICES

July

crepancy observed here is due in part to the assumption that theeffective carrier mobility given by (5), the surface charge Q s s , and the bulk charge Q B given by (10) are all independent of the gate voltage or the surface electrostatic potential. It is possible from the transfer characteristics given in Figs. 19(a)-(c) t o obtain an effective carrier mobility in the channel defined in (5). In order t o make this calculation from these experimental data, the oxide capacitance over the channel surface area of the gate electrode must be known. This can be obtained from the geometry given for these devices and thetotal gate capacitance CG measured when the surface is strongly degenerate so that it corresponds tothetotal oxide capacitance of the gate electrode COTotel for the entire gate area A, = ZL,. The measurement of the gate capacitance under degenerate surface condition may be obtained from the short circuit gate capacitance data shown in Fig. 19(d) where the can capacitance of 0.6 pf has already been substrated. The total gate capacitance corresponds to the maximum plateau value at large negative or positive gate voltage and is COTotal = 19.6 pf. The oxide thickness may be calculated from COT = Ko~OAII/xO using K O = 4.0 for the silicon oxide and A, = Z L , = 1.53 X 10 microns just obtained from the device geometry. Thus, x. microns.
= =

Ko~,A,/C0 Total 0.276

{5.42/[c0..t,l(pf)])(microns)

The gate capacitance over the active channel area is then

C,

CoT(A,/A,)

0.55 C o T o t s l

10.8 pf (48)

using the value of the gate areas calculated at the beginning of this section from the device geometry. The effective mobility can now be calculated using the slope of the g m versus V o curve in the saturation region dgms/dV, given in Fig. 19(b) or the slope d a / d V G in Fig. 19(a)and the ideal theory given by (15) and (19). The effective mobility is
p
=

The comparison of the short circuit input gate capacitance calculated from the simple theory shown in Fig. 10 and the experimental data given in Fig. 19(d) is considerably less satisfactory. It is evident from the expected capacitance drop of C0/3 = 3.6 pf from the ideal theory which is labeled in Fig. 19(d) that the ideal theory has neglectedsome capacitance contributions to the short circuit gate capacitance. The discrepancy comes again mainly from the contribution from the dependence of the bulk charge Q B and the surface state charge Q s s on the gate voltage which is neglected in the ideal theory. A similar analysis can be made tothe N-channel MOST whose experimental data are shown in Figs. 2O(a)-(d). The conclusions can again be made that the theoretical quadratic dependence of the saturation drain voltage I D s on the gate voltage is well followed experimentally and similar discrepancies exist between theory and experiments in the transconductance and gate capacitance characteristics. The analysis of the experimental data of these two devices together with many other MOS transistors of the same geometry but fabricated with differentoxide thickness, bulk impurity concentration and surface state concentration are listed in Table I. Each of the devices listed in Table I represents a typical unit of a group of about ten devices made by a given process. All columns are measured values or calculated from measured data. The column of the effective bulk charge, with a concentration NB, is calculated by assuming that the threshold voltage corresponds t o the voltage at the minimum capacitance of a MOS capacitor of the same oxide thickness and bulk concentration. This voltage denoted by V,, is plotted in Fig. 21 using the wellknown MOS capacitance analysis.2o The corresponding bulk charge, N, (number per unit area) is obtained from Q B = qNB = CoVBand is graphed in Fig. 22. The density of the surface states Nss is then evaluated from the calculated bulk charge and the observed threshold voltage V T using

( 2 L z / c O ) ( a 6 / v G ) t D = (L/~O)(agmS/v,)~D
/ a V G ) ; =

= 36.4 ~ o ( G a
=

18.2(dgm,/dvG)V~ cm2/volt-sec

(49)

where the oxide thickness is in microns, the drain current in milliamperes and the transconductance per gate voltage in micromhosper volt. For the P-channel device shown in Fig.19 the experimentally obtained effective surface mobility for holes in the channel is then p, = 115 crn2/volt-sec. This is about four times less thanthe mobility of holes in the bulk of the N-type silicon sub2O D. R. Frankl, Some effects of materialparameters on the strate whichis 6.0 ohm-ern and has a donor impurity design of surface space charge varactors, Solid State Electronics, concentration N o f D = 8.2 X 1014/cm3 giving a bulk vol. 2, pp. 71-76; January, 1961. Data in Fig. 21 is obtained from unpublished calculations made by A. S.Grove and C . T. Sah. mobility of approximately 470 cm/volt-see.

where the positive sign is for the N-channel device while the negative sign is for the P-channel device. The donor type surface state density isshown in the last column in Table I indicating surface state concentration in the range of 3 to 10 X 1011/cm2. It is also interesting to note from the experimental data in Table I that the effective mobility of the carriers in the surface channel is generally about 100 cm/volt-sec for holes and 500 cm2/volt-sec for electrons.

1964

Sah: Characteristics of MOS Transistors TABLE I

Som EXPERIMENTAL CHARACTERISTICS OF THE CIRCULAR OS
TRANSISTORS Substrate Resistit Scm Concent cm-3 8.2 X 1.3 X 1.3 x 1.3 x 4.6 x 4.6 X 4.6 x 4.6 x 1.2x 1.2 x 1014 10l6 1015 1015
COT

343

Run No.
630417-4 631010-3 631010A-2 631010B-2 631011-1 6310118-6 631011B-4 631011C-3 6310143 631014D-4

x0

P Pf -

_____

P N

N
N P N
P P P

6.0 10.5 10.5 10.5 10.5 10.5 10.5 10.5 10.8 10.8

19.6 24.0 25.9 12.4 1014 28.6 1014 28.3 1014 29.0 1014 15.0 106 6.72 1015 22.7

0.276 10.8 -12.2 -3.25 0.226 13.2 -2.45 0.210 14.2 0.438 6.82 -4.30 -4.56 0.190 15.7 -9.00 0.192 15.6 15.9 -4.8 0.20 8.25 -8.79 0.36 -23.0 3.69 0.81 12.5 -5.30 0.24

23 125 233 80 56 27 56 21 18 59

1 . 2 x 10 9.76 X 1.52 3.13 2.55 1.6 3.4 2.18 1.25 5.32 0.89 10.42 0.89 5.65 0.89

lo1

8 . 5 X 10 4.6 4.1 3.4 9.6 4.7

M
0

volts

2-z

k
t1
0

1010
0 . :

I
.2

I
.6

I
.8

.4
x

1 . 0

micron

Fig. 21-The contribution to the threshold voltage from the bulk impurity dopingversus the oxide thickness in a silicon-silicon oxide MOS transistor.

Fig. 22-The total effective bulk impurity concentration per unit area QB = C,VB versus the oxide thickness of a silicon-silicon oxide MOS transistor.

VIII. CONCLUSIONS From the critical comparison of the experimental dataandthe characteristics calculated from the elementary theory, it appears that the dependence of the surface state charge, the bulk charge, andthe surface mobility on the gate voltage or the surface potential well depth must be taken into account in the calculation of the differential characteristics of the device, expeciaIly in the regionbelow saturation. In addition, since the electric field parallel to thesurface is of the order of V J L , hot electron effect may be important. I f the fielddependence of the surface mobility is assumed t o be proportional to (electric field)-/2 as in the case for hot elec-

trons in a bulk sample12the drain current would be given b Y

1 , =

(PLoC0/L2)[a

/ 3 1

.[(V, - V,) - (V, -

v, - vD)3]1/2

where E. is the critical electric field and is of the order of a few hundred volts per em. Then the drain saturaW. Shockley, Hot electrons in germanium and Ohms law, Bell Sys. Tech. J., vol. 30, pp. 990-1034; October, 1951. The analysis of the MOS transistor characteristics follows the procedure used in the text and is similar t o the case of the junction-gate field effect transistor analysis made by Dacey and Ross in G. C. Dacey and I. M. Ross, The field-effect transistor, Bell Sys. Tech. J., vol. 34, pp. 1149-1189; November, 1955, who included thehot electron effect.

344

IEEE TRANSACTION# ON ELECTRON DEVICES

July

the dielectric constant of the oxide the dielectric contant of the semiconductor k the Boltzmann constant L = the length of the channel L C = the length or width of the gate metal electrode N , = the acceptor impurity concentration (no./cm) N D = the donor impurity concentration (no./cm3) n = the electron concentration (no./cm3) ni = the carrier concentration of an intrinsic specimen (no./cm3) LISTOF SYMBOLS p = the hole concentration (no./cm3) voltage gain QB = thetotal effective bulk charge densityperunit gate area over the channel, A , = Z L area &B = COVB total gate metal electrode area, A, = ZL, QCh = the total charge (coulombs) stored in the channel midband voltage gain per unit area short circuit output or drain capacitance QChS = QChin saturation drainto source equivalent circuit capacitance Q G = thetotal charge (coulombs) stored on thegate (zero) electrode per unit area short circuit input or gate capacitance Q s s = the surface state charge density perunitarea open circuit input or gate capacitance E , = thetotal effective load resistance connected bethe equivalent circuit gate to drain feedthrough tween the drainand source electrodes, ar. = capacitance l/iG 4 g d ) = the inner diameter of the annular source island Cudinsaturation, i.e., V , > V D s = VG - V,, s (zero) in the circular geometry the equivalent circuit gate to source capacitance T = the temperature of the sample in O K tCh = the charge storage time in the channel C,, in saturation the capacitance corresponding to the oxide layer t C h 8 = tChin the saturation region over the channel area A,, 6, = K O ~ O A c / ~ O t$m = the transconductance cutoff time constant, t,, = the capacitance corresponding to the oxide layer 1/G?n under the entire gate metal electrode, C, = tgms = t,, in the saturation region tL7 = the carrier transittimefromthe source tothe I C W L / X O drain electrode in the channel ColA, = Ko~o/xc diameter of the dmin island of the circular t t , in the saturationregion the normalized electrostatic potential, u = geometry energy level a t the bottom of the conduction -Ei/kT = &/kT the normalized quasi-Fermi potential of elecband edge the equilibrium Fermi energy level trons, U = , p+JkT = -F,/kT the normalized quasi-Fermi potential of holes, the width of the energy gap a t a given temperaU, p+,/kT -F J k T ture involt the intrinsic Fermi energy level, E , = --Q# the contribution to the threshold voltage from the bulk impurity doping the energy level at the top of the valence band the dc drain to source voltage edge the dc potential a t a distance y from the source the quasi-Fermi energy level of electrons electrode measured relative tothe source pothe Fermi energy level of electrons in the metal tential, V(y) = 4, - + p the quasi-Femi energy level of holes the load conductance connected between the the normalized V ( y ) ,v(y) = qV(y)/lcT = u, u , and drain source V D S = the dc drain to source voltage a t saturation, = VG - v P ga = theshort circuit drain conductance gds = gd in saturation (zero) = the small signal ac drain to source voltage g, = the transconductance V G = the dc gate to source voltage gms = the transconductance in the saturation region V G G= the dc battery voltage applied between the gate and the drain electrodes ID = dc current flowing into the drain electrode I D S = I Dsaturation in the region = the small signal ac gate tosource voltages differencebetween the source J,, = the electron current density per unit area along V , = thedcpotential and the pinch-off point nearest to the source in the channel the channel 2% For common source connection, externd circuit voltages are v o = the de potential across the oxide a t a distance denoted by a single subscript of the electrode and the subscript y from the source electrode s or X denotes the quantlty in the saturatlon reglon.
= = =

tion current would have a (V, - VT)32instead of ( V , - V,) dependence. This contradicts the experimental data which shows a parabolic dependence over a wide range of current for these devices which have a rather long channel. However, for high frequency and high speed devices which have very short channel length, the hot electron effect should become important and may dominate the saturation characteristics.

KO K,

v,

v,,

v,

TRANSACTIONS IEEE

ON ELECTRON DEVICES
U,

345

the built-in potential across the oxide at equilibrium the threshold gate voltage toturn on or turn off a channel the width of the transition layer of the drain junction the depth of the N + drain and source islands the thickness of the oxide over the channel the distance measured perpendicular t o the oxidesemiconductor interface the distance from the source measured parallel t o the oxide-semiconductor interface along the direction of the channel width of the device with the linear geometry shown in Fig. 2(d) permissitivity of free space, 8.85 X farad/cm mobility of the electrons in the channel, cm2/volt-sec. effective mobility of electrons in the channel effective mobility of the current carriers in the channel resistivity of the substrate in ohm-cms

dr
+M

5 conductivity due t o electrons, U, = qpnn = the equilibrium Fermi potential, + p = -Er/q = the electron work function of the metal of the

4n

+ ,
X

=
=

fi
fia

=
=

w = warn 5 uUm8 = wL =

gate electrode the quasi-Fermi potential of electrons, += = -F,/q the quasi-Fermi potential of holes, 9 , = -F,/q the electron aEnityinthe semiconductor the electrostatic potential, fi = -EJq the electrostatic potential a t the oxide-semiconductor interface the angular frequency the transconductance angular cutoff frequency warnin the saturation region the angular cutoff frequency due to the load resistance R,. ACKNOWLEDGMENT

The authoris indebted to V. H. Grinich, C. A. Bittmann and A. X. Grove for many helpful suggestions on the manuscript and to 0. Leistiko and D. A. Tremere for device fabrication assistances. The author is also grateful to Prof. J. Bardeen for comments and Dr. G. E. Moore for permission t o publish this paper.

Frequency Dependence o f the Reverse-Biased Capacitance of Gold-Doped SiliconP+N Step Junctions

Summary-The experimentally observed frequency dependences of the reverse-biased capacitance of gold-doped silicon step junctions over the frequency range from 10 cps to 30 Mc are found to be in agreement with a simple physical model which takes into account the charge condition andthe charging and discharging time constantof the deep-gold acceptor level in the transitionregion of the junction. Analysis based on the simple physical model provides explicit theoretical formulas for the junction capacitance at low- and high-frequency limits which show that the high-frequency capacitance underreversebias is approximately proportional to .\/ND - NA, and is considerably reduced below the low frequency ordc capacitance if thedonorsarenearly compensatedby the gold. The frequency effect is important for deep energy level impurities and becomes negligible if the impurity level is at or near the bandedges. The presence of gold, however, has negligible effect on the avalanche breakdown voltage if NA%< NO.

HE REVERSE-BIASED junction capacitance of

a P'N junction has been generally observed t o follow closely the theoretical relationship of the depletion approximation [l], [2] (see also Fig 1 for Ci2 data)

c o = /Wo =

dPEND/2(VD - V).

(1)

Manuscript received January 29, 1964; revised March 24, 1964. C. T. Sah is with the Department of Electrical Engineering and of Physics, University of Illinois, Urbana, Ill. V. G. K. Red& is with Fairchild Semiconductor Research and Development Laboratory, Pa10 Alto, Calif.

In this case, the capacitance is independent of the signal frequency of measurement. However, in high speed silicon diodes which contain high concentrations of gold impurity for reducing the minority carrier lifetime and the switching time, it has been found that the capacitance is highly frequency dependent not only at low forward bias where the diffusion capacitance is unimportant [2] but also at moderately large reverse bias in contradiction t o the simple theory given by (1). This experimental observation is demonEtrated in Fig. 1 in which the capacitance-voltage curves at 10 cps, 100 cps, 1000 cps, 10 kc, 50 kc, 100 kc and 30 M c are shown for a gold-doped and a nongold-doped P'N step junction of