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TLM-2.0 in Action: An
Example-based Approach to
Transaction-level Modeling
and the New World of Model
Interoperability
CONTENTS
Functional
RTL
Model
write(address,data)
RTL Functional
Model
Fast
RTL
Hardware verification
Test bench
VHDL, Verilog for design
Easy integration
CONTENTS
FUNCTIONAL VIEW
Algorithm developer
Untimed
VERIFICATION VIEW
Functional verification
Untimed through Cycle Accurate
RTL Implementation
Software Software
Bridge
Memory Custom
I/O RAM DMA D/A
interface peripheral
Copyright © 2007-2009 by Open SystemC Initiative and Doulos. All rights reserved. 10
Virtual Platform Characteristics 2
Transaction
+ timing
VHDL
ISS
Verilog
CONTENTS
• Based on SystemC
comparable to ISS
Copyright © 2007-2009 by Open SystemC Initiative and Doulos. All rights reserved. 15
Coding Styles and Mechanisms
Use cases
Software Software Architectural Hardware
development performance analysis verification
Loosely-timed
Approximately-timed
Copyright © 2007-2009 by Open SystemC Initiative and Doulos. All rights reserved. 16
Coding Styles
• Only sufficient timing detail to boot O/S and run multi-core systems
• Processes can run ahead of simulation time (temporal decoupling)
• Each transaction completes in one function call
• Uses direct memory interface (DMI)
Copyright © 2007-2009 by Open SystemC Initiative and Doulos. All rights reserved. 17
Interoperability Layer
1. Core interfaces
and sockets
Initiator Target
Command BEGIN_REQ
Address
Data END_REQ
Byte enables
Response status
BEGIN_RESP
Extensions
END_RESP
Copyright © 2007-2009 by Open SystemC Initiative and Doulos. All rights reserved. 18
Example – Initiator & Target Sockets
struct Initiator: sc_module
{
tlm_utils::simple_initiator_socket<Initiator> socket; Default: 32-bits wide, base protocol
SC_CTOR(Target) : socket("socket")
{
socket.register_b_transport (this, &Target::b_transport);
}
virtual void b_transport( tlm::tlm_generic_payload& trans, sc_time& delay );
...
};
Blocking
Sockets
transport
Copyright © 2007-2009 by Doulos. All rights reserved. 19
Example – Socket Binding
SC_CTOR(Top)
{
initiator = new Initiator ("initiator");
target = new Target ("target");
initiator->socket.bind( target->socket );
}
};
Sockets
Copyright © 2007-2009 by Doulos. All rights reserved. 20
Example - Initiator
void thread_process() {
tlm::tlm_generic_payload* trans;
sc_time delay;
...
trans = m_mm.allocate(); Get transaction object from pool
trans->acquire();
if ( trans->get_response_status() <= 0 )
SC_REPORT_ERROR("TLM-2", trans->get_response_string().c_str());
Forward Forward
path path
Initiator Target
Interconnect
Backward component Backward
path 0, 1 or many path
Transaction
object
Interface methods
Initiator Target
socket Forward path socket
b_transport ()
nb_transport_fw()
Initiator Target
get_direct_mem_ptr()
transport_dbg()
Backward path
nb_transport_bw()
invalidate_direct_mem_ptr()
• Sockets group interfaces, bind both paths with one call, and are strongly typed
Copyright © 2007-2009 by Open SystemC Initiative and Doulos. All rights reserved. 24
TLM Introduction
CONTENTS
Interoperability
layer
Initiator Target
Coding Style
Loosely- or Approximately-timed
Core interfaces
Sockets Utilities
Convenience sockets
Generic payload
Quantum keeper (LT)
Base protocol
Payload event queues (AT)
Instance-specific extensions (GP)
Ticks
Cycle-accurate
simulation
Quantum Quantum
Temporally
decoupled
simulation
0 10 20 30 40 50
Process 1
Annotated delays
Process 2
Process 3
socket.register_b_transport
LT Initiator
b_transport
LT Target
Interconnect b_transport
AT Initiator
nb_transport_fw
nb_/b_transport
adaptor
Generic
payload
Copyright © 2007-2009 by Open SystemC Initiative and Doulos. All rights reserved. 30
Extensions
Generic Generic
Payload Payload
Extension Extension
Initiator Target
Base
Protocol
Router
Initiator Interconnect Target
• Extended phases
33
Levels of Use
2. Write LT components
3. Write AT components
34