Transactions on Computer Science and Technology December 2013, Volume 2, Issue 4, PP.

55-61

Network on Chip-based Fault Tolerant Routing Algorithm and Its Implementation*

Shuyan Jiang, Shanshan Jiang, Peng Liu, Yue Liu, He Cheng
School of Automation Engineering, University of Electronic Science & Technology of China, Chengdu, Sichuan, China
Email:

542767381@qq.com

Abstract
In this paper, a new fault-tolerant routing algorithm is presented in order to effectively improve the fault-tolerant performance of NoC. Based on a classical XY dimension routing algorithm, this design realizes a fault-tolerant routing algorithm of a single routing error by increasing its adaptability, and maintains the advantages of the XY routing algorithm, such as simpleness, hardware overhead, and scalability. Then a 3*3 structure of 2D-mesh Noc is simulated in ISE Design Suit 14.1 platform. Experiment results show that the proposed fault-tolerant routing algorithm proposed can complete the functions of routing data forwarding and tolerance of a single fault on NoC. Keywords: Network on Chip; Fault-tolerant; Routing Algorithm; Topology

1 INTRODUCTION
With the deep sub-micron VLSI technology maturity and further development, the chip design industry is facing a new serious problem: With the advance of chip function and performance requirements, the growing chip size and the increasing operating frequency result into the longer development cycle, the increasing difficulty in guaranteeing design quality, and higher design costs.These requirements make bus structure as the main feature of the SoC design methodology increasingly difficult to meet the requirements, mainly in: the system scalability challenges, difficulties in a single clock synchronization, design efficiency and growth of scissors chip integration issues. For these reasons, in 1999, a new integrated circuit architecture-Network On Chip, NoC, was proposed. the core idea is migrating the computer network technology to chip design, thus completely solving problems of bus architecture [1] from the architecture . Electrical characteristics of on-chip System from its own device make the failure possibility of the transmission process greatly increased, transmission failure will make the network action error, causing the entire system unusable; also make the existing routing solution without deadlock and livelock become invalid; or it may make the system repeatedly act on the problem areas, the system power consumption is greatly improved. Seen the quality of service provided by the chip on network, the transmission reliability is one of the most important aspects. To avoid the above problems, it requires NoC has strong ability of fault tolerance. Therefore, fault tolerant technology can be one of the important supported technologies of successful application for a network. Currently, routing algorithm Network on Chip is divided into two categories, including adaptive routing algorithm and deterministic routing algorithm. the latter is simple,but the fault-tolerant performance is in general, adaptive routing algorithm is theoretically good performance, but consumes a lot of on-chip resources and will bring power [9] problem .

A. Adaptive Fault-tolerant Routing Algorithm

The so-called adaptive routing, refers to the packet routing path not only considering the starting address and the address information, but also considering the state of the network. The advantage of adaptive routing is the use of
*

This work was supported by the Program of National Nature Science Foundation of China under Grant No. 41301460 and 60934002, the Major Program of National High-Tech Research and Development Project of China under Grant No. G0701070111AA0102017, and the Application Fundamental Research Funds of Department of Science and technology of Sichuai Province under Grant No.13JC0504. - 55 http://www.ivypub.org/cst

adaptive routing path, avoiding network congestion, you can get higher network bandwidth saturation value; But routing logic is more complex, overhead is large in the case of low network congestion, and there is also deadlock.

B. Deterministic Fault-tolerant Routing Algorithm

The path routing of deterministic routing algorithm is only related to the starting address and destination address, given the start and end address, routing path is to be determined, and has nothing to do with the current network status. In determining the route, the use of the most is the Dimension-Ordered Routing, because it is very simple and easy to implement routing logic. In the dimension order routing, each data packet once passed on only in one dimension, after arriving in the appropriate coordinate in this dimension, passed on in another dimension from low- dimensional to high-dimensional order. The packet is strictly in accordance with the order of a single dimension of change within the network transmission, so there is no deadlock in dimension order routing. An XY 2D-mesh routing is one of them, its routing process is: firstly, the packet is sent to the destination node where the column in the X direction, and then along the Y direction the letter sent to the destination node where the packet line, as shown in figure 1. Specific processes dont elaborate.

FIG. 1 XY ROUTING PROCESS

In this paper, however, much the premise of increased hardware overhead, we propose a new fault-tolerant routing [2] algorithm. This fault-tolerant routing algorithm is based on the design of 2D-mesh network topology , for this network topology, a practical fault-tolerant routing algorithm must meet the following characteristics: low power, versatility, scalability, no deadlock and sequential transmission, in order to meet above requirements, this article chooses a classical deterministic routing algorithm-XY routing algorithm, based on it, appropriately enhancing its self-adaptive when meeting point of failure, in order to achieve the purpose of fault- tolerant .

2 Y-PRIORITY FAULT-TOLERANT ROUTING ALGORITHM

Based on the classical XY dimension order routing algorithm, This paper presents a new fault-tolerant routing algorithm, appropriately increase its adaptability, thus achieving a tolerance with a single routing error, while maintaining the good benefits of the XY routing algorithm, such as simpleness, small hardware overhead, scalability; while also avoiding deadlock on the basis of the adaptive routing. In the 2D-mesh network topology single routing error occurres, the error routing the situation around: shown in Figure 2, in a 2D-mesh network topology, each node (X, Y) has four direct neighbors (N, S, W, E) and four indirect neighbors (NE, NW, SE, SW). The eight nodes are called the node neighbors. When a single routing error occurs, neighbors of the error router divided the network into two parts: the normal section and the ineffective portion.

FIG. 2 SINGLE ROUTE ERROR

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For a size of M N of 2D-mesh network, there are M N kinds of possibilities of the error location of the node. Therefore, different from the location of the error, the error region can be divided into 9 categories: occurred in four angles of network errors each accounted for 1, occurred in the four boundaries of network errors each accounted for 1, occurred in the general location of network error each accounted for 1. Fault classification shown in Figure 3.

FIG. 3 FAULT CLASSIFICATION OF 2D-MESH NETWORK

Here, we take a network error occurred in the general location for the example, to illustrate the use of Y-priority routing algorithm how to bypass the error, in order to achieve fault tolerance. In a normal part of the network, the packet is forwarded in accordance with the XY routing algorithm, which is to forward in the X direction at first, after arriving at the destination address in a single direction, then upward along the Y direction forward, until it reaches the destination node. When a packet enters invalid part, and the next hop routing failure, no longer using XY routing algorithm. At this time, the packet is routed directly neighbors failed. In accordance with the Y-priority algorithm, when the data packet is transmitted directly to the point of failure neighbors, and by XY routing algorithm is the next hop routing failure, the data packets to their counterclockwise neighbor, that neighbor indirect routing failure forwarding hop; when a packet arrives indirect neighbors, first forwarded along the Y direction, until the packet leaves the ineffective portion or Y direction to reach the target coordinates. Algorithm is schematically shown in Figure 4. After further analysis, we can see that, if the four angle positions in the network fail, the process may be generally straight. For errors that occur at the network boundary, you can set certain boundary rules, the algorithm applies the boundary position.

FIG. 4 Y-PRIORITY ROUTING ALGORITHM

3 SIMULATION RESULTS ANALYSIS

In this simulation test, the design of a complete routing node includes input ports, output ports, the routing table, cache space, and other parts of the arbiter. For planar microstructures routing nodes, its general form should have five input and output interface, representing the East, South, West, North, and local five directions. Local direction and local IP core are connected through the resource network interface. Each input port can request for output data through output ports of the other four directions.

A. Routing Node Simulation

All simulations are completed by test platform provided in the ISE Design Suit14.1. Now with coordinate (1, 2) as the
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normal network node, receiving the target address (3, 4) data packet from the South Node and forwarding the packet outside eastward, taking the process for example doing simulation testing, and detailing the simulation results. 1) Head decoder emulation Head decoder is the key part for the design of entire router nodes. It is responsible for implementing the designed routing algorithm and completes the data transmission path selection. It first receives the frame header of data sent from the routing controller routes, analysis the frame head, takes out the target address, calculates the packet forwarding direction, finally the result feedback to routing controller. Head decoder simulation results is shown in Figure 3-1, the first decoder is pure combinational logic devices, and therefore not listed in the clock signal. 0-100ns, head decoder in the reset state, the decoder output Rev is high impedance, the decoding completion signal HD_Ready is low, 100ns, the reset signal HD_RST pulled, while receives the destination address XY_goal, local address XY_local, location register values Position_reg, channel register values Channel_reg into the head decoder, the head decoder began to perform routing algorithm. 200ns, HD_EN signal pulled, open head decoder output enable. At this time, the decoding completion signal HD_Ready output is high, that is head decoder completes decoding. decoded output Rev is 00100, which means that data forwarding in the east, in line with the expectations of the algorithm.

FIG. 5 RRESULTS OF HEAD DECODER SIMULATION

FIG. 6 RESULTS OF ROUTING CONTROLLER RECEIVES THE DATA SIMULATION

As can be seen from Figure 5, the head decoder implements accurately the routing algorithm and provides the correct
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forwarding direction. 2) Routing controller emulation Routing controller is the core device of the routing nodes. In this article, the routing controller uses polling for arbitration, and applies the principle of Hot Potato for forwarding, that packet is received, immediately analyze and forwarded out, not do extra storage. This ensures that the data transfer in order, while saving the chip area of the buffer area, reducing system power consumption. Route controller has two main functions: data receiving function and data transceiver function. Route controller completes the data receiving and forwarding function under the control of the internal state machine, simulation clock signal cycle is 100ns, the frequency is 10MHz, simulation results are shown in Figure 6 and Figure 7. The first two cycles, the system is reset. Data input port DIN, receiving acknowledge input port, sending acknowledge input ports are 0; data output port DOUT, receiving acknowledge output ports, sending acknowledge output ports are high impedance; simultaneously head decoder enable signal HD_EN is low level, the head decoder enabled closed. Beginning from the third cycle, routing controller into the receiving phase, packets are sent routing controller from the DIN port in turn. Each data frame reception takes one cycle. Eighth cycle, a complete packet has been sent, the receiver acknowledge output port into the high impedance state, the head frame from DOUT into head decoder, enable signal HD_EN pulled, the system enters the decoding state. After head decoder receiving data, the data output port DOUT re-enter a high impedance state. Before the arrival of the ninth cycle, head decoding complete, HD_Ready signal is high, the system enters the transmit state. From the thirteenth cycle begin, the system will receive the data frame in the order received to DOUT port, after sending the packet, DOUT output is high impedance. A data transfer completion. Figure 6 and Figure 7 show the routing controller implements a data reception and forwarding functions, forward direction matches the results of algorithm, simulation results show that the scheme is feasible.

FIG. 7 ROUTING CONTROLLER TANSFERS THE DATA SIMULATION RESULTS.

FIG. 8 NETWORK DIAGRAM.

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B. Network Simulation
In this section, the router using the above design, to build a scale of 3 * 3 2D-mesh network, shown in Figure 8, in the network, because (2, 2) at the failed router , from (2, 3) to the node (2, 1) does not follow the XY routing path, namely along the (2, 3), (2, 2), (2, 1) transmission. According to the above routing algorithm, the data will bypass (2, 2) node, along a new path (2, 3), (1, 3), (1, 2), (1, 1), (2, 1) transmitted to the destination node. The simulation results are shown in Figure 9: As we can be seen from Figure 3-5, the data forwarding path and algorithm analysis were consistent, indicating that the router has a single routing error tolerance fault tolerance.

FIG. 9 SIMULATION OF ROUTING NETWORK

4 CONCLUSION
With the development of NOC, fault tolerance becomes a hot topic and focus. This paper presents a new fault-tolerant routing algorithm, Based on the classical XY dimension order routing algorithm, increasing adaptive routing algorithm, in a normal part of the network, the packet is forwarded according to XY routing algorithm, when the packet enters ineffective portion, and the next hop routing failure, no longer using XY routing algorithm. At this time, if the packet is routed directly adjacent failed node, then according to Y-priority routing algorithm, the packet clockwise to their neighbors, namely jumping forward indirect adjacent node of fault routing; When the packet arrives indirect neighbor, first forwarded along the Y direction, until you leave the ineffective portion or Y direction to reach the target coordinates. Such an algorithm avoid network congestion and reduce latency. Simulation experiments were performed in ISE Design Suit14.1 platform running on a Noc simulation model, in this model, for 3*3 2D-mesh structure experiments. Simulation results show that: Based on the XY dimension order routing algorithm, this paper increases adaptive routing algorithm, this dynamic fault tolerant routing algorithm is superior to the single deterministic routing algorithm and adaptive routing algorithm, and its low power consumption, avoiding congestion, no dead lock, network performance is more stable.

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