Design of High Speed Data Acquisition System Based on FPGA and DSP

Zhang Baofeng 1, Wang Ya 2, Zhu Junchao 1

1

Tianjin Key Laboratory for Control Theory & Applications in Complicated Systems Tianjin University of Technology Tianjin, 300191, China
zhangbaofeng@263.net

2 Tianjin Key Laboratory for Control Theory & Applications in Complicated Systems Tianjin University of Technology Tianjin, 300191, China
wya518@163.com

Abstract-A high speed data acquisition system based on

FPGA and DSP is introduced in the paper. In this system . we use EP2C5Q208 FPGA of Cyclone II which belongs to Altera .Data is captured by AD and be send to FPGA for advance data processing .And then data will be Processed in DSP .In the end, they will reach the PC for record and display by PCI . The simping speed of the system can reach 150MSPS. it is suitable for applications in most of the high speed data acquisition Situation.

I n d ex T erms-high speed data acquisition. FPGA: DSP:

AD9254.

1. INTRODUCTION DESIGN OF THE SYSTEM

With the Evolvement of testing ,we need to capture and process the weak signal, high frequency signal and the complex signal quickly and accurately. Then ,it will be more stringent in sampling rate, accuracy, storage capacity, processing speed, etc. High-speed data acquisition system is widely used in image data acquisition , radar , communications , telemetry , remote sensing, medical imaging technology. The speed of Data acquisition system will be Directly limited by MCU which is Controlled by it. Recently, FPGA/CPLD have been more widely used by its very stable, fast, flexible programmability[ll.
2. DESIGN OF THE SYSTEM

appropriate signal processing algorithms for further data processing[21. Figure 1 is the block diagram of hardware design of the high-speed data acquisition system. This system can complete the acquisition of complex signals. The data information will be changed into the fonn of differential signal in the signal conditioning circuit which captured by the front-end sensor, and the data will import AD. AD9254 will change the analog signals into 14bit digital signals and the data will be processed by FPGA. Corresponding digital signal processing algorithms will be implemented in the DSP. Data, processed by FPGA and DSP ,will be sent to PC b PCI interface[21.

circuit

Fig.

1.

Block diagram of hardware design of the high-speed data

acquisition system

This paper introduces a high-speed data acqUIsItIon system based on FPGA and DSP. The device of FPGA is EP2C5Q208 of Cyclone II device family which be provided by ALTERA. The AD device is AD9254 of AD! which Sample Rate can reach 150MSPS. Data pre processing, include system global clock module, digital mixing module, FIR filter module and FIFO modules, will be done by FPGA.DSP of TI will complete the
978-1-4244-6936-9/10/$26.00 2010 IEEE

Fig. 2. Pcture of the high speed data acquisition card

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3. FUNCTION MODULE

3.3.

Design of DSP

All paragraphs must be indented. All paragraphs must be justified, i.e. both left-justified and right-justified.
3. 1.

AD Sample Circuit

The AD9254 is a monolithic, single 1.8 V supply, 14bit, 150 MSPS analog-to-digital converter (ADC) which provided by ADI , featuring a high performance sample and-hold amplifier (SHA) and on-chip voltage reference. SNR 71.8 dBc (72.8 dBFS) to 70 MHz input ,SFDR 84 dBc to 70 MHz input ,differential input with 650 MHz bandwidth. The product uses a multistage differential pipeline architecture with output error correction logic to provide l4-bit accuracy at 150 MSPS data rates and guarantees no missing codes over the full operating temperature range. A differential clock input controls all internal conversion cycles. A duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance. Figure3 is the functional block diagram of AD9254[7l.
= =

AVDD

DRIIDO

AD9254

The system uses the high-performance fixed-point DSP TMS320DM642 of Tl. The TMS320DM642 device is the highest-performance fixed-point DSP generation in the TMS320C6000 DSP platform. With performance of up to 5760 million instructions per second (MIPS) at a clock rate of 720 MHz, the DM642 device offers cost-effective solutions to high-performance DSP programming challenges. The TMS320DM642 (DM642) device is based on the second-generation high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications[5l. The C64x DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units-two multipliers for a 32-bit result and six arithmeticlogic units (ALUs)-with VelociTI 2 extensions.The DM642 uses a two-level cache- based architecture and has a powerful and diverse set of peripherals. In addition, the TMS320DM642 device also has lots of function, for example, 64-Bit External Memory Interface (EMIF);1024M-Byte Total Addressable External Memory Space; Enhanced Direct-Memory Access (EDMA)Controller;32-Bit/66-MHz,3.3-V Peripheral Com-ponent Interconnect (PCI) Master/Slave Interface Conforms to PCI Specification 2.2.etc[5l[6l.
4. IMPLEMENT OF

OR Deo VREF
SENSE
01J

FPGA'S INTERNAL FUNCTION

(MSB)

DO (LSS)
SCLKlDFS SOIO/OCS CSS

AGNO

eLK.

CLK-

POWN

CRGNO

IF signal of the system is 70MHz, channel bandwidth is lOMHz. Taking into account the rectangular coefficients of the analog filter, chosen the sampling rate of AD9254 at 50MHz. Data pre-processing is done in FPGA,we completed the software design by QuartusII 7.2. The software include a system global clock module, digital mixing module, FIR filter module and FIFO module[2l. 50MHz .

Fig. 3. Functional Block Diagram of AD9254

3.2.

Design of FPGA

I IOOMHz

AD System In this system ,we use EP2C5Q208 of Altera Cyclone Configur Global II FPGAs .Following the immensely successful first CLK ation generation Cyclone device family, Altera Cyclone II FPGAs extend the low-cost FPGA density range to 68,416 logic elements (LEs) and provide up to 622 usable I/O pins and up to 1.1 Mbits of embedded memory. Cyclone II Digital FPGAs are manufactured on 300-mm wafers using FIR Mixing FIF O AD TSMC's 90-nm low-k dielectric process to ensure rapid Module .. Module I-.. availability and low cost. By mini-mizing silicon area, I Cyclone II devices can support complex digital systems Fig. 4. Internal functional block diagram ofFPGA on a single chip at a cost that rivals that of ASICs[4l. The Cyclone II device family offers the following fea 4. 1. System Global Clock Module tures: High-density architecture with 4,608 to 68,416 LEs ; There are several clock signals in FPGA, we used Embedded multipliers ;Advanced 110 support; Flexible Phase-locked 100p(PLL) of Cyclone II FPGA to generate clock management circuitry;Device configuration internal and external clock signal .There are two PLL in Intellectual properti4l. EP2C5, and Each PLL have up to six internal clock, four

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pairs of differential (or eight single-ended) external clock output. The external clock output can only be assigned to dedicated external clock output pin. As external device clock, they can not be used internally in the FPGA..PLL can implement delay offset, clock Flip, PLL reconfiguration, programmable bandwidth, spread spectrum clock, external clock output function, and it can achieve clock multiplication and division with the same clock source.
4.2.

entry; rdreq: Reading signal; wrreq: Write signal; Empty: empty flag; full: full marks; q: data output; usedw: Storage space[2][3].
scfifo:scfifo_component clocl< rdrcq
wrreq

clock rdreQ wITeq dulurS .

. .

emply
filii

empt.y

full
-

data[5 .

. .

0]

q rS . . 0] 01 usedwrll .
. .

[5 . . 0]
. .

01

usedwill .

01

Digital Quadrature Mixer Module

Mainly based on software radio in the digital mIxer theory.ln order to get the signal after mixing:
J'(n)=x(2n)e(-IY; Q'(n)=x(2n + 1) e(-I)";

We can get the output signal ,by reuse the two-way signal, x(n)*1, 1, -1, -l. Through this method, the data rate of the output signal is twice of I' (n), Q' (n). First, put the local oscillator signal into ROM module; second, make the input data multiply the LO signal by Embedded hardware multiplier in FPGA, we can get the quadrature mixing signals. Because data was double extracted after mix, in the follwing , clock signal will be the half division of mix. Therefoe,use the PLL to implement division of clock. PLL not only can achive multiplication and division but also can setup the phase difference between different output clocks.
4.3.

FIR Filter Module

FIR low-pass filter module mainly uses the IP core " MegaWizard Plug-In Manager " of design,use Altera ,choose "create a new custom megafunction" , unfold DSP> Filters , choose FIR Compiler, Select the out -put file ' s type of your design,. Selected the user library which choosed in the second step, then you can setup the parameter of filter by IP toolbench of FIR Compiler .We can setup the order of filter, sampling rate, bandwidth, filter structures, filter input channels, input data bits and the use of the filter structure,etc[3]. For filter based on IP core design, generally, we can get coefficient by FIR Compiler, and also can get by MATLAB or SPW and load the coefficient in to IP core .The advantage of the latter is there will be more method to design filter. You can save a lot of time by Simulation.
5. SYSTEM SOFTWARE DESIGN

Software design include FPGA and DSP software design software design. FPGA software design use Quartus II 7.2,program with VHDL .The program consists of 3 parts: AD92S4 control module; underlying pre processing module; FIFO memory module. FigS is the RTL diagram . Among them: clock: clock input; data: data

Fig. S. RTL of FIFO Memory module FIFO memory VHDL program: LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf ; USE altera_mf . altera_mecomponent s. all ; ENTITY my_fifo IS PORT(clock : IN STD_LOGIC; data : IN STD_LOGIC_ VECTOR (1S DOWNTO 0) ; rdreq : IN STD_LOGIC; wrreq : IN STD_LOGIC; empty : OU T STD_LOGIC; full : OU T STD_LOGIC; q : OU T STD_LOGIC_ VECTOR (1S DOWNTO 0) ; usedw:OUT STD_LOGIC_VECTOR (11 DOWNTO 0) ) ; END mLfifo ; ARCHITECTURE SYN OF mLfifo IS SIGNAL sub_wireO :STD_LOGIC_VECTOR (11 DOWNTO 0) ; SIGNAL sub_wire1 :STD_LOGIC; SIGNAL sub_wire2 :STD_LOGIC_ VECTOR (1S DOWNTO O) ; SIGNAL sub_wire3 :STD_LOGIC; COMPONENT scfifo GENERIC ( intended_devicejamily : STRIN G; lpm_numwords :NATURAL ; lpm_showahead :STRlN G; lpm_type :STRING; lpm_width :NATURAL ; lpm_widthu :NATURAL ; overflow_checking :STRIN G; underflow_checking :STRING; use eab :STRING ); PORT ( usedw:OUT STD_LOGIC_VECTOR (11 DOWNTO 0) ; rdreq : IN STD_LOGIC; empty :OU T STD_LOGIC; clock : IN STD_LOGIC; q : OU T STD_LOGIC_ VECTOR (1S DOWNTO 0) ; wrreq : IN STD_LOGIC; data : IN STD_LOGIC_ VECTOR (1S DOWNTO 0) ;

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full :OU T STD LOGIC ); END COMPONENT ; BEGIN usedw < sub_wireO (11 DOWNTO 0) ; empty < sub_wire1 ; q < sub_wire2 (15 DOWNTO 0) ; full < sub_wire3 ; scfifo_component : scfifo GENERIC MAP ( intended_deviceJamily > "ACEXI K" , lpm_numwords > 4096 , lpm_showahead > "OFF" , lpm_type > " scfifo" , lpm_width > 16 , lpm_widthu > 12 , overflow_checking > "ON" , underflow_checking > "ON" , use eab > "ON" ) PORT MAP ( rdreq > rdreq , clock > clock , wrreq > wrreq , data > data , usedw > sub_wireO , empty > sub_wire1 , q > sub_wire2 , full > sub wire3 ); END SYN ;
= = = = = = = = = = = = = = = = = = = = =

Conditioed Signal

200
Fig. 7. Conditioned Signal

(00

600

1110

11100

PlOcested

Signal

200

(00

800

1000

Fig. 8. Processed Signal

7. CONCLUSION

6. THE EXPERIMENT RESULTS AND ANALYSIS

The high speed data acquisition system was simulated with high-frequency input signal at 300MHz by using CCStudio and Labview .From the results of the system simulation ,we can reach a conclusion that the system performances in a hi h level.

This paper introduces a high speed data acqUISItIOn system based on FPGA and DSP .The paper described design of the system, AD sampling circuit, FPGA circuit design, DSP circuit design and FPGA design software. The system uses AD9254 with high speed and precision .The chip is mainly used for medical imaging, 3G mobile communications and other fields. It is rarely in the application of the data acquisition. The high speed data acquisition system based on FPGA and DSP is strong versatility.
ACKNOWLEDGMENT

The work is supported by Tianjin Science and Technol ogy Development Fund.
REFERENCES
[1] Sumukh Pathare, Robert Gao, Biju Varghese,"A DSP-Based Tclemetric Data Acquisition System for In-Process Monitoring of Grinding Operation," Department of Mechanical and Industrial Engineering University of Massachusetts, St. Paul, Minnesota, USA May 18-21, 1998 [2] DAI Gang,LI Mei ,SU Wei,A novel single chip implementation of MEMS INS data acquisition and processing system using FPGA and its soft processors,Institute of Electronic Engineering, China Academy of Engineering Physics, MianYang ,Sichuan,2009

Fig. 6. Generated Signal

[3]

Van Lei, Zhao Gang, Ryu Si-Heon, The Platform of Image Acquisition and Processing System Based on DSP and FPGA, Kyungpook National University, 702-70 I, Korea,2008

[4] [5] [6] [7]

Cyclone II Device Handbook, www.altera.com. Data Manual TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor. Data Manual.www.ti.com TMS320C6000 DSP eripheral Component Interconnect (PCI) eferenee Guide. Data Manual.www.ti.com AD9254 Data Manual. www.altera.com

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