The Principles Of BoundaryB Boundary -Scan S

Lesson Lesson 2
October 2009

The Test Challenge

Find the failures before your customers do!

More than 90% of the PCBs produced will contain at least one structural fault
Ref: Charles Robinson and Amit Verma, Teradyne Inc., APEX 2002
October 2009

The functional testing approach

Advantages
Exercises the product the way it will be used in the field field functionally Very effective at assuring quality standards are met

Disadvantages
Test prepared manually, often requiring input from the design engineer Faults found at functional test may be difficult to diagnose, requiring designer participation Most factories have a bone-pile of boards that fail functional test

October 2009

The structural testing approach

Advantages
Tests are generated automatically, by intelligent software tools, using an exhaustive list of the potential structural faults on the board Detection and diagnosis of faults can be precise and to the pin level

Disadvantages
Intended to detect manufacturing faults only solder problems, incorrect parts, etc. (not design faults) Only valuable if sufficient test point access is available

October 2009

Traditional structural testing

Potentially defective wire bond BGA ESD damage Open under BGA BGA Short to power or ground

Power or GND

Bridging fault

Inner board layers, layers blind vias

In-circuit In circuit testing will have difficulty finding these types of faults
Boundary-scan can help!
October 2009

test coverage with boundary-scan

Test wire bond BGA TAP Detects ESD damage Finds open BGA Finds short, , s-a-0 or s-a-1

Power or GND

Finds solder bridge under BGA

Provides access to blind vias, inner layers

Fixture is greatly simplified or eliminated

October 2009

IEEE 1149.1 BoundaryBoundary-Scan Standard

Adopted in 1990 by the IEEE as Standard 1149.1 Prepared by the Joint Test Action Group (JTAG) Originally for testing boards and devices 1149.1 is an IC standard Serial 4-wire (5th is optional) TAP interface That Provides Access To Device I/O Pins Defines a set of operations outside the chips normal operation Semiconductor manufacturer is responsible for: Designing device for compliance to the IEEE 1149.1 Standard Many components are now Boundary Boundary-Scan Scan compliant Microprocessors, CPLDs, ASICs, FPGAs, DSPs & Memory FLASH Memory is programmable, via Boundary-Scan Providing A Compliant BSDL file

October 2009

What is IEEE 1149.1 boundaryboundary-scan?

A chip chip-level level standard, standard adopted by the IEEE in 1990 4 (or 5) added pins form the Test Access Port (TAP) Additional logic inside the IC: scan cells on I/Os, controller & registers Data from the boundary-scan source (on TDI) can be loaded into the device and read from the device pins on TDO Optional 5th line TRST active low asynchronous reset

IC Core

TDI

Bypass Instruction Reg. ID Register

TDO

TMS TCK

Controller

TRST

Every I/O on a compliant IC becomes a test point

October 2009

IEEE 1149.1 Architecture

Internal Core Logic Shift-DR Shift Bypass Shift IR TDI Bypass Identification Instruction TMS TCK TAP Controller TDO

October 2009

IEEE 1149.1 State Machine

1 0 Test Logic Test-Logic Reset 0 Run-Test Idle 1 1 Capture-DR 0 0 Shift-DR 1 1 Exit1-DR 0 Pause-DR 1 0 TMS: 0,1 Update-DR Update DR 1 0 1 Exit2-DR 1 Update-IR 0 0 Exit2-IR 1 0 Pause-IR 1 Exit1-IR 0 0 Shift-IR 1 1 0 Select DR-scan 0 1 Capture-IR 0 1 Select IR-scan 0 1 Data Register Instruction Register

October 2009

The Instruction Register

Decoded Output to Selected Data Registers
Internal core logic
TDI TDO

Bypass Identification Instruction

TMS TCK TAP controller

Hold Elements

Decoder

TMS TCK

Test Access Port TAP controller

TRST (optional)

Clock-DR Shift-DR Update-DR Capture-DR TCK Clock-IR Shift-IR Update-IR Capture-IR Select

TDI Shift Register

TDO

0 1 IR Length > 2

October 2009

BoundaryBoundary -Scan Instructions

Instruction Bypass Bypass (Initialized state) Sample/Preload / Boundary-Scan 000..00 Boundary-Scan Extest Intest Idcode RunBist Scan Usercode Clamp HighZ Code 111..11 Selected Data Register mandatory

Boundary-Scan Identification or Bypass optional Internal BIST Internal Scan Identification Bypass: outputs from BS cells Bypass: outputs in High-Z High Z state

October 2009

The Boundary Boundary-Scan (DATA) Register

X-Bit Shift Register A Data Register Selected by One Of The Instructions: - EXTEST - SAMPLE PRELOAD
TDI
Bypass Internal

core logic

TDO

- INTEST
Identification

- ???? Parallel Input and/or Output

TMS TCK

Instruction

TAP controller

October 2009

Cell Types of the Boundary Register

TDI INPUT CLOCK
CELL CELL CELL

TDO

CELL

2-STATE OUTPUT

CORE LOGIC CELL CELL

CELL

INTERNAL CELL

CELL

3-STATE OUTPUT

CELL

CELL

BI-DIRECTIONAL

October 2009

Bypass (DATA) Register

One Bit Shift Stage Selected by BYPASS Instruction No Parallel Output Captures a Hardwired 0
TDI
Internal core logic

Bypass

TDO

Identification Instruction

TMS

Shift-DR

TAP

TCK

controller

0
TDI

_ 1 1

1D

TDO C Clock DR
C1

October 2009

Identification Register
Main Function: Identify the Device 32-Bit Shift Register Selected by IDCODE Instruction No Parallel Output Captures a 32 Bit Hardwired Word If No Identification Register Is Present, The BYPASS Instruction Must be Selected
TMS TCK TAP controller TDI

Internal core logic

TDO

Bypass Identification Instruction

**Part of infrastructure test

October 2009

Device identification code structure

31 28 27 Part Number 16 Bits Manufacturers Own Coding
G

12 11

1 Manufacturer 11 Bits

0 1 1 Bit

Version 4 Bits Version Code

Compressed Form Of JEDEC Code

Shift-DR 0/1 TDI Clock DR

_ 1 1

1D

TDO
C1

October 2009

Applying boundary boundary-scan to the PCB

Scan device #1 TDI TDO TMS TCK

Example of a PCB
Scan device #2

TAP

with one boundaryscan chain

Typically, Typically only a

fraction of the ICs need to be scancompliant

Scan device #3

October 2009

Alternate partitioning (2 chains)

Scan device #1 TDI

Chains are tested

Scan device #2

TDO TMS TCK

concurrently for max throughput with no loss of test coverage

Up to 4 chains with

TAP 1

single QuadPOD
Provides valuable
Scan device #3

design flexibility*
TDI TDO TMS TCK

*To be discussed in DFT section

October 2009

TAP 2

Board Level Applications

Testing
Infrastructure Interconnections Clusters Memory A/D buses
& control signals
SD PLD R R uP

TAP2 TAP1

Digital I/O D scan module

TAP

Connector

FPGA

P Programming
SD

CPLDs, FPGAs Flash memories

(w/ AutoWrite)
F

Cluster

Cluster

Connector

October 2009

Infrastructure Capture test

TCK TMS
Test logic reset Run-test/idle Select-DR Select-IR Capture-IR Shift-IR Exit-1
October 2009

BoundaryBoundary -Scan Test Principle

Stage 1 Shift Data to Output cell

1 core 0 core

10

October 2009

BoundaryBoundary -Scan Test Principle

Stage 2 Update Data from Output Cell to Net

1 1 core 0 0 core

October 2009

BoundaryBoundary -Scan Test Principle

Stage 3 Capture Data from Net to Input cell

1 1 0 core 0 0 core 1

October 2009

BoundaryBoundary -Scan Test Principle

Stage 4 Shift Captured Data Out

1 core 0 core

01

October 2009

Extensions to the IEEE 1149.1 Standard

Ieee 1149.4 1149 4
Released in 1999 Analog testing, voltage measurement and current driving
Drive and sense analog values via 2 additional pins and busses internal to the IC

Up until now, very limited deployment/nonexistent U / JTAG offers analog evaluation kits

Ieee 1149.6
Approved March 20, 2003 For high-speed AC-coupled nets and differential signaling

Ieee 1532
Latest version: Dec. 11, 2002 Standardizes PLD programming among various vendors
Allows concurrent programming, mixed vendor chains BSDL files include the programming algorithms

October 2009

The Show

October 2009