EEE523: ADVANCED ANALOG IC DESIGN

PROJECT 1 CMOS -MULTIPLIER BASED CONSTANT-GM CURRENT REFERENCE Current Mirrors

NAME (LAST, FIRST, MI)

: PARAMAIAHGARI SRIKANTH R

ASU ID #

: 1206321047

Objective:
1 Objective In this project, we will design three -multiplier based current reference circuits, using CMOS transistors in TSMC 0.25 CMOS design library. For the current setting resistor R, we can use an ideal zero-temperature coefficient resistor from analogLib library. The resistor R and multiplication value K sets the branch currents. We will size the transistors, K and R to optimize in such a way that the reference currents Iref1 , Iref2 match for a wide range of supply voltage Vdd for designs 1, 2 and 3 and try to be as constant as possible. Also, We would use this current to bias an NMOS transistor and prove that its gm is constant, just like the current setting resistor R across process, voltage and temperature. Design Procedure: First of all to make sure the startup circuit work properly, we need to make sure the VGS of startup transistor less than Vth after the circuit turns on completely. To make sure VGS of stratup transistor is less than Vth , we need to increase the length of the diode connected PMOS or NMOS. For all three designs, considering M1 and M2 NMOS transistors applying KVL around the loop, we can write Vgs1=Vgs2+I2R. which can only be valid if VGSI > VGS2. To ensure that this is the case, we use a larger value of in M2, that is, we multiply-up M1's in M2 so that less gate-source voltage is needed to conduct Iref. This is done by simply using a larger width in M2.The resulting circuit is called a Beta-multiplier reference circuit. =(2/((/)))+ Assume 2=(/)2 = K 1 Therefore, W2 = KW1 Solving for I2 from the above two relations, we get 2=(2/(2(/)))1(11/)2 Using the above equation wr can solve for R for given reference current Iref=10uA. Note that we have no dependency on VDD. For k=4, solving for Iref, we have a constant gm biasing circuit. Gm= Sqrt(2*k*w/L*Iref)= 1/R. In this pro ject, k is chosen to be 4 in three designs. To find the correct R value at Iref=10A, parametric analysis in Cadence is performed by varying the R(Because the calculated value of R is not exact due to ignoring body effect and channel length modulation effects).

All the transistors are sized by assuming Vdsat=125 mV. For design3, to achieve zero temperature coefficient for Vref, we need to find the correct value of resistor temperature coefficient to compensate it. The procedure to find the temperature coefficient is as follows : Plot dVth/dT of NMOS vs temperature (The Vth can be obtained from Calculator-->info-->op--> select the NMOS device and select Vth). Find the value of dVth/dT at 27C from the plot. Plot (1/Kp)*(dKp/dT) of the NMOS device vs temperature (The betaeff parameter from the op of NMOS should be divided by its (W/L) to get Kp). Find the value of (1/Kp)*(dKp/dT) at 27 C from the plot.Now use the equation (1/R)*(dR/dT) = R*Kp*(dVth/dT) (1/Kp)*(dKp/dT) and find out (1/R)*(dR/dT) using the values calculated above. This value corresponds to the Temperature coefficient1 parameter in the resistor model used in cadence. Now we can sweep the temperature coefficient value of the resistor and select the value of temperature coefficient 1 such that dVref/dT is minimum at 27C.

Design1: Schematic:

Sizing and biasing:

Parameter VDD Iref1 Iref2 gm Min 2.0V 9.043u 9.042u 110.6u Nom 2.5V 9.997uA 9.997uA 113.8u Max 3.0V 10.91u 10.91u 117u

These are obtained from Iref vs Vdd plots attached below. And it can be observed from the below schematic that Iref1=Iref2=10uA for 2.5V.

R= 7.757 kOhms.
Device M1 M2 M3T M3B M4T M4B MS1 MS2 MS3 W(um) 2.775 11.1 11.925 7.95 11.925 7.95 0.45 0.45 0.45 L(um) 0.6 0.6 0.825 0.9 0.9 0.6 45 0.3 0.6 Vgs-Vt(m V) 136.9 81.96 146 151.2 146 151.3 1.554V 44.7m 132m Vds(mV) 594.6 796.9 -737.4 -1.168 -736 888.5 -2.445V 1.169V 45.2 Ibias(uA) 10 10 10 10 10 10 0.6 10.01f 0.6

Iref1,Iref2 Vs Vdd: It can be observed from the below plot that Iref1 and Iref2 are with
+/- 5% (<0.5uA difference for 10uA) for entire Vdd range of 2 V to 3 V.

Vref vs Vdd:

Vref vs Temperature:

Gm vs Temperature: Theoritical gm=1/R= 1/7.754K = 128.9 uA/V. which is close to practical gm=129uA.

Design2: Schematic: Current of 10 uA is flowing through both the legs as observed at the resistor.

Sizing and Biasing:

Design questions: R=7.341 kOhms(parametric analysis)

Parameter Min VDD Iref1 Iref2 Gm 2.0V 9.54uA 9.51uA Nom 2.5V 10uA 10uA Max 3.0V 10.2u 10.25u

128uA/V 130uA/V 131uA/V

DESIGN QUESTIONS: Device M1 M2 M3T M3B M4B M4T M1T M2T Startup_n Startup_p W 2.775um 11.1um L .6um .6um VGS-Vt 136mV 82.2mV 141mV VDS Ibias

594.6mV 10uA 796.9mV 10uA 737mV 10uA 10uA 10uA 10uA

11.925um .9um 7.95um 7.95um .9um .9um

151.4mV 1.168V 151.2mV 889.5V 140.6mV 736mV

11.925um .6um 7.95um 7.95um 0.45um 0.450um .6um .6um

141.8mV 479.9mV 10uA 144mV 859.5mV 10uA 45.2mV 2.455V 1.169V 0.697uA 0.697uA 10fA

0.6um 131mV 45um .6um 1.553V 45mV

NMOS_switch 0.450um

Iref1,Iref2 Vs Vdd: It can be observed from the below plot that Iref1 and Iref2 are with
+/- 5% (<0.5uA difference for 10uA) for entire Vdd range of 2 V to 3 V.

Vref vs Vdd:

Vref vs Temperature:

Gm vs Temperature: Theoritical gm=1/7.341K= 136 uA/V close to practical.

Design3: Schematic:

Sizing and biasing:

Design questions: R=7.4265 kOhms(parametric analysis)

Parameter VDD Iref1 Iref2 Min 2.0V 9.9996uA Nom 2.5V 10uA Max 3.0V 10.0006u 10.00095u

9.99975uA 10uA

Gm(zero temp co R) 127.7uA/V DESIGN QUESTIONS: Device M1 M2 M3 M4 MA1 MA2 MA3 MA4 Startup_n Startup_p W 2.775 11.1um L .6um .6um

129.1uA/V 130.2uA/V

VGS-Vt 136mV 82.2mV 141mV

VDS 594mV 520mV

Ibias 10uA 10uA

11.925um .9um 11.925um .9um 2.775um 2.775um .6um .6um

1.905mV 10uA

140.6mV 1.905mV 10uA 135mV 145 122mV 122mV 1.744mV 12.27uA 1.77 755mV 730mV 45.2mV 2.455V 1.169V 12.25uA 12.27uA 12.25uA 0.697uA 0.697uA 10fA

11.925um .9um 11.925um .9um 0.45um 0.450um

0.6um 131mV 45um .6um 1.553V 45mV

NMOS_switch 0.450um

Iref1,Iref2 Vs Vdd: For entire range of Vdd Matching error between Iref1 and I ref2 is < 5%. It is very small as observed from below plot.

Vref vs Vdd:

Vth Vs Temperature:

Kpn vs Temperature:

Vref vs Temperature: With Zero temperature coefficient resistor

With 5m temp coefficient resistor

Gm vs Temperature Zero temperature coefficient resistor

With 5m temperature coefficient resistor: