TRAFFIC LIGHT CONTROL INTERFACE AIM: To interface the traffic light control system board to 8085 microprocessor kit

and write an assembly language program for the given traffic conditions. APPARATUS REQUIRED: 8085 microprocessor kit, traffic light control system board, 26 pin port THEORY:

Figure shows a simple arrangement and pin connections for microprocessor based traffic control. All ports of 8255 have been programmed as output ports. Three types of LEDs have been used, red, yellow and green. Green light glows to allow crossing, yellow to make alert and red does not allow crossing. Eight dual colour LEDs are provided for pedestrian crossing. These LEDs change their colour to red or to green. When the LED is ON it shows green colour and when it is OFF it shows red colour. The following traffic control states are for the experiment: State1: Vehicles can go from South to North. State2: Wait state. State3: Vehicles can go from East to West. State4: Wait state. State5: Vehicles can go from North to South. State6: Wait state. State7: Vehicles can go from West to East. State8: Wait state. State9: All pedestrians can cross. State10: Wait state. Since the LED is an output device, all 8255 ports are assumed to be output ports in mode 0. Therefore the control word is 80H. For the state 1, the green LED connected to pin PA4 must glow and the red LEDs connected to pins PA1, PB3, PA3 must glow. Also pedestrians must be in OFF conditions. Therefore the data that is to be sent to the ports A, B and C are 1A, F8, 00 respectively. DIRECTIONS PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 DATA South-North 0 0 0 1 1 0 1 0 1A DIRECTIONS PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 DATA South-North 1 1 1 1 1 0 0 0 F8

The above data is sent to the respective port to allow the vehicle from south to north. Similarly all the data are sent to the port for the further process

Port A Data table: DIRECTIONS PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 DATA South-North 0 0 0 1 1 0 1 0 1A Wait-1 0 1 1 0 1 0 0 0 68 East-West 1 0 0 0 1 0 0 0 88 Wait-2 1 0 1 0 1 0 0 0 A8 North-South 1 0 0 0 1 0 1 0 8A Wait-3 1 0 0 0 0 1 1 0 86 West-East 1 0 0 0 0 0 1 1 83 Wait-4 1 0 0 0 0 1 1 0 86 All pedestrians 1 0 0 0 1 0 1 0 8A Wait-5 0 1 0 0 1 0 1 0 4A Port B Data table: DIRECTIONS PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 DATA South-North 1 1 1 1 1 0 0 0 F8 Wait-1 1 1 1 1 1 0 0 0 F8 East-West 1 1 1 1 1 0 1 0 FA Wait-2 1 1 1 1 0 1 0 0 F4 North-South 1 1 1 1 0 0 0 1 F1 Wait-3 1 1 1 1 0 1 0 0 F4 West-East 1 1 1 1 1 0 0 0 F8 Wait-4 1 1 1 1 1 0 0 0 F8 All pedestrians 0 0 0 0 1 0 0 0 08 Wait-5 1 1 1 1 1 0 0 0 F8

Program
Memory location code Label Mnemonics Comments

4100 4102 4104 4106 4108 410A 410C 410F 4111 4113 4115 4117 411A 411C 411E 4120 4122 4125 4127 4129 412B 412D 4130 4132 4134 4136 4138 413B 413D 413F 4141 4143 4146 4148

3E,80 D3,OF 3E,1A D3,OC 3E,F8 D3,OD CD,85,41 3E,68 D3,OC 3E,F8 D3,OD CD,75,41 3E,88 D3,OC 3E,FA D3,OD CD,85,41 3E,A8 D3,OC 3E,F4 D3,OD CD,75,41 3E,8A D3,OC 3E,F1 D3,OD CD,85,41 3E,86 D3,OC 3E,F4 D3,OD CD,75,41 3E,83 D3,OC

START

MVIA,80 OUT OF MVIA,1A OUT OC MVIA,F8 OUT OD CALL DELAY1 MVIA,68 OUT OC MVIA,F8 OUT OD CALL DELAY2 MVIA,88 OUT OC MVIA,FA OUT OD CALL DELAY1 MVIA,A8 OUT OC MVIA,F4 OUT OD CALL DELAY2 MVIA,8A OUT OC MVIA,F1 OUT OD CALL DELAY1 MVIA,86 OUT OC MVIA,F4 OUT OD CALL DELAY2 MVIA,83 OUT OC

Initialize all ports in Output port Send port A and port B data of state 1 to respective ports

Send port A and port B data of wait state to respective ports Send port A and port B data of state 2 to respective ports

Send port A and port B data of wait state to respective ports

Send port A and port B data of state 3 to respective ports

Send port A and port B data of wait state to respective ports

Send port A and port B

414A 414C 414E 4151 4153 4155 4157 4159 415C 415E 4160 4162 4164 4167 4169 416B 416D 416E 4172 4175 4177 417A 417B 417C 417D 4180 4181 4184 4185 4187 418A 418B 418C 418D 4190 4191 4194

3E,F8 D3,OD CD,85,41 3E,86 D3,OC 3E,F8 D3,OC CD,75,41 3E,8A D3,OC 3E,08 D3,OD CD,85,41 3E,4A D3,OC 3E,F8 D3,OD CD,75,41 C3,04,41 OE,14 21,94,F6 2B 7D B4 C2,7A,41 OD C2,77,41 C9 OE,14 21,94,F6 2B 7D B4 C2,8A,41 OD C2,87,41 C9

DELAY 2 LOOP 2 LOOP 1

DELAY 1 LOOP 4 LOOP 3

MVIA,F8 OUT OD CALL DELAY1 MVIA,86 OUT OC MVIA,F8 OUT OC CALL DELAY2 MVIA,8A OUT OC MVIA,08 OUT OD CALL DELAY1 MVIA,4A OUT OC MVIA,F8 OUT OD CALL DELAY2 JUMP START MVIC,14 LXIH,F694 DCX,H MOV A,L ORA,A JNZ LOOP1 DCR, C JNZ LOOP2 RET MVIC,84 LXIH,93F2 DCX,H MOV A,L ORA,A JNZ LOOP3 DCR,C JNZ LOOP4 RET

data of state 4 to respective ports Send port A and port B data of wait state to respective ports

Send port A and port B data of state 5 to respective ports

Send port A and port B data of wait state to respective ports

Initialize count

Initialize count