Lab Report: FPGA

Group members (WRK STATION 1): Section 7-C

Zohaib Ali Farhat Abdul Rehman Wali Hamzah Khan Ali Adil Buttar

100183 100393 100128 100318

Date: 8/12/2013

LAB # 1 Xilinx ISE 7.1 Tutorial

Objective:
The goal of this lab is for you to become familiar with the Xilinx ISE by making a project in ISE and then to simulate it on Xilinx ISE Simulator.

Instruction:
The main emphases will be to make you learn, how the tools works to implement a Verilog code on FPGA.

Procedure:
o Create an ISE project for a Spartan-3 FPGA device. o Create a top-level HDL design and verify that your HDL code uses the correct syntax. o Create a test bench waveform to be used in simulation of the design. o Create a User Constraints File. o Apply timing and pin location constraints to the design. o Perform behavioral simulations on the design. o Synthesize and implement your design. o View the placed and routed design in FPGA Editor. o View the area groups of the design in Floor-planner. o Create a configuration bit-stream.

Code:
module lab1(a, b, y); input a, b; output y; assign y=a&b;

endmodule

RTL Diagram:

Results:

Lab # 2 Implementation of 4-to-1 Line Multiplexer on FPGA Kit Objective:

This lab is an introduction to Digilent Nexys2 Board. The goal of this lab is for you to design a 4-to-1 line multiplexer, simulate it and implement it on FPGA Kit.

Instruction:
Implement 4-to-1 line multiplexer using Behavioural Modelling. After you have simulated the code you will implement it on FPGA so as to exercise your implementation skills.

Procedure:
Use Xilinx ISE to make your project. You have to design a 4-to-1 line multiplexer and simulate it. Create a top-level HDL design and verify that your HDL code uses the correct syntax. Create a test bench to be used in simulation of the design. Create a User Constraints File. Apply pin location constraints to the design. Perform behavioral simulations on the design. Synthesize and implement your design. View the area groups of the design in Floor-planner. Create a configuration bit-stream. Implement the design on Digilent Nexys2 Training Board

Code:
module mux(Y,A,B,C,D,S0,S1); input A,B,C,D,S0,S1;

output Y; assign Y= S0?(S1?A:B):(S1?C:D); endmodule RTL Diagram:

Results:

LAB # 3 To Implement Combinational Circuit and Simulate the Required Result in Model-Sim Objective:
This lab is an introduction to Model-Sim. The goal of this lab is for you to learn how to code hardware architecture, simulate it on Model-Sim and implement it on FPGA Kit.

Instruction:
Implement the Architecture using module instantiation and write a simulator as per following instructions. After you have simulated the code on Model-Sim you will implement it on FPGA so as to exercise your implementation skills

Procedure:
Use Xilinx ISE to make your project. Code Figure 1 as Hardware Architecture.v file and its simulator as Test-bed.v Create a top-level HDL design and verify that your HDL code uses the correct syntax. Create a test bench to be used in simulation of the design. Create a User Constraints File. Apply pin location constraints to the design. Perform behavioral simulations on the design. Synthesize and implement your design. View the area groups of the design in Floor-planner. Create a configuration bit-stream. Implement the design on Digilent Nexys2 Training Board.

Code:
module mux(C1,a0,b0,s1); input [3:0] a0,b0; output [3:0] C1; input s1; assign C1=s1?a0:b0; endmodule

module function (Cout,s5,a0,b0,a1,b1,a2,b2,a3,b3,s1,s2,s3,s4); input [3:0] a0,b0,a1,b1,a2,b2,a3,b3; input s1,s2,s3,s4; output [7:0] Cout; output s5; wire [3:0] C1,C2,C3,C4;

wire [7:0] w1,w2,w3,w4; mux m1(C1,a0,b0,s1), m2(C2,a1,b1,s2), m3 (C3,a2,b2,s3), m4 (C4,a3,b3,s4); assign w1={c2,c1}, w2={c4,c3}, w3=w1+w2, w4=w1-w2; assign Cout =s5?w4:w3; endmodule

RTL Diagram:

Results:

LAB # 4 Implementation and Comparison of 8-bit Ripple Carry Adder and Carry Look Ahead Adder

Objective:
To understand the delays in digital circuits and its effects by implementation of two different types of Adder circuit on FPGAs.

Requirement before entering into the Lab:

You must read the Hardware algorithm of Carry Look Ahead adder and Ripple Carry Adder. You must bring your Text-Book which will help you in coding.

Instructions:
The delay in digital circuits is evident when we implement big combinational clouds. These delays lead to Hazards in digital logic circuits. One type of circuit where the effect of gate delays is particularly clear is an ADDER. In this lab you will simulate and measure the delay of ripple carry adder and carry look-ahead adder.

Procedure:
Make separate projects for both ripple carry adder and carry-look-ahead adder. Simulate functional model of both the adders using Model-Sim. The carry-look-ahead adder should be made as in the figure-4. First make 4bit adder and then replicate as given in the figure.

Do Timing Simulation after you have implemented the circuit. Check out the
results.

Code (Ripple carry adder):

module binary_adder (c8,s,a,b,c0); input [7:0] a,b; input c0; output [7:0] s; output c8; wire c1,c2,c3,c4,c5,c6,c7; fulladder FA0 (s[0],c1,a[0],b[0],c0); fulladder FA1 (s[1],c2,a[1],b[1],c1); fulladder FA2 (s[2],c3,a[2],b[2],c2); fulladder FA3 (s[3],c4,a[3],b[3],c3); fulladder FA4 (s[4],c5,a[4],b[5],c4); fulladder FA5(s[5],c6,a[5],b[5],c5); fulladder FA6(s[6],c7,a[6],b[6],c6); fulladder FA7(s[7],c8,a[7],b[7],c7); endmodule module fulladder (s1,c,x,y,z); input x,y,z; output s1,c; assign s1= x^y^z; assign c=x&y|y&z| z&x; endmodule

RTL Diagram:

Code (carry look ahead adder):

module CLA (a,b,c0,s,c8); input [7:0] a,b; input c0; output [7:0] s; output c8; wire c1,c2,c3,c4,c5,c6,c7; wire [7:0] p,g; halfadder HA0(p[0],g[0],a[0],b[0]); halfadder HA1(p[1],g[1],a[1],b[1]); halfadder HA2(p[2],g[2],a[2],b[2]); halfadder HA3(p[3],g[3],a[3],b[3]); halfadder HA4(p[4],g[4],a[4],b[4]); halfadder HA5(p[5],g[5],a[5],b[5]); halfadder HA6(p[6],g[6],a[6],b[6]); halfadder HA7(p[7],g[7],a[7],b[7]); assign c1=g[0]|(p[0]&c0); assign c2=g[1]|(p[1]&c1);

assign c3=g[2]|(p[2]&c2); assign c4=g[3]|(p[3]&c3); assign c5=g[4]|(p[4]&c4); assign c6=g[5]|(p[5]&c5); assign c7=g[6]|(p[6]&c6); assign c8=g[7]|(p[7]&c7); assign s[0]=(p[0]^c0); assign s[1]=(p[1]^c1); assign s[2]=(p[2]^c2); assign s[3]=(p[3]^c3); assign s[4]=(p[4]^c4); assign s[5]=(p[5]^c5); assign s[6]=(p[6]^c6); assign s[7]=(p[7]^c7); endmodule

module halfadder (s1,c,x,y); input x,y; output s1,c; assign s1=x^y; assign c=x&y; endmodule

RTL Diagram:

Comparison:
8 bit ripple carry adder: Delay in case of ripple carry adder is 19.756 ns

8 bit carry look ahead adder: Delay in case of 8 bit carry look ahead adder is 21.234 ns.

LAB # 5
Wallace Tree Multiplier

Objective:
This lab is an introduction to Model-Sim. The goal of this lab is to learn how to code Wallace tree multiplier, simulate it on Model-Sim.

Procedure:
Use Xilinx ISE to make your project. Code Wallace tree multiplier.

Create a top-level HDL design and verify that your HDL code uses the correct syntax.

Create a test bench to be used in simulation of the design. Perform behavioral simulations on the design. Synthesize and implement your design. View the area groups of the design in Floor-planner. Create a configuration bit-stream.

Code:
module Wallace_tree (a,b,w); input [3:0] a,b; output [7: 0] w; integer i,j; wire s1,s2,s3,s4,s5,s6,s7,s8,s10,s11,s12,s13; wire c1,c2,c3,c4,c5,c6,c7,c8,c10,c11,c12,c13; reg [3:0]p[0:3];

always @ (a or b) begin for (i=0; i<=3; i=i+1) for(j=0; j<=3; j=j+1) p[j][i]=a[j]&b[i]; end halfadder HA1(s1,c1,p[1][0],p[0][1]); halfadder HA2(s4,c4,p[3][1],p[2][2]); fulladder FA1(s2,c2,p[2][0],p[1][1],p[0][2]); fulladder FA2(s3,c3,p[3][0],p[2][1],p[1][2]); halfadder HA3(s5,c5,s2,c1); fulladder FA3(s6,c6,s3,c2,p[0][3]); fulladder FA4(s7,c7,s4,c3,p[1][3]); fulladder FA5(s8,c8,p[3][2],c4,p[2][3]); halfadder HA4(s10,c10,s6,c5); fulladder FA6(s11,c11,s7,c6,c10); fulladder FA7(s12,c12,s8,c7,c11); fulladder FA8(s13,c13,p[3][3],c8,c12); assign w={ c13,s13,s12,s11,s10,s5,s1,p[0][0] }; endmodule

module halfadder (s1,c1,x1,y1); input x1,y1; output s1,c1; assign s1=x1^y1; assign c1=x1&y1; endmodule

module fulladder (s,c,x,y,z); input x,y,z; output s,c; assign s= x^y^z; assign c=x&y|y&z| z&x; endmodule

RTL Diagram:

Results:

LAB # 6 Frequency Generator Objective:

The goal of this lab is to implement a circuit that generates square waves at specific frequencies based on user input.

Instructions:

Frequency select

Frequency Generator

Out

Clock

Reset

The clock must be the 50 MHz clock signal available from the oscillator. As shown in Figure, the module has three inputs. There are clock and reset inputs, plus a two-bit input to select one of four frequencies. There is a single output signal, which is intended to be connected to Oscilloscope. The module must drive the output to generate a square wave at the frequencies specified. The reset signal, on the other hand, certainly disables transitions on the output.

Count=

= Count = 250

Procedure:
make a new project for this lab.

use hierarchal Design flow or make the module in just one file. simulate the design and save the simulation result. synthesize the simulated design and make a .ucf file and assign the inputs and outputs on required ports.

implement the design on Digilent Nexys2 Board.

Code:
module abc (rst,clk,count) input rst,clk; output count; reg freq,count; always @ (posedge clk or negedge rst) if (rst==0) begin freq=0; count=0; end else if (count<250) count=count+1; else begin freq=~freq; count=0; end endmodule

RTL Diagram:

LAB # 7
Implementation of Piano keys using DIP Switch and 0.25 Watt speaker on FPGA Objectives:
This lab covers simple logic design using familiar building blocks. From previous work, we should already be familiar with flip flops, counters, and multiplexers. The goal of this lab is to implement a circuit that generates square waves at specific frequencies based on user input. When you successfully complete this lab, you will have developed a piece of intellectual property that you might be able to re-use in the future.

Instructions:
You are allowed to use only one clock and only one asynchronous reset signal. The clock must be the 50 MHz clock signal available from the oscillator. As shown in Figure, the module has four inputs. There are clock and reset inputs, plus a four-bit input to select one of 16 tones and an additional input to silence the audio output. There is a single output signal, which is intended to be connected to some form of audio output device.

Procedure:
Make a new project for this lab. Use hierarchal Design flow or make the module in just one file. Simulate the design and save the simulation result. Synthesize the simulated design and make a ucf file and assign the inputs and outputs on required ports. Implement the design on Nexys2 board.

Code:
module abc (y,freq,a,rst,clk);

input [3:0]a; input rst,clk; output y; output freq; reg y; reg freq,count; always @ (a) begin case (a) 4b0000 : y=16hDDF1; 4b0001 : y=16hD17C; 4b0010 : y=16hC5BA; 4b0011 : y=16hBAA1; 4b0100 : y=16hB028; 4b0101: y=16hA645; 4b0110 : y=16h9CF0; 4b0111 : y=16h9421; 4b1000 : y=16h8BD0; 4b1001 : y=16h83F7; 4b1010 : y=16h7C8F; 4b10101: y=16h7591; 4b1100 : y=16h6EF8; 4b1101 : y=16h68BE; 4b 1110 :y=16h62DD; 4b1111 : y=16h5D50; endcase end

always @ (posedge clk or negedge rst) if (rst==0) begin freq=0; count=0; end else if (count<y) count=count+1; else begin freq=~freq; count=0; end endmodule

RTL Diagram:

Results:

LAB # 8
Implement the given problem Statement using FSM Objective:
This Lab is about the Mealy & Moore Finite State Machine and their Implementation on Verilog HDL. A problem statement is given which is then converted into FSM and then code it using Verilog.

Instructions:

In Moore FSM the ouput is a function of the current state while in Mealy machine

output is the function of both the input and the current state of the Machine. Formulate the following problem into Finite state machine. An engineer working for SUPARCO. They want to design a FSM to test their newest SUPA Robot around the AIR University campus. Assume the Robot starts at A Block.

Robot will be required to go to the following locations (their 3-bit binary representations are listed as well): A Block (000) B Block (001), Management Block (010), Mini-Block(011), Student Cafeteria (100), IAA Building (101), Faculty Car Parking (110), and the VC office (111). From any state the robot can only travel to one of two other states. The information which tells the robot which location to visit next is wirelessly transmitted to the robots FSM by SUPARCO. The output of the FSM is the current state of the robot. The movements from location to location are as follows.
A Block: B Block: IAA Building:

If 0 stay at A Block. If 0 go to VC office.

If 0 stay at IAA Building.

If 1 go to B Block. If 1 go to IAA Building.

If 1 go to the Student Cafeteria If 1 stay at the Management

Management Block: If 0 go to the Student Cafeteria. Block Student Cafeteria: If 0 go to the Management Block.

If 1 go to Mini-Block.

Faculty Car Parking: If 0 go to Mini-Block. Mini-Block: VC office: If 0 stay at Mini-Block. If 0 go to IAA Building.

If 1 go to VC office. If 1 go to Faculty Car Parking. If 1 go to A Block.

Draw the state transition diagram for this FSM. If the SUPA is given the sequence 101001 write down the path (AIR University locations) the SUPA visits. If the rover is forever given a sequence of ones what location will it never visits? Design a module in Verilog for the rovers FSM (fsm.v).

Procedure:
Make a new project for this Lab. write code in RTL Verilog which should be synthesizable.

After writing the Code, simulate the Code using Model Sim. simulate the sequence 101001.

Code:
module fsm(clk, rst, bin, state); input clk, rst, bin; parameter ablock=3'b000,bblock=3'b001,managementblock=3'b010; parameter miniblock=3'b011,cafe=3'b100, iaablock=3'b101, vcoffice=3'b111; output [2:0] state; reg [2:0] state , nxtstate; always @(posedge clk or negedge rst) begin if(~rst) state <=ablock; else state <=nxtstate; end always@(bin or state) begin case(state) ablock : if (bin==0) begin nxtstate=ablock; end else if (bin==1) carparking=3'b110,

begin nxtstate=bblock; end bblock : if (bin==0) begin nxtstate = vcoffice; end else if (bin==1) begin nxtstate=iaablock; end managementblock : if(bin==0) begin nxtstate=cafe; end else if (bin==1) begin nxtstate=managementblock; end cafe :if(bin==0) begin nxtstate=managementblock; end

else if (bin==1) begin nxtstate=miniblock; end carparking :if(bin==0) begin nxtstate=miniblock; end else if (bin==1) begin nxtstate=vcoffice; end miniblock :if(bin==0) begin nxtstate=miniblock; end else if (bin==1) begin nxtstate=carparking; end vcoffice : if(bin==0) begin nxtstate=iaablock;

end else if (bin==1) begin nxtstate=ablock; end iaablock : if(bin==0) begin nxtstate=iaablock; end else if (bin==1) begin nxtstate=cafe; end endcase end endmodule Results:

LAB # 9 Implementation of Pipelined Version of Circuit in Lab 03 with an Accumulator using Verilog and Simulate Result in Model-Sim Objective:
In this lab we learn how pipelining works and what are the benefit of pipelining and what are its cost. We use an earlier design we made and modified it as given in the instruction.

Instructions:
Implement the Architecture using Data Flow Modelling and write a simulator as per following instructions. Simulated the code on Model-Sim. When the Final Summary Report of ISE is generated find how many LUTs have been used and what and which resource of FPGAs have been used in the Architecture.

Please note that Overflow/carry out/borrow has to be ignored. Simulation should be for the following inputs

A0=4'b0010; A1=4'b1000; A2=4'b1101; A3=4'b0100; B0=4'b1010; B1=4'b1100; B2=4'b1001; B3=4'b1000; CTRL_1=1; CTRL_2=0; CTRL_3=1; CTRL_4=0; CTRL_5=0; #20 A0=4'b0011; A1=4'b1000; A2=4'b1110; A3=4'b0100; B0=4'b1100; B1=4'b1101; B2=4'b1010; B3=4'b1001; CTRL_5=1; #20 A0=4'b0100; A1=4'b1000; A2=4'b1111; A3=4'b0100; B0=4'b1101; B1=4'b1101; B2=4'b1010; B3=4'b1001; CTRL_5=0; #20 A0=4'b0101; A1=4'b1000; A2=4'b1111; A3=4'b0100; B0=4'b1110; B1=4'b1101; B2=4'b1010; B3=4'b1001; CTRL_5=1; #20 A0=4'b0110; A1=4'b1111; A2=4'b1100; A3=4'b1001; B0=4'b1111; B1=4'b1101; B2=4'b1010; B3=4'b1001; CTRL_5=0; #20 A0=4'b0000; A1=4'b0000; A2=4'b0000; A3=4'b0000; B0=4'b0000; B1=4'b0000; B2=4'b0000; B3=4'b0000;

CTRL_5=1; #20 A0=4'b0000; A1=4'b0000; A2=4'b0000; A3=4'b0000; B0=4'b0000; B1=4'b0000; B2=4'b0000; B3=4'b0000; CTRL_5=0; #20 A0=4'b0000; A1=4'b0000; A2=4'b0000; A3=4'b0000; B0=4'b0000; B1=4'b0000; B2=4'b0000; B3=4'b0000; CTRL_5=1; #20 A0=4'b0000; A1=4'b0000; A2=4'b0000; A3=4'b0000; B0=4'b0000; B1=4'b0000; B2=4'b0000; B3=4'b0000; CTRL_5=0; #20 A0=4'b0000; A1=4'b0000; A2=4'b0000; A3=4'b0000; B0=4'b0000; B1=4'b0000; B2=4'b0000; B3=4'b0000; CTRL_5=0; You should able to monitor your input in the following way $monitor($time, "\nA0=%B\tA1=%B\tA2=%B\tA3=%B\nB0=%B\tB1=%B\tB2=%B\tB3=%B\nCTRL1= %B\t CTRL2=%B\tCTRL3=%B\tCTRL4=%B\tCTRL5=%B\nOUT=%d\n", A0, A1, A2, A3,B0,B1,B2,B3,CTRL_1,CTRL_2,CTRL_3,CTRL_4,CTRL_5, OUT);

Procedure:
Use Xilinx ISE to make your project. Code Figure 1 as HardwareArchitecture.v file and its simulator as Test-bed.v File

Working model on FPGA is not required only bit stream and final report summary is important.

Synthesize the circuit place and route, and generate the bit stream. Find the Number of LUTs used. The Resources of FPGA Spartan used.