Basics of porting C-code to and between ARM CPUs: the Cortex-M1 and Cortex-M0

Joseph Yi ! ARM "td# 10$1%$&011 ':11 PM ()*

In Part 2 in a series, Joseph Yiu, author of "The definitive guide to the ARM CortexM0," des ri!es the differen es !et"een the Cortex-M# and the Cortex-M0 and ho" to port $our soft"are ode !ase !et"een the%& Both the Cortex-M1 and the Cortex-M0 are based on the ARM architecture v6-M, so the differences between the Cortex-M1 and the Cortex-M0 are relatively small Instru tion 'et& !n the Cortex-M! "rocessor, #$!, #$% and &%' instructions are executed as ()*s +here is no slee" feature on current im"lementations of the Cortex-M! "rocessor &'C instruction su""ort is o"tional in the Cortex-Ml ,based on the desi-n confi-uration "arameter defined by an $*.A desi-ner/, whereas in the Cortex-M0 "rocessor, &'C instruction is always available ('!C &'C and *end&' exce"tions are o"tional in the Cortex-Ml "rocessor +hey are always "resent in the Cortex-M0 !nterru"t latency are also different between the two "rocessors &ome o"timi0ations related to interru"t latency ,e - 0ero fitter/ are not available on the current im"lementations of Cortex-M! "rocessor '$ste%-(eve) *eatures& +he Cortex-M1 has +i-htly Cou"led Memory ,+CM/ su""ort to allow memory bloc1s in the $*.A to connect to the Cortex-M1 directly for hi-h-s"eed access, whereas the Cortex-M0 "rocessor has various low-"ower su""ort features li1e #!C ,#a1eu" !nterru"t Controller/ +here are also a number of differences in the confi-uration o"tions between the two "rocessors +hese o"tions are only available for $*.A desi-ners ,for Cortex-M1 users/ or A&!C desi-ners ,for Cortex-M0 microcontroller vendors/ $or exam"le, with the Cortex-M1 "rocessor you can include both the serial wire debuand the 2+A. debu- interface, whereas Cortex-M0 microcontrollers normally only su""ort either the serial wire or the 2+A. debu- interface

Porting between the Cortex-M0 and -M 1 !n -eneral, software "ortin- between Cortex-M0 and Cortex-M 1 is extremely easy A"art from "eri"heral "ro-rammin- model differences, there are few re3uired chan-es Because both "rocessors are based on the same instruction set, and the architecture version is the same, the same software code can often be used directly when "ortin- from one "rocessor to another +he only exce"tion is when the software code uses slee" features Because the Cortex-Ml does not su""ort slee" mode, a""lication code usin#$! and #$% mi-ht need to be modified +here is also a small chance that the software needs minor ad4ustment because of execution timin- differences At the time of writin-, no CM&!& software "ac1a-e is available for the Cortex-M1 5owever, you can use the same CM&!& files for the Cortex-M0 on Cortex-Ml "ro-rammin-, because they are based on the same version of the ARMv6-M architecture )ifferences between the Cortex-M+ and -M0 +he Cortex-M6 "rocessor is based on the ARMv7-M architecture !t su""orts many more 68bit +humb instructions and a number of extra system features +he "erformance of the CortexM6 is also hi-her than that for the Cortex-M0 +hese factors ma1e the Cortex-M6 very attractive to demandin- a""lications in the automotive and industrial control areas Progra%%er+s Mode)& +he ARMv7-M architecture is a su"erset of the ARMv6-M architecture &o it "rovides all the features available in the ARMv6-M +he Cortex-M6 "rocessor also "rovides various additional features $or the "ro-rammer9s model, it has an extra non"rivile-ed mode ,:ser +hread/ when the "rocessor is not executin- exce"tion handlers +he user +hread mode access to the "rocessor confi-uration re-isters ,e - , ('!C, &ys+ic1/ is restricted, and an o"tional memory "rotection unit ,M*:/ can be used to bloc1 "ro-rams runnin- in user threads from accessin- certain memory re-ions ,,ig re &1#+ be-ow.# A"art from the extra o"eration mode, the Cortex-M6 also has additional interru"t mas1in- re-isters +he BA&%*R! re-ister allows interru"ts to of certain "riority level or lower to be bloc1ed, and the $A:;+MA&< "rovides additional fault mana-ement features

*igure 2#&,-Progra%%er+s %ode) differen es !et"een the Cortex-M0.-M,& +he C)(+R); re-ister in the Cortex-M6 also has an additional bit ,bit=0>/ to select whether the thread should be in "rivile-ed or user +hread mode +he x*&R in the Cortex-M6 also has a number of additional bits to allow an interru"ted multi"le load?store instruction to be resumed from the interru"ted transfer and to allow an instruction se3uence ,u" to four instructions/ to be conditionally executed /0IC and 1x eptions& +he ('!C in the Cortex-M6 su""orts u" to 8@0 interru"ts +he number of "riority levels is also confi-urable by the chi" desi-ners, from A levels to 8B6 levels ,in most cases A levels to 68 levels/ +he "riority level settin-s can also be confi-ured into "reem"tion "riority ,for nested interru"t/ and sub"riority ,used when multi"le interru"ts of the same "reem"t "riority are ha""enin- at the same time/ by software )ne of the ma4or differences between the ('!C in the Cortex-M6 and Cortex-M0 is that most of the ('!C re-isters in the Cortex-M6 can be accessed usin- word, half word, or byte transfers #ith the Cortex-M0, the ('!C must be accessed usin- a word transfer $or exam"le, if an interru"t "riority re-ister needs to be u"dated, you need to read the whole word ,which consists of "riority-level settin-s for four interru"ts/, modify 1 byte, and then write it bac1 !n the Cortex-M6, this can be carried out usin- 4ust a sin-le byte-si0e write to the "riority-level re-ister $or users of the CM&!& device driver library, this difference does not cause a software "ortin- issue, as the CM&!& ('!C access function names are the same and the functions use the correct access method for the "rocessor

+he ('!C in the Cortex-M6 also su""orts dynamic chan-in- of "riority levels-in contrast to the Cortex-M0, where the "riority level of an interru"t should not be chan-ed after it is enabled +he Cortex-M6 has additional fault handlers with "ro-rammable "riority levels !t allows the embedded systems to be "rotected by two levels of fault exce"tion handlers ,*igure 2#&2 !e)o"/ #hen used to-ether with the memory "rotection unit in the CortexM6, robust systems can be build for embedded systems that re3uire hi-h reliability

*igure 2#&2- Mu)tip)e )eve)s of fau)t hand)ing in the Cortex-M, +he ('!C in the Cortex-M6 also su""orts the followin- featuresC 0e tor Ta!)e 3ffset Register& +he vector table can be relocated to another address in the C)D% memory re-ion or the &RAM memory re-ion 'oft"are Trigger Interrupt Register& A"art from usin- ('!C !nterru"t *endin- &et Re-ister, the "endin- status of interru"ts can be set usin- this re-ister Interrupt A tive 'tatus Register& +he active status of each interru"t can be determined by software +here are also additional fault status re-isters for indicatin- causes of fault exce"tions and fault addressand an additional exce"tion called the debu- monitor for debu"ur"oses Instru tion 'et& !n addition to the +humb instructions su""orted in the Cortex-M0 "rocessor, the Cortex-M6 also su""orts a number of additional 16-bit and 68-bit +humb instructions +hese include the followin-C 1- &i-ned and unsi-ned divide instructions ,&D!' and :D!'/ &- Com"are and branch if 0ero ,CBE/, com"are and branch if not 0ero ,CB(E/ +- !$-+5%( ,!+/ instruction, allowin- u" to four subse3uence instructions to be conditionally executed based on the status in A*&R /- Multi"ly and accumulate instructions for 68-bit and 6@-bit results

'- Count leadin- 0ero ,C;E/ 0- Bit field "rocessin- instructions for bit order reversin-, bit field insert, bit field clear, and bit field extract 1- +able branch instructions ,commonly used for the switch statement in C/ %- &aturation o"eration instructions 2- %xclusive accesses for multi"rocessor environments 10- Additional instructions that allows hi-h re-isters ,RA and above/ to be used in data "rocessin-, memory accesses, and branches +hese additional instructions allow faster "rocessin- of com"lex data li1e floatin- "oint values +hey also allow the Cortex-M6 to be used in audio si-nal "rocessin- a""lications, real time control systems 34ste5-"e6e- ,eat res +he Cortex-M6 includes a number of system-level features that are not available on the CortexM) +hese include the followin-C 4 Me%or$ prote tion unit 5MP67& A memory access monitorin- unit that "rovides ei-ht memory re-ions %ach memory re-ion can be defined with different locations and si0e, as well as different memory access "ermissions and access behavior !f an access violation is found, the access is bloc1ed and a fault exce"tion is tri--ered +he )& can use the M*: to ensure each tas1 can only access "ermitted memory s"ace to increase system reliability 4 6na)igned %e%or$ a esses. !n the Cortex-M0, all the data transfer o"erations must be ali-ned +his means a word-si0e data transfer must have an address value divisible by @, and half-word data transfer must occur at even addresses +he Cortex-M6 "rocessor allows many memory access instructions to -enerate unali-ned transfers )n the CortexM0 "rocessor, access of unali-ned data has to be carried out by multi"le instructions 4 8it !and regions& +he Cortex-M6 has two bit addressable memory re-ions called the bitband re-ions +he first bit-band re-ion is in the first 1 MB of the &RAM re-ion, and the second one is the first 1 MB of the "eri"heral re-ion :sin- another memory address ran-e called bit-band alias, the bit data in the bit band re-ion can be individually accessed and modified 4 1x )usive a esses& +he Cortex-M6 su""orts exclusive accesses, which are used to handle shared data in multi"rocessor systems such as sema"hores +he "rocessor bus interface su""orts additional si-nals for connectin- to an exclusive access monitor unit on the bus system

)eb g ,eat res +he Cortex-M6 "rovides additional brea1"oints and data watch"oints in its debu- system +he brea1"oint unit can also be used to rema" instruction or literal data accesses from the ori-inal address ,e - , mas1 R)M/ to a different location in the &RAM re-ion +his allows nonerasable "ro-ram memories to be "atched with a small "ro-rammable memory ,*ab-e &1#' be-ow/

Ta!)e 2#&9- :e!ug and Tra e *eature Co%parison !n addition to the standard debu- features, the Cortex-M6 also has trace features +he o"tional %mbedded +race Macrocell ,%+M/ allows information about instruction execution to be ca"tured so that the instruction execution se3uence can be reconstructed on debu--in- hosts +he Data #atch-"oint and +race ,D#+/ unit can be used to -enerate trace for watched data variables or access to memory ran-es +he D#+ can also be used to -enerate event trace, which shows information of exce"tion entrance and exit +he trace data can be ca"tured usin- a trace "ort analy0er such as the ARM Real'iew+race unit or an in-circuit debu--er such as the <eil :;!(<*ro +he Cortex-M6 "rocessor also su""orts software--enerated trace thou-h a unit called the !nstrumentation +race Macrocell ,!+M/ +he !+M "rovides 68 messa-e channels and allows software to -enerate text messa-es or data out"ut Porting between Cortex-M0 and Cortex-M+ Althou-h there are a number of differences between the Cortex-M0 ,ARMv6-M/ and the Cortex-M6 ,ARMv7-M/, "ortin- software between the two "rocessors is usually easy Because the ARMv7-M su""orts all features in the ARMv6-M, a""lications develo"ed for the Cortex-M0 can wor1 on the Cortex-M6 directly, a"art from chan-es that result from their "eri"heral differences ,,ig re &1#' be-ow/

*igure 2#&9- Co%pati!i)it$ !et"een the Cortex-M0 and Cortex-M, pro essors& (ormally, when "ortin- an a""lication from the Cortex-M0 to the Cortex-M6, you only need to chan-e the device driver library, chan-e the "eri"heral access code, and u"date the software for system features li1e cloc1 s"eed, slee" modes, and the li1e *ortin- software from the Cortex-M6 to the Cortex-M0 mi-ht re3uire more effort A"art from switchin- the device driver library, you also need to consider the followin- areasC F ('!C and &CB ,&ystem Control Bloc1/ re-isters in the Cortex-M0 can only be accessed in word-si0e transfers !f any "ro-ram code accesses these re-isters in byte-si0e transfers or half-word transfers, they need to be modified !f the ('!C and &CB are accessed by usin- CM&!& functions, switchin- the CM&!&-com"liant device driver to use the Cortex-M0 should automatically handle these differences F &ome re-isters in the ('!C and the &CB in the Cortex-M6 are not available in the Cortex M) +hese include the !nterru"t Active &tatus Re-ister, the &oftware +ri--er !nterru"t Re-ister, the 'ector +able )ffset Re-ister, and some of the fault status re-isters F +he bit-band feature in the Cortex-M6 is not available in the Cortex-M0 !f the bit-band alias access is used, it needs to be converted to use normal memory accesses and handle bit extract or bit modification by software F !f the a""lication contains assembly code or embedded assembly code, the assembly code mi-ht re3uire modification because some of the instructions are not available on the Cortex-M0 $or C a""lication code, some instructions such as hardware divide are not available in the Cortex-M0 !n this case, the com"iler will automatically call the C library to handle the divide o"eration F :nali-ned data transfer is not available on the Cortex-M0 F &ome instructions available in the Cortex-M6 ,e - , exclusive accesses, bit field "rocessin-/ are not available on the Cortex-M0

&ome Cortex-M0 microcontrollers su""ort a memory rema""in- feature A""lications that use the vector table relocation feature on the Cortex-M6 mi-ht able to use the memory rema""in- feature to handle vector table relocation A""lications that re3uire the user +hread mode or the M*: feature cannot be "orted to the Cortex-M0 because these features are not su""orted in the Cortex-M0 Porting between Cortex-M0 and Cortex-M/ +he Cortex-M@ "rocessor is based on the same architecture as that used for the CortexM6 !t is similar to the Cortex-M6 in many as"ectsC it has the same 5arvard bus architecture, a""roximately the same "erformance in terms of Dhrystone DM!*&?M50, the same exce"tion ty"es, and so on Com"ared to the Cortex-M6, the Cortex-M@ has additional instructions such as sin-le instruction, multi"le data ,&!MD/ instructions, saturation arithmetic instructions, data "ac1in- and extraction instructions, and o"tional sin-le "recision floatin- "oint instructions if a floatin- "oint unit is im"lemented +he floatin- "oint su""ort in the Cortex-M@ is o"tionalG therefore, not all Cortex-M@ microcontrollers will su""ort this feature !f the floatin- "oint unit is included, it includes an additional floatin- "oint re-ister ban1 and additional re-isters, as well as extra bit fields in the x*&R and C)(+R); s"ecial re-isters ,,ig re &1#0 be-ow/ +he floatin"oint unit can be turned on or off by software to reduce "ower consum"tion

*igure 2#&;- Progra%%er+s %ode) of the Cortex-M2 "ith a f)oating point& A"art from these additional instructions, the system features of the Cortex-M@ are similar to those of the Cortex-M6 "rocessor +herefore, the techni3ues for "ortin- software between the Cortex-M0 and the CortexM6 "rocessors can also be used on "ortin- software between the Cortex-M0 and CortexM@ "rocessors 5owever, because of the differences between the nature of the two "rocessors, some a""lications develo"ed for the Cortex-M@ "rocessor ,e - , hi-hend audio "rocessin- or industrial a""lications that re3uire floatin- "oint o"erations/ are unsuitable for the Cortex-M0 "rocessor Joseph Yiu, author of The definitive guide to the ARM Cortex-M0, is a staff engineer at ARM Ltd., Cambridge, U . +o read Part 1, -o to ARM 7+DM! and Cortex-M0 (ext in *art 6C ,ro5 %-$10-bit MCUs to the Cortex-M0 6sed "ith per%ission fro% /e"nes, a division of 1)sevier& Cop$right 20##, fro% <The definitive guide to the ARM Cortex-M0," !$ Joseph Yiu& *or %ore infor%ation a!out this tit)e and other si%i)ar !oo=s, p)ease visit """&e)sevierdire t& o%&