3.

3 MEMORY
1. Every computer needs memory. 1.1 Memory is used for storing both instructions and data. 1.2 Lets examine the basic components of a memory system starting at the gate level.

3.3.1 Latches
2. To have a 1-bit memory, we need a circuit that remembers previous input values. 2.1 You can use NOR gates as in Fig 3-21 (a). 2.1.1 You can make the same kind of circuit using NAND gates (conceptually the same).
S 0 0 1 _ Q S 0 1 0 _ Q

1 R 0 0 (a) Q R

0 0 (b) 1 Q

A 0 0 1 1

B NOR 0 1 1 0 0 0 1 0 (c)

Figure 3-21. (a) NOR latch in state 0. (b) NOR latch in state 1. (c) Truth table for NOR

2.1.2 The circuit of Fig 3-21 (a) is called an SR latch. 2.1.2.1 The circuit has two inputs: S for Setting the latch and R for Resetting (clearing) it. 2.1.2.2 It has two outputs of Q and Not Q which are complementary. 2.1.2.3 Unlike the combinational circuit, the outputs of the latch are not uniquely determined by the current inputs. 2.1.2.4 To see how this happens, assume S and R are 0 (they are 0 most of the time). 2.1.2.5 If Q = 0 then that 0 is fed back into the upper NOR gate and thus both its inputs are 0. 2.1.2.6 That will generate a 1 for the Not Q that, in turn, is fed to the bottom NOR gate and its inputs would be 1 and 0 thus generating a 0 for the Qs output. 2.1.2.7 This state is shown in Fig 3-21 (a). 2.1.3 Now if the Q was not 0 but a 1 with both R and S still 0, the upper gate would have 0 and 1 as input and would generate an output of 0 for Not Q. Page 1 of 1

2.1.3.1 That 0 is fed into the lower gate and the inputs would be 0 and 0 thus generating an output of 1 for Q. 2.1.3.2 That is in Fig 3-21 (b). Note: have Q and Not Q both be 0 or 1 would not last because the NOR gates would force a stable state if Fig 3-21 (a) and Fig 3-21 (b). 2.1.4 Lets try the S or R inputs. 2.1.4.1 If S = 1 while Q = 0, the inputs of the upper gate are then 1 and 0 forcing the Not Q to 0. 2.1.4.2 Then that 0 goes down to the lower gate with both inputs being 0 and forcing Q to be 1. 2.1.4.3 If you set R to 1, nothing happens since Q is already set to 0. 2.1.4.4 Now if Q = 1 and R is set to 1, then the lower gate would have an output Q of 0 and would set the Not Q to 1. 2.1.4.5 So the latch remembers when S or R had been on. 2.2 It is often convenient to change memory only at certain times. 2.2.1 So we modify the circuit to include a clock and AND gates for S and R to get what is called a clocked SR latch.
S

_ Q

Clock

Q R Figure 3-22. Clocked SR latch

2.2.2 In Fig 3-22, the clock is normally 0 that causes the output of both AND gates to be 0, no matter what S and R is. 2.2.2.1 If the clock becomes 1 then the AND gates are activated and S and R values can go through. 2.2.2.2 Despite the name, the clock signal does not need to be driven by a clock. 2.2.2.3 Terms of enable and strobe are used widely to mean the clock is 1 to make the circuit is sensitive to state of S and R.

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2.2.3 There is a problem with both S and R being 1 at the same time: the circuit becomes nondeterministic (i.e. flops around) until S and R become 0. 2.2.3.1 If both S and R become 0 at the same time (likely), then the latch jumps to one of its stable states at random. 2.2.3.2 To prevent SR latchs ambiguity (because of S = R = 1) is to allow only one input of D as in Fig 3-23. If D = 1 and the clock is 1 the latch is driven into state Q = 1. 2.2.3.3 If D = 0 and clock is 1 the latch Q state become 0. 2.2.3.4 In other words when the clock becomes 1, the latch becomes whatever D is. 2.2.3.5 This circuit is called clocked D latch and is a true 1-bit memory. 2.2.3.6 This circuit requires 11 transistors but less obvious designs can be used with as few as six transistors.

_ Q

Figure 3-23. Clocked D latch

3.3.2 Flip-Flops
2.3 Sometimes its necessary to sample the value on a line at a particular instance in time and store it. 2.3.1 This variation is called a flip-flop and the state transition does not occur when the clock is 1 but during the clock transition from 0 to 1 (rising edge) or from 1 to 0 (falling edge). 2.3.2 The length of the clock is unimportant as long as the transitions are fast. 2.3.3 Thus a flip-flop is edge triggered and can be edge triggered and the latch is level triggered (unfortunately the term of flip-flop and latch can be confused by many authors). 2.3.4 There are many ways to design a flip-flop. Page 3 of 3

2.3.4.1 For instance, if there was a way to generate a very short pulse on the rising edge of the clock signal, that signal could be fed into a D latch like in Fig 3-24 (a):
d

b c

b AND c c

(a)

b a Time (b)

Figure 3-24. (a) Pulse generator. (b) Timing at four points in the circuit

2.3.4.2 It might appear that the output of the AND gate would always be zero since AND with an invert would be 0. 2.3.4.3 However, the inverter (NOT gate) has a small but detectable propagation delay which makes the circuit work. 2.3.4.4 If we measure the voltage of a, b, c, and d as shown in Fig 3-25 (b): the input signal of a is a long clock pulse (bottom), the input signal of b is shown above a and it is inverted and slightly delayed by a few nanoseconds. 2.3.4.5 Signal at c is delayed also but only at the speed of light along the distance (for example, 20 microns which would be 0.0001 nsec negligible compared to the inverter so a and c are essentially the same). 2.3.4.6 When the b AND c is done the signals are combined into one short pulse (called ! and is about 5 nsec or less) and d is set a short time later (5 nsec or less also) which is caused by the propagation delay of the AND gate. 2.3.4.7 Figure 3-25 shows the implementation of the D flip-flop:

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D _ Q

Figure 3-25. D flip-flop

2.3.4.8 Note: in real circuits more sophisticated flip-flops are used. 2.3.5 Standard symbols for latches and flip-flops are shown in Fig 3-26. 2.3.5.1 Fig 3-26 (a) is a latch whose state is loaded when the clock, CK, is 1, Fig 3-26 (b) is where the latch is set when the clock, CK, is 0, and Fig 3-26 (c) and (d) are flip-flops indicated by > on the clock, CK. 2.3.5.2 Fig 3-26 (c) changes states on the rising edge of the clock pulse. 2.3.5.3 Fig 3-26 (d) changes states on the falling edge of the clock pulse. 2.3.5.4 Many, but not all, latches and flip-flops also have the NOT Q as output and some have Set or Preset (set Q = 1) and Reset or Clear (set Q = 0).

CK (a)

CK (b)

> CK (c)

> CK (d)

Figure 3-26. D latches and flip-flops

3.3.3 Registers
3 Flip-flops have a variety of configurations. 3.1 Flips-flops can be combined in groups to create registers that have data types with more then 1-bit 3.1.1 Register in Fig 3-27 has 8 flip-flops ganged together to form an 8-bit storage register 3.1.2 Can take an 8 bit input value (I0 to I7) when the clock CK transitions Page 5 of 5

3.1.3 To implement the register, the clock lines are connected to the same input signal, CK, to allow accepting the 8-bit at the same time 3.1.4 The flip-flops themselves are of type Fig 3-26 (d) 3.1.4.1 But the inversion bubbles on the flip-flops are canceled by the inverter tied to the clock signal CK flip-flops are loaded on the rising transition of the clock 3.1.4.2 All eight clear signals are also ganged so that when the clear goes to 0, all flips are forced to their 0 state 3.2 By the way, why have an inverter at the CK and also at each gate? 3.2.1 The input signals may not have enough current to drive all eight flip-flops 3.2.2 The inverters actually are used as amplifiers
O0 I0 O 1 I1 O 2 I2 O 3 I3 CK

> CK CLR

> CK CLR

> CK CLR

> CK CLR

CLR > CK Q D

CLR > CK Q D

CLR > CK Q D

CLR > CK Q D

O4 CLR

I4

O5

I5 O 6

I6 O 7

I7

Figure 3-27. An 8-bit register constructed from single-bit flip-flops

3.3.4 Memory Organization

4 We went from a 1-bit memory in Fig 3-23 to the 8-bit memory of Fig 3-27. 4.1 Now we need larger memories but the organization must be different to be able to address individual words. 4.1.1 Fig 3-28 has a widely-used memory organization that does this. It has a memory with four 3-bit words. 4.1.2 Each operation reads or writes a 3-bit word. 4.1.3 While the total memory is 12 bits and hardly larger than the octal flipflops it has fewer pins and the design extends to larger memories.

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4.2 Fig 3-28 is not as complicated as it looks. 4.2.1 It has eight input lines and three output lines. 4.2.2 Three inputs are data: I0, I1, and I2. Two inputs are for the address: A0 and A1. 4.2.3 Finally, three inputs are for control: CS for Chip Select, RD for distinguishing between read and write, and OE for Output Enable. 4.2.4 The three outputs are for data: O0, O1, and O2. In principle this could be packaged with 14 pins verses the 20 pins for the octal flip-flops. 4.2.5 Set the CS high and the RD high (logical 1) for read and low (logical 0) for write. 4.2.6 The two address lines must be set to select which of the four 3-bit words to read or write. 4.2.7 For the read, the data input lines are not used but the data is placed on the data output lines. 4.2.8 For the written, the data input lines are loaded into the selected memory word and the data output lines are not used. 4.3 With Fig 3-28 has four word-select AND gates at the left of the memory that form a decoder. 4.3.1 The input inverters are placed so that each gate is enabled (output high) by a different address. 4.3.2 Each gate signals a word select line from top to bottom for words 0, 1, 2, and 3. 4.3.3 When chip has been selected for a write, the vertical line for CS * Not RD is high thus enabling one of the four write gates depending on which word select line is high. 4.3.4 The output of the write gate drives all the CK signals for the selected word thus doing a write to the selected flip-flops (only is CS is high and RD is low and the word is selected via A0 and A1). 4.4 Read is like the write: the address decoding is exactly the same but the CS * Not RD is low so all the write gates are disabled and none of the flip-flops are modified. 4.4.1 The word select line is selected that enables the AND gates tied to the Q bits of the selected word and that word outputs its data into the four-input OR gates at the bottom of the figure while the three other words output 0s.

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Data in I2 I1 I0 Write gate D >CK Q D >CK Q D >CK Q Word 0

Word 0 select line

D >CK

D >CK

D >CK

Word 1

A1 A0

Word 1 select line

D >CK

D >CK

D >CK

Word 2

Word 2 select line

D >CK

D >CK

D >CK

Word 3 __ CS * RD

CS O2 RD O1 O0 Output enable = CS * RD * OE

OE

Figure 3-28. Logic diagram for a 4 X 3 memory. Each row is one of four 3-bit words. A read or write operation always reads and writes a complete word.

4.4.2 We could have problems with the output lines if we used only OR gates since the values could be outputted while a write is being done or interfere in another way. 4.4.2.1 We need a switch to disconnect the OR gates on writes. 4.4.2.2 The switches exist and are shown in Fig 3-29.

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4.4.3 The noninverting buffer is in Fig 3-29 (a) and shows that is has a data input and a control. 4.4.3.1 When the control is high, the buffer is like a wire as shown in Fig 3-29 (b). 4.4.3.2 But if the control is low, the buffer acts like an open circuit in Fig 3-29 (c) like someone took a wirecutter to the circuit. If the control sign is high again, in just a few nanoseconds the connection is restored. 4.4.3.3 Fig 3-29 (d) shows an inverting buffer that acts like a normal inverter when the control is high else will disconnect if the control is low. 4.4.3.4 Both kinds of buffers are tri-state devices: 0, 1, or none (open circuit). 4.4.4 So the three noninverting buffers on Fig 3-28 are for outputting data when CS, RD, and OE are all true and off when not.
Data in Data out

Control (a) (b) (c) (d)

Figure 3-29. (a) Noninverting buffer. (b) Effect of (a) when control is high. (c) Effect of (a) when control is low. (d) Inverting buffer.

3.3.5 Memory Chips The memory of Fig 3-29 nicely extends to larger sizes. It was a 4 X 3 memory four words of 3 bits each. To extend to 4 X 8 we need only five more columns of four flipflops and five more input lines and five more output lines. Or we could do 8 X 3 where we add four more rows of three flip-flops each as well as another address line of A2. Number of words for memory should be a multiple of 2 for efficiency but the number of bits per word can be any size. The number of bits per chip increases according to Moores law. However, that does not necessarily mean the older chips are no longer used because of trade-offs of price, capacity, power, and interfacing convenience. Typically, the largest chips are the most expensive than the older smaller chips. There are various ways of organizing memory. Fig 3-31 has two possible ways to organize 4 Mbit: 512K X 8 and 4096K X 1 (note: memory chips are quoted in bits). Fig 3-31 (a) has 19 address lines to address one of 219 bytes and eight data lines for loading or storing the byte selected.

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Some pins the high voltage causes an action to happen and on others it is low voltage. To avoid confusion, well say a signal is asserted, rather than goes high or low, to cause an action. Pins that are asserted when the voltage is low will have a bar over it. Thus: __ CS is for high voltage for assert and CS is for low voltage for assert (or not CS).

The opposite of asserted is negated when nothing is happening, the pins are negated. Since a computer has many memory chips, you need to be able to select a particular chip. The Not CS signal is used to select a chip. It also needs a way to know whether to read or write to the chip. The Not WE (Write Enable) signal being asserted will tell the chip the data is being written and not read. The Not OE (Output Enable) signal is asserted to drive the output signals. When not assert, the chip output is disconnected from the circuit. Fig 3-31 (b) uses a different addressing scheme. This chip is organized internally as 2048 X 2048 matrix of 1-bit cells for 4 Mbits. To address the chip, first a row is selected by putting its 11-bit number on address pins. The Not RAS (Row Address Strobe) is asserted. Then a column number is put on the address pins and Not CAS (Column Address Strobe) is asserted. Then the chip can accept or output one data bit. Larger memories frequently use n x n matrices that are addressed by row and column. This reduces the number of pins required but also makes addressing the chip slower since you need two addressing cycles one for row and one for column. To get the speed back, at least partly, some memory chips can be given a row address followed by a sequence of column addresses to get consecutive bits in a row. Page 10 of 10

Large memory chips were often organized like Fig 3-31 (b). But as memory words went from 8 bits to 32 bit and beyond, 1-bit wide chips began to be inconvenient. For a 32-bit word from 4096 X 1 chips needed 32 chips in parallel. With 512K chips needs only four chips in parallel and allows memories as small as 2 MB. So most manufacturers now have 4-, 8-, and 16-bit widths. Two examples of modern 512-Mbit chips are shown in Fig 3-32. Design of Fig 3-32 (a) is a 32M X 16 design with 13 lines for Not RAS signal, 10 lines for the Not CAS signal, and 2 lines for the bank select. That makes 25 signals to allow each of the 225 internal 16bit cells to be addressed. However, Fig 3-32 (b) is a 128M X 4 design with 13 lines for Not RAS signal, 12 lines for Not CAS signal,, and 2 lines for bank select. 27 signals allow selecting any of the 227 internal 4-bit cells to be addressed. How many rows and columns would be an engineering reason and the matrix need not be square.

3.3.6 RAMs and ROMs Memories we looked at thus far can be read and written and are called RAMs (Random Access Memories) a bit of a misnomer since all memory chips are randomly accessed. RAMs are either static or dynamic. Static RAMs (SRAMs) are constructed internally using circuits like the basic D flip-flop. Their memories are retrained as long as the power is kept on (seconds, minutes, hours, days, etc). Static RAMs are very fast and the typical access time is a few nsec. They are popular as level 2 cache memory. Page 11 of 11

Dynamic RAMs (DRAMs) do not use flip-flops. They use an array of cells with each cell with one transistor and a tiny capacitor. Capacitors are charged or discharged to hold a 0 or a 1. But electric charge tends to leak out so each bit in a dynamic RAM must be refreshed (reloaded) every few milliseconds to keep the data. Dynamic RAMs need more complex interfacing that static ones but this disadvantage is compensated for their larger capacities. That is because dynamic RAMs need only one transistor and one capacitor verses six transistors per bit for the best static RAM. Main memories are nearly always built out of dynamic RAMs but they are slow (tens of nanoseconds). Having both dynamic RAMs (main memory chips) and static RAMs (cache) help to combine the good properties of both. There are several type of dynamic RAM. Oldest type is FPM (Fast Page Mode) DRAM. It is a matrix of bits and works by having the hardware present a row address and then step through the column addresses using the Not RAS and Not CAS like in Fig 3-31. Explicit signals tell the memory when it is time to respond so the memory would run asynchronously to the main system clock. FPM DRAM was replaced with EDO (Extended Data Output) DRAM that allowed a second memory reference to begin before the previous memory reference was done. That did not make a single memory reference go faster but did improve memory bandwidth more words per second. When cycle times of 12 nsec and slower were common, FPM and EDO worked well. But when processors got so fast that faster memories were needed, FPM and EDO were replaced by SDRAM (Synchronous DRAM) which is a hybrid of static and dynamic RAM and is driven by the main system clock. Big advantage of SDRAM is that the clock eliminates the need for control signals to tell the memory chip when to respond. Instead the CPU tells the memory how many cycles it should run then starts it. This increases the data rate between CPU and memory. Next improvement over SDRAM was DDR (Double Data Rate) SDRAM. This kind of memory produces output on both the rising edge of the clock and the falling edge thus doubling the data rate. An 8-bit wide DDR chip running at 200 MHz outputs two 8-bit values 200 million times a second (burst only) thus giving a theoretical burst rate of 3.2 Gbps. RAMs are not the only kind of memory chips. Many times, like in toys, appliances, and cars, the program and some data must remain stored even with the power off. And that program and data are not ever changed. We need ROMs (Read-Only Memories) that cannot be changed or erased. Data in ROM are inserted during its manufacture by exposing a photosensitive material through a mask containing the desired bit pattern then etching away the exposed or unexposed surface. Can only change the program in ROM by replacing the entire chip. ROMs are much cheaper than RAMs when ordered in large enough volumes. But they are inflexible because they cannot be changed after manufacture and it can take weeks from the order to getting the ROMs. So to make it easier for companies to develop new Page 12 of 12

ROM-based products, PROM (Programmable ROM) was invented. In the field, the PROM can be programmed once and eliminate the turnaround time. PROMs have an array of tiny fuses inside. A specific fuse can be blown out by selecting its row and column and applying a high voltage to a certain pin on the chip. The next development would be an EPROM (Erasable PROM) that is field-programmed but also field-erased. It has a quartz window on the chip that when strong ultraviolet light is shown on it for 15 minutes then all the bits are set to 1. If many changes are done, EPROMs are quite economical because they can be reused. EPROMs have the same organization as static RAMs. Even better than the EPROM is the EEPROM that can be erased by applying pulses to it instead of using ultraviolet light. The EEPROM can be programmed in place (better than placing the EPROM in a special EPROM programming device). But EEPROMs are only 1/64 as large as common EPROMS and only half as fast. EEPROMs cannot compete with DRAMs or SRAMs because they are 10 times slower, 100 times smaller in capacity, and much more expensive. They are used only in situations where nonvolatility is needed. Most recent kind of EEPROM is flash memory. Flash memory is block erasable and rewritable. Like EEPROM, flash memory an be erased without removing it from the circuit. Many manufacturers produce small printed circuit cards up to 1 GB of flash memory on them for film for storing pictures in digital cameras and other purposes. Flash memories may replace disk drives and thus improve storage access since they have a 50-nsec access time. The problem with flash memory is that they wear out after about 100,000 erasures whereas disks last for years no matter how often they are rewritten. A summary of various kinds of memories are in Fig 3-33. Type SRAM DRAM SDRAM ROM PROM EPROM EEPROM Flash Byte Category Erasure alterable Volatile Typical use Read/write Electrical Yes Yes Level 2 cache Read/write Electrical Yes Yes Main memory (old) Read/write Electrical Yes Yes Main memory (new) Read-only Not possible No No Large volume appliances Read-only Not possible No No Small volume equipment Read-mostly UV light No No Device prototyping Read-mostly Electrical Yes No Device prototyping Read/write Electrical No No Film for digital camera Figure 3-33. Comparison of various memory types

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