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Synopsys Tutorial: Power Estimation - CVL Wiki

Synopsys Tutorial: Power Estimation

From CVL Wiki
Power Estimation with OSU Standard Cell Library and Synopsys tools (PrimeTime-Px) By Syed Haider

Contents
1 Note 2 Setting Up Standard Cell Library and Project Directory 3 Sample Design Example 4 Test Bench and VCD Output 5 Synthesize Design with Synopsys Design Vision 6 Simulate Design and Get Switching Activity (VCD file) 7 Power Estimation with Synopsys PrimeTime-PX 7.1 Explanation of Power Script

Note
It has come to my attention that copying text from a wiki to text files sometimes leads to the insertion of hidden characters. So if the tools experience trouble with the scripts or hdl code copied from this wiki, just retype the files shown and the tools should have no trouble.

Setting Up Standard Cell Library and Project Directory

1. Download Oklahoma State University Library from http://vcag.ecen.okstate.edu/projects/scells/ Specifically, from: http://vcag.ecen.okstate.edu/projects/scells/download/iit_stdcells_v2.3beta/ Download the iitcells_lib_2.3.tar.gz package. 2. untar the library somewhere nice like your home directory where you will really never touch it (i.e. /home/syedh/). The Directory will be called iit_stdcells. 3. Create a project directory somewhere else. (example: mkdir /home/syedh/Project1) In Project1 create another directory called WORK. 4. Back in Project1 directory create an empty file called: .synopsys_dc.setup This file will specify to Synopsys and design_vision software what libraries you are using. A sample version of the file is listed below. The path after /home/syedh/ should remain unchanged if this tutorial is being followed correctly!!!

#. s y n o p s y s _ d c . s e t u pf i l e #D e f i n et h et a r g e tt e h c n o l o g yl i b r a r y ,s y m b o ll i b r a r y , #a n dl i n kl i b r a r i e s s e tt a r g e t _ l i b r a r y/ h o m e / s y e d h / i i t _ s t d c e l l s / l i b / t s m c 0 1 8 / l i b / i i t 0 1 8 _ s t d c e l l s . d b # d on o th a v eas y m b o ll i b r a r y # s e ts y m b o l _ l i b r a r y # s e tl i n kl i b r a r y( s e ta ss a m ea st a r g e tl i b r a r y ) s e tl i n k _ l i b r a r y / h o m e / s y e d h / i i t _ s t d c e l l s / l i b / t s m c 0 1 8 / l i b / i i t 0 1 8 _ s t d c e l l s . d b* s e td e s i g n e r" Y o u rN a m e "

5. Copy /home/syedh/iit_stdcells/lib/tsmc018/lib/iit018_stdcells.v into Project1 Directory.

Sample Design Example

6. Now it is design time. Create verilog description of something amazing. Here is a design of a full adder and some registers that spans multiple design files (full_adder.v, top.v):
/ / f u l l _ a d d e r . v / / T h i si sam o d u l ef o ra1b i tF u l lA d d e r m o d u l ef u l l _ a d d e r ( a , b ,c _ i n ,s ,c _ o u t ) ; i n p u ta ,b ,c _ i n ; o u t p u tw i r es ,c _ o u t ; a s s i g ns=a^b^c _ i n ; a s s i g nc _ o u t=( ( a&b ) )|( c _ i n&( a ^ b ) ) ;

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e n d m o d u l e

Synopsys Tutorial: Power Estimation - CVL Wiki

/ / t o p . v / / T h i sc o n t a i n saf u l la d d e rw i t hs o m er e g i s t e r sf o ri n p u ta n do u t p u t . ` t i m e s c a l e1 n s / 1 0 p s m o d u l et o p( c l k ,a ,b ,c _ i n ,s u m ,c _ o u t ) ; i n p u tc l k ,a ,b ,c _ i n ; o u t p u ts u m ,c _ o u t ; r e gi n _ a ; r e gi n _ b ; r e gs u m _ r e g ; r e gc _ o u t _ r e g ; r e gc _ i n _ r e g ; f u l l _ a d d e rf a 1 ( . a ( i n _ a ) ,. b ( i n _ b ) ,. c _ i n ( c _ i n _ r e g ) ,. s ( s u m ) ,. c _ o u t ( c _ o u t ) ) ; a l w a y s@ ( p o s e d g ec l k ) b e g i n i n _ a=a ; i n _ b=b ; c _ i n _ r e g=c _ i n ; c _ o u t _ r e g=c _ o u t ; s u m _ r e g=s u m ; e n d e n d m o d u l e

Test Bench and VCD Output

7. Now it is time to create a test bench file to test the design. The things that will be highlighted in purple are system tasks that will create dumps (value change dumps) of signals in your design. The system tasks will produce a VCD file during simulation that will contain switching activity needed for power estimation.
/ / t b _ t o p . v / / t e s t b e n c h ` t i m e s c a l e1 n s / 1 0 p s m o d u l et b _ t o p ( ) ; r e gc l k ; r e ga ,b ,c _ i n ; w i r ec _ o u t ,s u m ; / / c l o c k i n gd e s c r i p t i o n i n i t i a l b e g i n c l k=0 ; e n d

/ / c l o c kp e r i o di s# 1 0 0 a l w a y sb e g i n # 5 0 c l k=~ c l k ; e n d / / i n i t i a l i z ei n p u tt of u l la d d e r i n i t i a lb e g i n a=0 ; b=0 ; c _ i n=0 ; e n d / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / /T o g g l et h ei n p u t sa tv a r y i n gr a t e s / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / t o g g l ec a r r y _ i n i n i t i a lb e g i n # 6 0 ; r e p e a t( 5 0 ) b e g i n c _ i n< =~ c _ i n ; # 1 0 0 ; e n d e n d / / t o g g l ea i n i t i a lb e g i n # 6 0 ; r e p e a t( 2 5 ) b e g i n a< =~ a ; # 2 0 0 ; e n d e n d / / t o g g l eba n ds e t u pv c dd u m p i n i t i a lb e g i n $ d u m p f i l e ( " d m p _ t o p . v c d " ) ; $ d u m p v a r s ( 0 , t o p ) ; / / r e a dv e r i l o gb o o kf o rm o r ei n f oo ns y s t e mc o m m a n d # 6 0 ; $ d u m p o n ; r e p e a t( 1 0 ) b e g i n b< =~ b ; # 5 0 0 ; e n d $ d u m p o f f ; $ f i n i s h ; / / e n d ss i m u l a t i o n

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e n d

Synopsys Tutorial: Power Estimation - CVL Wiki

/ / M o d u l eu n d e rt e s t t o pu u t ( . c l k ( c l k ) ,. a ( a ) ,. b ( b ) ,. c _ i n ( c _ i n ) ,. s u m ( s u m ) ,. c _ o u t ( c _ o u t ) ) ; e n d m o d u l e

Synthesize Design with Synopsys Design Vision

8. Now comes the time to create a synthesized top level design from {full_adder.v top.v}. We are interested in creating a synthesized version of top. At command prompt type the following:
S y n o p s y s d e s i g n _ v i s i o n

Now a design_vision gui has started up. In this gui follow these steps:

In Menu: File --> Analyze. A Dialog box will appear called Analyze Designs. Click the Add.. button and add every design file {full_adder.v top.v}. You can do this one file at a time or all at one time by using the CTRL key to select multiple files. After adding all the files press OK.

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In Menu: Design --> Elaborate. A Dialog box will appear called Elaborate Designs. There will be a drop down selection menu called Design. In this selection menu there will be two objects listed: top(verilog) and full_adder(verilog). Make sure that top(verilog) is selected. Press OK.

Now in the Design Vision the Hier 1 window will have objects listed in it.

In Menu: Design --> Compile. In the dialog box that shows up press OK. After doing this your design will now have parts from the library in it.

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In Menu: File --> Save As. Save the design as a verilog design with a new name (ex. top_syn.v). 9. Exit the gui and in the command prompt type exit to quit out of the design_vision_xg_t shell. Then type exit again to quit Synopsys.

Simulate Design and Get Switching Activity (VCD file)

10. Now it is time to simulate the synthesized design, top_syn.v, with the testbench, tb_top.v. The verilog simulator program of Synopsys is called VCX. The first step is to write a script for the simulation:
# v c s _ s c r i p t . s c r # T h i si sas c r i p tf i l ef o rV C Xs i m u l a t o r . / t b _ t o p . v . / t o p _ s y n . v v. / i i t 0 1 8 _ s t d c e l l s . v + l i b e x t + . v+ n o l i b c e l l+ d e f i n e + V P D + S A I F + V C D + S D F

11. At command prompt type:

S y n o p s y s

Now type:
v c sfv c s _ s c r i p t . s c r

The result of running this command is that an executable called simv is created. 12. Run simv :
. / s i m v

13. Now the file dmp_top.vcd has been created.

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Power Estimation with Synopsys PrimeTime-PX

14. Now we will use a tool called PrimeTime-Px to get power estimation. The following script called power.scr will be used.
# p o w e r . s c r s e tp o w e r _ e n a b l e _ a n a l y s i sT R U E s e tt a r g e t _ l i b r a r y" / h o m e / s y e d h / i i t _ s t d c e l l s / l i b / t s m c 0 1 8 / l i b / i i t 0 1 8 _ s t d c e l l s . d b " s e tl i n k _ l i b r a r y" / h o m e / s y e d h / i i t _ s t d c e l l s / l i b / t s m c 0 1 8 / l i b / i i t 0 1 8 _ s t d c e l l s . d b* " r e a d _ d b$ t a r g e t _ l i b r a r y r e a d _ v e r i l o gt o p _ s y n . v c u r r e n t _ d e s i g nt o p l i n k r e a d _ v c dd m p _ t o p . v c ds t r i p _ p a t ht b _ t o p / u u t c r e a t e _ p o w e r _ w a v e f o r m s o u t p u tv c d r e p o r t _ p o w e r

Explanation of Power Script

1. 2. 3. 4. 5. 6. 7. 8. This script first sets up the libraries that PrimeTime will use, similar to the .synopsys_dc.setup file. The read_db command reads (analyze & elaborates) the libraries. The read_verilog command will now load the verilog design file on which we are interested on performing power analysis. The current_design command picks out a particular module from the design file read and sets it as the focus of power analysis The link command now takes the current design and links it with the link_library. In the read_vcd command the -strip_path option isolates the switching activity related to the module of our focus and annotates the design with that activity. create_power_waveforms is a command needed to run to get peak power. report_power generates the power report.

15. At the Synopsys command prompt type:

p t _ s h e l l

Now run the power.scr:

s o u r c ep o w e r . s c r

16. If all went right the output from the script should look something like this:
= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = S u m m a r y : T o t a ln u m b e ro fn e t s=1 1 N u m b e ro fa n n o t a t e dn e t s=1 1( 1 0 0 . 0 0 % ) T o t a ln u m b e ro fl e a fc e l l s=7 N u m b e ro ff u l l ya n n o t a t e dl e a fc e l l s=7( 1 0 0 . 0 0 % ) = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = I n f o r m a t i o n :T h ew a v e f o r mo p t i o n sa r e : F i l en a m e : p o w e r _ w a v e s . f s d b F i l ef o r m a t : f s d b T i m ei n t e r v a l : 0 . 0 1 n s H i e r a r c h i c a ll e v e l : a l l I n f o r m a t i o n :P o w e ra n a l y s i si sr u n n i n g ,p l e a s ew a i t. . . I n f o r m a t i o n :a n a l y s i si sd o n ef o rt i m ew i n d o w( 0 n s-5 0 5 0 n s ) * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * R e p o r t:E v e n tB a s e dP o w e r D e s i g n:t o p V e r s i o n :Z 2 0 0 7 . 0 6 S P 3 D a t e :W e dF e b1 31 4 : 3 4 : 1 12 0 0 8 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *

A t t r i b u t e s i - I n c l u d i n gr e g i s t e rc l o c kp i ni n t e r n a lp o w e r u - U s e rd e f i n e dp o w e rg r o u p I n t e r n a l S w i t c h i n g L e a k a g e T o t a l P o w e rG r o u p P o w e r P o w e r P o w e r P o w e r ( % ) A t t r s i o _ p a d 0 . 0 0 0 0 0 . 0 0 0 0 0 . 0 0 0 0 0 . 0 0 0 0(0 . 0 0 % ) m e m o r y 0 . 0 0 0 0 0 . 0 0 0 0 0 . 0 0 0 0 0 . 0 0 0 0(0 . 0 0 % ) b l a c k _ b o x 0 . 0 0 0 0 0 . 0 0 0 0 0 . 0 0 0 0 0 . 0 0 0 0(0 . 0 0 % ) c l o c k _ n e t w o r k 3 . 2 9 2 e 0 6 0 . 0 0 0 0 0 . 0 0 0 03 . 2 9 2 e 0 6( 5 8 . 6 7 % ) i r e g i s t e r 6 . 7 2 2 e 0 74 . 7 3 5 e 0 74 . 8 2 2 e 1 01 . 1 4 6 e 0 6( 2 0 . 4 2 % ) c o m b i n a t i o n a l 8 . 6 4 0 e 0 73 . 0 8 6 e 0 74 . 0 3 7 e 1 01 . 1 7 3 e 0 6( 2 0 . 9 0 % ) s e q u e n t i a l 0 . 0 0 0 0 0 . 0 0 0 0 0 . 0 0 0 0 0 . 0 0 0 0(0 . 0 0 % ) N e tS w i t c h i n gP o w e r =7 . 8 2 1 e 0 7 C e l lI n t e r n a lP o w e r =4 . 8 2 8 e 0 6 C e l lL e a k a g eP o w e r =8 . 8 5 9 e 1 0 T o t a lP o w e r =5 . 6 1 1 e 0 6 XT r a n s i t i o nP o w e r G l i t c h i n gP o w e r = 0 . 0 0 0 0 =2 . 1 5 2 e 0 8 ( 1 3 . 9 4 % ) ( 8 6 . 0 5 % ) (0 . 0 2 % ) ( 1 0 0 . 0 0 % )

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P e a kP o w e r P e a kT i m e =4 . 7 2 6 e 0 3 = 5 5 0 . 1 0 0

Synopsys Tutorial: Power Estimation - CVL Wiki

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