St' MIC"AEL COLLEGE OF ENGINEERING & TEC"NOLOG$

:ALA$AR:OIL - 9(0 ,,1 A. ISO *001: 200; Certi<ie= I.stituti3.

St' MIC"AELa) COLLEGE ENGINEERING & TEC"NOLOG$ placementOF and its algorithm.%#)

b) 2ortioning and its algorithm. %#)

St' MIC"AEL COLLEGE OF ENGINEERING & TEC"NOLOG$
:ALA$AR:OIL - 9(0 ,,1 A. ISO *001: 200; Certi<ie= I.stituti3.

:ALA$AR:OIL - 9(0 ,,1 A. ISO *001: 200; Certi<ie= I.stituti3.

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING CENTRALIZED INTERNAL TEST II St' MIC"AEL COLLEGE OF ENGINEERING & TEC"NOLOG$ :ALA$AR:OIL - 9(0 ,,1 Register Number:
A. ISO *001: 200; Certi<ie= I.stituti3.

ET7201 !LSI ARC"ITECT#RE AND DESIGN MET"ODOLOGIES $e%r & SEM: I M'E &II D%te : '0('201) Time: *'10 10')0AM M%r+s: ,0 m%r+s PART - A A.s/er %00 t1e 2uesti3.s 4,5 2 6 10m%r+s7

333334)) 56( .(*533333

1) Define global routing. What are all the main objectives of global routing? 2) What is meant by multilevel rouing? 3) What are the data types in Verilog? ) What are the bit!ise operators in Verilog? ") Define test bench and !aveform generation.
PART - 8 415 9 6 9 M%r+s7 DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING CENTRALIZED INTERNAL TEST II Register Number: ET7201 !LSI ARC"ITECT#RE AND DESIGN MET"ODOLOGIES $e%r & SEM: I M'E &II D%te : '0('201) Time: *'10 10')0AM M%r+s: ,0 m%r+s PART - A A.s/er %00 t1e 2uesti3.s 4,5 2 6 10m%r+s7

#) What is po!er routing and e$plain detail?%#) %&r) ') ($plain the design procedure for V)*+ design flo! and its flo!chart.%#)
PART - C 4 25 12 6 2)M%r+s7

1) Define global routing. What are all the main objectives of global routing? 2) What is meant by multilevel rouing? 3) What are the data types in Verilog? ) What are the bit!ise operators in Verilog? ") Define test bench and !aveform generation.
PART - 8 415 9 6 9 M%r+s7

,) Write short notes on follo!ing !ith neat diagram a) -ate level modeling% ) b) .ehavioral modeling% ) c) Data flo! modeling % ) %&r) /) Write the program for ripple carry adder using structural modeling and gate level modeling.%12) 10) ($plain the different 1ind of routing in detail !ith its neat diagram.%12) %&r) 11) Define follo!ing !ith its types

#) What is po!er routing and e$plain detail?%#) %&r) ') ($plain the design procedure for V)*+ design flo! and its flo!chart.%#)
PART - C 4 25 12 6 2)M%r+s7

,) Write short notes on follo!ing !ith neat diagram d) -ate level modeling% ) e) .ehavioral modeling% )

f) Data flo! modeling % ) %&r) /) Write the program for ripple carry adder using structural modeling and gate level modeling.%12) 10) ($plain the different 1ind of routing in detail !ith its neat diagram.%12) %&r) 11) Define follo!ing !ith its types a) placement and its algorithm.%#) b) 2ortioning and its algorithm. %#)

333334)) 56( .(*533333