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TITLE
DIGITAL DESIGN INSTRUCTIONS
STEPS TO COMPILE AND SIMULATE THE
VERILOG
STEPS FOR SYNTHESIS
PROGRAMS
1. Write a Verilog code and Test bench for an inverter,
observe the waveform and synthesise the code with
technological library with given constraints. Do the initial timing
verification with gate level simulation?
2. Write Verilog code and Test bench for a buffer, observe the
waveform and synthesise the code with technological library
with given constraints. Do the initial timing verification with gate
level simulation?
3. Write Verilog code and test bench for a Transmission Gate,
observe the waveform and synthesise the code with
technological library with given constraints. Do the initial timing
verification with gate level simulation?
4. Write Verilog code and test bench for a Basic/Universal
gates, observe the waveform and synthesise the code with
technological library with given constraints. Do the initial timing
verification with gate level simulation?
5a. Write Verilog code and test bench for an SR flip-flop,
observe the waveform and synthesise the code with
technological library with given constraints. Do the initial timing
verification with gate level simulation?
5b. Write Verilog code and test bench for a D flip-flop, observe
the waveform and synthesise the code with technological
library with given constraints. Do the initial timing verification
with gate level simulation?
5c. Write Verilog code and test bench for a JK flip-flop,
observe the waveform and synthesise the code with
technological library with given constraints. Do the initial timing
verification with gate level simulation?
5d. Write Verilog code and test bench for an MS-JK flip-flop,
observe the waveform and synthesise the code with
technological library with given constraints. Do the initial timing
verification with gate level simulation?
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5e. Write Verilog code and test bench for a T flip-flop, observe
the waveform and synthesise the code with technological
library with given constraints. Do the initial timing verification
with gate level simulation?
6a. Write Verilog code and test bench for a Serial Adder,
observe the waveform and synthesise the code with
technological library with given constraints. Do the initial timing
verification with gate level simulation?
6b. Write Verilog code and test bench for a Parallel Adder,
observe the waveform and synthesise the code with
technological library with given constraints. Do the initial timing
verification with gate level simulation?
7a. Write Verilog code and test bench for a Synchronous 4bitcounter, observe the waveform and synthesise the code
with technological library with given constraints. Do the initial
timing verification with gate level simulation?
7b. Write Verilog code and test bench for aAsynchronous 4bitcounter, observe the waveform and synthesise the code
with technological library with given constraints. Do the initial
timing verification with gate level simulation?
ANALOG DESIGN
STEPS FOR THE ANALOG LAB
BUILDING THE TEST DESIGN FOR THE CELL
STEP TO SIMULATE
STEPS FOR LAYOUT
1.Design an Inverter with given specifications, completing the
design flow mentioned below:
a. Draw the schematic and verify the following
i. DC Analysis
ii.
Transient Analysis
b. Draw the Layout and verify the DRC, ERC
c. Check for LVS
d. Extract RC and back annotate the same and verify the
Design
e. Verify &Optimise for Time, Power and Area to the given
constraint.
2.Design the following circuits with given specifications,
completing the design flow mentioned below:
a. Draw the schematic and verify the following
i. DC Analysis
ii.
Transient Analysis
b. Draw the Layout and verify the DRC, ERC
c. Check for LVS
d. Extract RC and back annotate the same and verify the
Design
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DIGITAL DESIGN
ASIC-DIGITAL DESIGN FLOW:
INSTRUCTIONS
To source the cadence tools type source cshrc.mainin the command line
Get into the VLSI_LAB directory by typing cd VLSI_LAB in the command line
The verilog code should be written inside the rtl directory and test bench code in the
test_bench directory and simulation to be done in the simulation directory.
Enter into the rtl directory to write the verilog code by typing cd rtl in command line
Eg: viinverter.v
To type the code in the vi editor press I, which will get into the insert mode.
After writing the code press esc to exit from the insert mode
o To save the file type :w
o To exit the editor type :q!
6
To exit from the current directory type cd ../in the command line.
Enter into the test_bench directory to write the test bench code by typing cd
test_bench in command line
To type the code in the vi editor press i, which will get into the insert mode.
After writing the code press esc to exit from the insert mode
o To save the file type :w
o To exit the editor type :q!
o Or to save and exit type :wq
To exit from the current directory type cd ../in the command line.
To simulate the program enter into the simulation directory by typing cd
simulationin command line
To verify and run the verilog code in the cadence tool type
irun<path of verilog code><path of test bench code> -access +rwc gui
eg: irun ../rtl/inverter.v ../test_bench/inverter_tb -access +rwc gui
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Now the tool will verify the codes one by one and open a simulation window if there
is no error. Here you can check your respective waveforms.
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Copy the verilog code from the rtl directory to rtl directory inside rclabs by typing:
cp /home/userA1/VLSI_LAB/rtl/*.v /home/userA1/VLSI_LAB/rclabs/rtl.
(this command can be typed either before entering rclabs or after entering rclabs).
Inside rclabsgo to work directory.
Inside work directory type vi constraints_{name}.g
E.g.: viconstraints_inverter.g
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Type rc gui in command prompt which will open a RTL compiler window, and the
command prompt changes to rc command prompt illustrated below:
rc:/>
Set the paths for library and hdl files by giving command below:
set_attrlib_search_path<location of library>
set_attrhdl_search_path<location of verilog code>
eg:
set_attrlib_search_path ../lib
set_attrhdl_search_path ~/VLSI_LAB/rtl
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In order to perform synthesis we must first read that hdl file using following
command:
read_hdl {<hdl file>}
eg: read_hdl {ms_d.vdl.v}
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PROGRAM-1
1. Write a Verilog code and Test bench for an inverter, observe the waveform and
synthesise the code with technological library with given constraints. Do the initial
timing verification with gate level simulation?
Verilog:
`timescale 1ns / 1ps
Module invt(a, y);
input a;
output y;
assign y= ~a;
endmodule
TESTBENCH:
`timescale 1ns / 1ns
Module invt_tb;
reg a;
wire y;
invt uut (.a(a), .y(y));
initial
begin
a = 0;
#100;
a=1;
#100;
a=0;
#100;
a=1;
#100;
a=0;
end
initial
$display(time=%d,$time,input=a,output=y);
endmodule
CONSTRAINTS:
set_input_delay -max 1.0 [get_port "a"]
set_output_delay -max 1.0 [get_port "y"]
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RESULT:
WAVEFORMS:
23
REPORT
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PROGRAM- 2
2. Write Verilog code and Test bench for a buffer, observe the waveform and
synthesise the code with technological library with given constraints. Do the initial
timing verification with gate level simulation?
Verilog
`timescale 1ns / 1ns
module buffer(in, out);
input in;
output out;
wire q1;
invt inst0(in, q1);
invt inst1(q1,out);
endmodule
Testbench:
`timescale 1ns / 1ns
Module buffer_tb;
reg in;
wire out;
buffer uut (.in(in), .out(out));
initial
begin
#100;in=0;
#100;in=1;
end
endmodule
CONSTRAINTS:
set_input_delay -max 1.0 [get_port "in"]
set_output_delay -max 1.0 [get_port "out"]
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REPORT
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RESULT:
WAVEFORMS:
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PROGRAM- 3
3. Write Verilog code and test bench for a Transmission Gate, observe the waveform
and synthesise the code with technological library with given constraints. Do the initial
timing verification with gate level simulation?
Verilog:
`timescale 1 ns / 1 ns
module trans (o, i, cntrl1, cntrl2);
output o;
reg o;
input i;
input cntrl1,cntrl2;
always @ (i or cntrl1 or cntrl2)
begin
if (cntrl1 == cntrl2)
o = i;
else if (cntrl1 == 0 & cntrl2 == 1)
o = i;
else if (cntrl1 == 1 & cntrl2 == 0)
o = 1'bz;
end
endmodule
Testbench:
`timescale 1 ns / 1 ns
Module trans_tb;
wire o ;
reg i ;
reg cntrl1,cntrl2;
transgate t1(o, i,cntrl1, cntrl2);
initial
begin
i= 1'b0 ; cntrl1 = 1'b0 ; cntrl2 = 1'b1 ;
i= 1'b0 ; cntrl1 = 1'b1 ; cntrl2 = 1'b0 ;
i= 1'b1 ; cntrl1 = 1'b0 ; cntrl2 = 1'b1 ;
i= 1'b1 ; cntrl1 = 1'b1 ; cntrl2 = 1'b0 ;
i= 1'b1 ; cntrl1 = 1'b1 ; cntrl2 = 1'b1 ;
i= 1'b1 ; cntrl1 = 1'b0 ; cntrl2 = 1'b0 ;
i= 1'b0 ; cntrl1 = 1'b1 ; cntrl2 = 1'b1 ;
i= 1'b0 ; cntrl1 = 1'b0 ; cntrl2 = 1'b0 ;
end
#10 ; display ;
#10 ; display ;
#10 ; display ;
#10 ; display ;
#10 ; display ;
#10 ; display ;
#10 ; display ;
#10 ; display ;
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endmodule
CONSTRAINTS:
set_input_delay -max 1.0 [get_ports"i"]
set_input_delay -max 1.0 [get_port "cntrl1"]
set_input_delay -max 1.0 [get_port "cntrl2"]
set_output_delay -max 1.0 [get_port "o"]
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REPORT:
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RESULT:
WAVEFORMS:
34
PROGRAM- 4
4. Write Verilog code and test bench for a Basic/Universal gates, observe the waveform
and synthesise the code with technological library with given constraints. Do the initial
timing verification with gate level simulation?
Verilog:
`timescale 1ns/1ns
module allgates(a,b,and1,or2,xor3,nand4,nor5,xnor6,not7);
inputa,b;
output and1,or2,xor3,nand4,nor5,xnor6,not7;
reg and1,or2,xor3,nand4,nor5,xnor6,not7;
always@(a or b )
begin
and1=a&b;
or2=a|b;
xor3=a^b;
nand4=~(a&b);
nor5=~(a|b);
xnor6=~(a^b);
not7=~(a);
end
endmodule
Testbench:
`timescale 1ns/1ns
module allgates_tb;
reg a,b;
wire and1,or2,xor3,nand4,nor5,xnor6,not7;
allgates uut(a,b, and1,or2,xor3,nand4,nor5,xnor6,not7);
task display;
begin
$display("time=%d",$time,"input=",a,b,"output=",and1,or2,xor3,nand4,nor5,xnor6,not7);
end
endtask
initial
begin
a=0;b=0;#30;display;
a=0;b=1;#30;display;
a=1;b=0;#30;display;
a=1;b=1;#30;display;
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end
endmodule
CONSTRAINTS:
set_input_delay -max 1.0 [get_port"a"]
set_input_delay -max 1.0 [get_port"b"]
set_output_delay -max 1.0 [get_port"and1"]
set_output_delay -max 1.0 [get_port"or2"]
set_output_delay -max 1.0 [get_port "xor3"]
set_output_delay -max 1.0 [get_port "nand4"]
set_output_delay -max 1.0 [get_port "nor5"]
set_output_delay -max 1.0 [get_port "xnor6"]
set_output_delay -max 1.0 [get_portnot7"]
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RESULT:
WAVEFORMS:
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REPORT:
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PROGRAM- 5a
5a. Write Verilog code and test bench for an SR flip-flop, observe the waveform and
synthesise the code with technological library with given constraints. Do the initial
timing verification with gate level simulation?
Verilog:
`timescale 1ns/1ns
module srff(clk,s,r,q,qbar);
input clk;
input s,r;
output q,qbar;
reg q,qbar;
always@(posedgeclk)
begin
if(s==1'b0 && r==1'b0)
begin
q<=q;
qbar<=qbar;
end
else if(s==1'b0 && r==1'b1)
begin
q<=1'b0;
qbar<=1'b1;
end
else if(s==1'b1 && r==1'b0)
begin
q<=1'b1;
qbar<=1'b0;
end
else
begin
q<=1'bx;
qbar<=1'bx;
end
end
endmodule
Testbench:
`timescale 1ns/1ns
module srff1_tb;
reg clk,s,r;
wire q,qbar;
srff uut(clk,s,r,q,qbar);
42
initial
clk=1'b0;
always
#10 clk=~clk;
initial
begin
s=1'b0;r=1'b0;
#50 s=1'b1;r=1'b0;
#50 s=1'b0;r=1'b1;
#50 s=1'b1;r=1'b1;
end
always
#5 $display($time,"clk=%b s=%b r=%b",clk,s,r);
initial
#500 $finish;
endmodule
CONSTRAINTS:
create_clock -name clk -period 10 -waveform {0 5} [get_ports "clk"]
set_clock_transition -rise 0.1 [get_clocks "clk"]
set_clock_transition -fall 0.1 [get_clocks "clk"]
set_input_delay -max 1.0 [get_port "s"] -clock [get_clocks "clk"]
set_input_delay -max 1.0 [get_port"r"] -clock [get_clocks "clk"]
set_output_delay -max 1.0 [get_port "q"] -clock [get_clocks "clk"]
set_output_delay -max 1.0 [get_port "qbar"] -clock [get_clocks "clk"]
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RESULT:
WAVEFORMS:
44
REPORT:
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PROGRAM- 5b
5b. Write Verilog code and test bench for a D flip-flop, observe the waveform and
synthesise the code with technological library with given constraints. Do the initial
timing verification with gate level simulation?
Verilog:
`timescale 1ns/1ns
module dff(q,clk,rst,din);
input clk,din,rst;
output q;
reg q;
always@(posedgeclk)
begin
if(rst)
q<=1'b0;
else
q<=din;
end
endmodule
Testbench:
`timescale 1ns/1ns
module dff1_tb;
reg clk,din,rst;
wire q;
dff1 d3(q,clk,rst,din);
initial
clk=1'b0;
always
#10 clk=~clk;
initial
begin
din=1'b0;
rst=1'b0;
#20 rst=1'b1;
#20 rst=1'b0;
#10 din=1'b1;
#20 din=1'b0;
#10 din=1'b1;
#20 din=1'b0;
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end
always
#5 $display($time,"clk=%b din=%b q=%b",clk,din,q);
initial
#300 $finish;
endmodule
CONSTRAINTS:
create_clock -name clk -period 10 -waveform {0 5} [get_ports "clk"]
set_clock_transition -rise 0.1 [get_clocks "clk"]
set_clock_transition -fall 0.1 [get_clocks "clk"]
set_input_delay -max 1.0 [get_port "din"] -clock [get_clocks "clk"]
set_input_delay -max 1.0 [get_port "rst"] -clock [get_clocks "clk"]
set_output_delay -max 1.0 [get_port "q"] -clock [get_clocks "clk"]
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RESULT:
WAVEFORMS:
50
REPORT:
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52
PROGRAM- 5c
5c. Write Verilog code and test bench for a JK flip-flop, observe the waveform and
synthesise the code with technological library with given constraints. Do the initial
timing verification with gate level simulation?
Verilog:
`timescale 1ns/1ns
module jkff(clk,reset,j,k,q,qbar);
output q,qbar;
input clk,j,k,reset;
reg tq,tqb;
always@(posedgeclk or posedge reset)
begin
if(reset)
begin
tq<=1'b0;
tqb<=1'b0;
end
else
begin
if(j==0 && k==0)
begin
tq<=tq;
tqb<=tqb;
end
else if(j==0 && k==1)
begin
tq<=1'b0;
tqb<=1'b1;
end
else if(j==1 && k==0)
begin
tq<=1'b1;
tqb<=1'b0;
end
else
begin
tq<=~tq;
tqb<=~tqb;
end
end
53
end
assign q=tq;
assignqbar=tqb;
endmodule
Testbench:
`timescale 1ns/1ns
module jkff_tb;
reg clk,j,k,rst;
wire q,qbar;
jkff uut(.j(j),.k(k),.clk(clk),.q(q),.qbar(qbar),.rst(rst));
initial
clk=1'b0;
always
#10 clk=~clk;
initial
begin
j=1'b0;k=1'b0;rst=1'b0;
#10 rst=1'b1;
#20 rst=1'b0;
#20 j=1'b0;k=1'b0;
#20 j=1'b0;k=1'b1;
#20 j=1'b1;k=1'b0;
#20 j=1'b1;k=1'b1;
#50 rst=1'b0;
#200 $finish;
end
endmodule
CONSTRAINTS:
create_clock -name clk -period 10 -waveform {0 5} [get_ports "clk"]
set_clock_transition -rise 0.1 [get_clocks "clk"]
set_clock_transition -fall 0.1 [get_clocks "clk"]
set_input_delay -max 1.0 [get_port "j"] -clock [get_clocks "clk"]
set_input_delay -max 1.0 [get_port "k"] -clock [get_clocks "clk"]
set_input_delay -max 1.0 [get_port "rst"] -clock [get_clocks "clk"]
set_output_delay -max 1.0 [get_port "q"] -clock [get_clocks "clk"]
set_output_delay -max 1.0 [get_port "qbar"] -clock [get_clocks "clk"]
54
55
RESULT:
WAVEFORMS:
56
REPORT:
57
58
PROGRAM- 5d
5d. Write Verilog code and test bench for an MS-JK flip-flop, observe the waveform and
synthesise the code with technological library with given constraints. Do the initial
timing verification with gate level simulation?
Verilog:
`timescale 1ns/1ns
module msjkff1(msq,msqbar,msclk,msreset,msj,msk);
input msclk,msreset,msj,msk:
output msq,msqbar;
wire q1,qb1;
jkff1 u1(q1,qb1,msclk,msreset,msj,msk);
jkff2 u2(msq,msqbar,~msclk,msreset,q1,qb1);
endmodule
Testbench:
`timescale 1ns/1ns
module msjkff_tb;
reg msclk,msreset,msj,msk;
wire msq,msqbar;
msjkff1
uut(.msq(msq),.msqbar(msqbar),.msclk(msclk),.msreset(msreset),.msj(msj),.msk(msk))
;
initial
clk=1b0;
always
#10 msclk=~ msclk;
initial
begin
msreset=1b0;msj=1b0;msk=1b0;#50;$display;
msreset=1b0;msj=1b0;msk=1b1;#50;$display;
msreset=1b0;msj=1b1;msk=1b0;#50;$display;
msreset=1b0;msj=1b1;msk=1b1;#50;$display;
msreset=1b1;msj=1b0;msk=1b0;#50;$display;
msreset=1b1;msj=1b0;msk=1b1;#50;$display;
msreset=1b1;msj=1b1;msk=1b0;#50;$display;
msreset=1b1;msj=1b1;msk=1b1;#50;$display;
end
always
begin
#500 $finish;
end
endmodule
59
CONSTRAINTS:
create_clock -name clk -period 10 -waveform {0 5} [get_ports "clk"]
set_clock_transition -rise 0.1 [get_clocks "clk"]
set_clock_transition -fall 0.1 [get_clocks "clk"]
set_input_delay -max 1.0 [get_port "j"] -clock [get_clocks "clk"]
set_input_delay -max 1.0 [get_port "k"] -clock [get_clocks "clk"]
set_output_delay -max 1.0 [get_port "q"] -clock [get_clocks "clk"]
set_output_delay -max 1.0 [get_port "qbar"] -clock [get_clocks "clk"]
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RESULT:
WAVEFORMS:
61
REPORT:
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63
PROGRAM- 5e
5e. Write Verilog code and test bench for a T flip-flop, observe the waveform and
synthesise the code with technological library with given constraints. Do the initial
timing verification with gate level simulation?
Verilog:
`timescale 1ns/1ns
module tff(clk,t,rst,q,qb);
input clk,t,rst;
output q,qb;
reg tq;
always@(posedgeclk or negedgerst)
begin
if(!rst)
begin
if(t==1b1)
begin
tq<=~tq;
end
else
begin
tq<=tq;
end
end
else
tq<=1b0;
end
assign q=tq;
assign qb=~q;
endmodule
Testbench:
`timescale 1ns/1ns
module tff_tb;
reg clk,t,rst;
wire q,qb;
tff uut(clk,t,rst,q,qb);
initial
clk=1'b0;
always
#10 clk=~clk;
64
initial
begin
rst=1b1;t=1b0;#50;$display;
rst=1b0;t=1b1;#50;$display;
rst=1b0;t=1b1;#50;$display;
rst=1b1;t=1b1;#50;$display;
rst=1b0;t=1b1;#50;$display;
end
always
begin
#500 $finish;
end
endmodule
CONSTRAINTS:
create_clock -name clk -period 10 -waveform {0 5} [get_ports "clk"]
set_clock_transition -rise 0.1 [get_clocks "clk"]
set_clock_transition -fall 0.1 [get_clocks "clk"]
set_input_delay -max 1.0 [get_port "t"] -clock [get_clocks "clk"]
set_input_delay -max 1.0 [get_port "rst"] -clock [get_clocks "clk"]
set_output_delay -max 1.0 [get_port "q"] -clock [get_clocks "clk"]
set_output_delay -max 1.0 [get_port "qb"] -clock [get_clocks "clk"]
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RESULT:
WAVEFORMS:
66
REPORT:
67
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PROGRAM- 6a
6a. Write Verilog code and test bench for a Serial Adder, observe the waveform and
synthesise the code with technological library with given constraints. Do the initial
timing verification with gate level simulation?
Verilog
`timescale 1ns/1ns
module serial_adder(a,b,clk,load, sum);
input [7:0] a,b;
inputclk,load;
output [8:0] sum;
reg [7:0] ina,inb;
reg [8:0] oreg;
wire c0,s0;
always@(posedge(clk))
begin
if(load == 1)
begin
ina = a;
inb = b;
end
else
begin
ina[7:0] = {1b0,ina[7:1]};
inb[7:0] = {1b0,inb[7:1]};
end
end
always@(posedge(clk))
begin
if(load == 1)
begin
oreg = 8'd0;
end
else
begin
oreg[8] = c0;
oreg[7:0] = {s0,oreg[7:1]};
end
end
assign s0 = ina[0] ^ inb[0] ^ oreg[8];
assign c0 = (ina[0] &inb[0]) | (ina[0] &oreg[8]) | (oreg[8] &inb[0]);
assign sum = oreg ;
endmodule
Test Bench
70
module serial_test_v;
reg [7:0] a;
reg [7:0] b;
regclk;
reg load;
wire [8:0] sum;
serial_adder my_adder(a,b,clk,load,sum);
initial
clk = 1'b0;
always
#5 clk = ~clk;
initial
begin
load = 0;
a = 8d100;
b = 8d25;
#10;
load = 1;
#10;
load = 0;
#80 ;
$display("a=%d",a," b=%d", b, " sum = %d",sum);
end
always
#100 $finish;
endmodule
CONSTRAINTS:
create_clock -name clk -period 10 -waveform {0 5} [get_ports "clock"]
set_clock_transition -rise 0.1 [get_clocks "clock"]
set_clock_transition -fall 0.1 [get_clocks "clock"]
set_clock_uncertainty 1.0 [get_port "clock"]
set_input_delay -max 1.0 [get_port "A"] -clock [get_clocks "clock"]
set_input_delay -max 1.0 [get_port "B"] -clock [get_clocks "clock"]
set_input_delay -max 1.0 [get_port "reset"] -clock [get_clocks "clock"]
set_output_delay -max 1.0 [get_port "sum"] -clock [get_clocks "clock"]
71
RESULT:
WAVEFORMS:
72
REPORT:
73
74
PROGRAM- 6b
75
6b. Write Verilog code and test bench for a Parallel Adder, observe the waveform and
synthesise the code with technological library with given constraints. Do the initial
timing verification with gate level simulation?
Verilog:
`timescale 1ns/1ns
module para(carryin,x,y,sum,carryout);
input carryin;
input [3:0]x,y;
output [3:0]sum;
output carryout;
fulladd stage0(carryin,x[0],y[0],sum[0],c1);
fulladd stage1(c1,x[1],y[1],sum[1],c2);
fulladd stage2(c2,x[2],y[2],sum[2],c3);
fulladd stage3(c3,x[3],y[3],sum[3],carryout);
endmodule
module fulladd(cin,x,y,s,cout);
input cin,x,y;
output s,cout;
assign s=x^y^cin;
assign cout=(x&y)|(x&cin|(y&cin));
endmodule
Testbench:
`timescale 1ns/1ns
module para_tb;
reg [3:0]x,y;
reg carryin;
wire [3:0]sum;
wire carryout;
para a1(carryin,x,y,sum,carryout);
initial
begin
$monitor($time,"sum=%d",sum);
x=4'b0000;
y=4'b0000;
carryin=1'b0;
#20 x=4'b1111;
y=4'b1010;
76
#50 x=4'b0111;
y=4'b1111;
#60 $finish;
end
endmodule
CONSTRAINTS:
set_input_delay -max 1.0 [get_port "carryin"]
set_input_delay -max 1.0 [get_port "x"]
set_input_delay -max 1.0 [get_port "y"]
set_output_delay -max 1.0 [get_port "sum"]
set_output_delay -max 1.0 [get_ports "carryout]
77
RESULT:
WAVEFORMS:
78
REPORT:
79
80
81
PROGRAM- 7a
7a. Write Verilog code and test bench for a Synchronous 4-bit counter, observe the
waveform and synthesise the code with technological library with given constraints. Do
the initial timing verification with gate level simulation?
Verilog:
`timescale 1ns/1ns
module binsync(clk,reset,count);
input clk,reset;
output [3:0]count;
reg [3:0]count;
always@(posedge reset or posedgeclk)
begin
if(reset)
count<=4'b0000;
else if (clk)
count<=count+1;
end
endmodule
Testbench:
`timescale 1ns/1ns
module binsync_tb;
reg clk;
reg reset;
wire [3:0]count;
initial
clk=1'b0;
always #5 clk=~clk;
binsync uut(.clk(clk),.reset(reset),.count(count));
initial
begin
reset=1'b0;
#10 reset=1'b1;
#20 reset=1'b0;
#190 reset=1'b1;
#20 reset=1'b0;
#40 reset=1'b1;
#190 reset=1'b1;
82
#100 reset=1'b1;
#40 reset=1'b0;
#300 $finish;
end
initial
$display($time,"count=%d",count);
endmodule
CONSTRAINTS:
create_clock -name clk -period 10 -waveform {0 5} [get_ports "clk"]
set_clock_transition -rise 0.1 [get_clocks "clk"]
set_clock_transition -fall 0.1 [get_clocks "clk"]
set_input_delay -max 1.0 [get_port "reset"] -clock [get_clocks "clk"]
set_output_delay -max 1.0 [get_port "count"] -clock [get_clocks "clk"]
83
RESULT:
WAVEFORMS:
84
REPORT:
85
86
87
PROGRAM- 7b
7b. Write Verilog code and test bench for a Asynchronous 4-bit counter, observe the
waveform and synthesise the code with technological library with given constraints. Do
the initial timing verification with gate level simulation?
Verilog:
`timescale 1ns/1ns
module sync(clk,reset,count);
input clk,reset;
output[3:0]count;
reg c0,c1,c2,c3;
always@(posedgeclk or posedge reset)
begin
if(reset)
c0<=1'b0;
else
c0<=~c0;
end
always@(negedge c0 or posedge reset)
begin
if(reset)
c1<=1'b0;
else
c1<=~c1;
end
always@(negedge c1 or posedge reset)
begin
if(reset)
c2<=1'b0;
else
c2<=~c2;
end
always@(negedge c2 or posedge reset)
begin
if(reset)
c3<=1'b0;
else
c3<=~c3;
end
assign count[0]=c0;
assign count[1]=c1;
assign count[2]=c2;
assign count[3]=c3;
endmodule
88
Testbench:
`timescale 1ns/1ns
module async_tb;
reg clk,reset;
wire[3:0]count;
async r1(clk,reset,count);
initial
clk=1'b0;
always #10 clk=~clk;
initial
begin
reset=1'b0;
#10 reset=1'b1;
#10 reset=1'b0;
#190 reset=1'b1;
#20 reset=1'b0;
#100 reset=1'b1;
#40 reset=1'b0;
#10 reset=1'b1;
#10 reset=1'b0;
#290 reset=1'b1;
#20 reset=1'b0;
#100 reset=1'b1;
#40 reset=1'b0;
#250;
$finish;
end
initial
$monitor($time,"op=%d",count);
endmodule
CONSTRAINTS:
create_clock -name clk -period 10 -waveform {0 5} [get_ports "clk"]
set_clock_transition -rise 0.1 [get_clocks "clk"]
set_clock_transition -fall 0.1 [get_clocks "clk"]
set_input_delay -max 1.0 [get_port "reset"] -clock [get_clocks "clk"]
set_output_delay -max 1.0 [get_port "count"] -clock [get_clocks "clk"]
89
90
RESULT:
WAVEFORMS:
91
REPORT:
92
93
ANALOG DESIGN
ANALOG DESIGN FLOW:
STEPS FOR THE ANALOG LAB
Creating The Library
Go to cd VLSI_LAB/cadence_analog_lab.
Go to csh mode.
Source the tool source ~/cshrc.main.
Type `virtuoso & and press enter, it will open a virtuoso tool.
94
95
Select create pins, and place the ports (vin, vdd, gnd, vout) on the editor.
96
Make the complete connection by using wires by selecting create wire (narrow).
After complete of the schematic, save the file by file check & save .
97
98
STEPS TO SIMULATE
In the Virtuoso Schematic Editor after completing the test circuit design,
launch ADE L.
GotoAnalyses choose, select tran for transient analysis ( stop time = 200n,
accuracy default moderate) and apply, now select dc for DC analysis ( select
save dc operating point, component parameter and double click select component
and select input source vpulse in schematic editor, and dc, sweep range is 0 to
1.8v).
99
100
1. Open the Library Manager in Virtuoso, select CMRIT and double click inverter,
then gotoFile New Cellview.
2. In the Schematic Editor Window, Go to
3. In the Layout Window Go to
Launch
Connectivity
Layout XL.
Generate
show/hide
Incomplete.nets.
7. In the layout window press shift F to view the layers for the transistor.
8. Move each component to the I quadrant and place Vdd, Vss, Vin, Vout in the
appropriate position.
9. To draw the rectangle of layers for ex:-Metal1, Choose Metal1 dra in
LSW(Layout Selection Window) & press R or (create
shape
rectangle) &
give the connections to Vdd, Vout, Vss.
102
11. Place the substrate contacts Vdd&Vssi.e, M1 - n-well for Vdd&M1 - P-sub
for Vss.
12. Draw the n-well layer to cover the Vdd&pmos transistor.
13. Check and save the layout.
14. In the same window gotoASSURArunDRC.Check for the errors
15. GotoASSURA
run LVS
16. In LVS debug Window, check for errors in summary and rectify if required.
17. After layout and schematic matches, go to
ok.
ASSURA
Run RCX
click
103
INVERTER
1.Design an Inverter with given specifications, completing the design flow mentioned
below:
a. Draw the schematic and verify the following
iii.
DC Analysis
iv.
Transient Analysis
b. Draw the Layout and verify the DRC, ERC
c. Check for LVS
d. Extract RC and back annotate the same and verify the Design
e. Verify & Optimise for Time, Power and Area to the given constraint.
SPECIFICATIONS:
Library Name
Gpdk180
Gpdk180
Cell Name
Pmos
Nmos
Pin Name
Vin
Vout
Vdd, Vss
Library Name
Properties
Model name=pmos1; w=2u; l=180n
Model name=nmos1; w=2u; l=180n
Direction
Input
Output
Input
Cell Name
Properties
104
CMRIT
Analoglib
Inverter
Vpulse
Analoglib
Vdd, Vss
Symbol
Define pulse specification
as
V1 =0v V2 = 1.8v period
= 20n PW = 10n
Rise time = fall time = 1n
Vdd(Vdc)=2.5v, Vss=gnd
SCHEMATIC:
105
TEST SCHEMATIC:
106
LAYOUT:
107
WAVEFORM:
ANALYSIS
Transient analysis : stop time = 200n
108
Choose moderate
DC analysis :
109
2.Design the following circuits with given specifications, completing the design flow
mentioned below:
a. Draw the schematic and verify the following
iii.
DC Analysis
iv.
Transient Analysis
b. Draw the Layout and verify the DRC, ERC
c. Check for LVS
d. Extract RC and back annotate the same and verify the Design
iii. A Single Stage differential amplifier
iv.
Common source and Common Drain amplifier
I.
DIFFERENTIAL AMPLIFIER
SPECIFICATIONS:
Library Name
Gpdk180
Gpdk180
Cell Name
Pmos
Nmos
Pin Name
Idc, V1,V2
Vout
Vdd, Vss
Properties
Model name=pmo,pm1; w=15u; l=1u
Model name=nmo,nm1; w=3u; l=1u
Model name=nm2,nm3; w=4.5u; l=1u
Direction
Input
Output
Input
Library Name
CMRIT
Analoglib
Cell Name
Diff_amplifier
Vsin
Analoglib
Vdd, Vss
Properties
Symbol
Define pulse specification
as AC magnitude = 1;
Amplitude = 5m; Frequency
= 1k
Vdd(Vdc)=2.5v,
Vss=(Vdc)=-2.5
110
Analoglib
Idc
DC current = 30u
SCHEMATIC:
111
TEST SCHEMATIC:
112
WAVEFORM:
ANALYSIS
Transient analysis : stop time = 5m
113
Choose moderate
DC analysis :
AC analysis :
ON frequency
Start = 150
Stop = 100M
Step size = logarithmic
Points per decade = 20
114
SPECIFICATIONS :
Library Name
Gpdk180
Gpdk180
Cell Name
Pmos
Nmos
Pin Name
Vin, Vbias
Vout
Vdd, Vss
Properties
Model name=pmos1; w=50u; l=1u
Model name=nmos1; w=10u; l=1u
Direction
Input
Output
Input
Library Name
CMRIT
Analoglib
Cell Name
cs_amplifier
Vsin
Analoglib
Vdd, Vss,Vbias
Properties
Symbol
Define pulse specification
as AC magnitude = 1; DC
voltage=0; Amplitude = 5m;
Frequency = 1k
Vbias = Vdd(Vdc)=2.5v,
Vss=(Vdc)=-2.5
SCHEMATIC:
116
TEST SCHEMATIC:
117
LAYOUT:
118
WAVEFORM:
ANALYSIS
Transient analysis : stop time = 5m
Choose moderate
DC analysis :
Start = -5
Stop = 5
AC analysis :
ON frequency
Start = 150
Stop = 100M
Step size = logarithmic
Points per decade = 20
120
SPECIFICATIONS:
Library Name
Gpdk180
Gpdk180
Cell Name
Pmos
Nmos
Pin Name
Idc, V1,V2
Vout
Vdd, Vss
Properties
Model name=pmo,pm1; w=50u; l=1u
Model name=nmo,nm1; w=10u; l=1u
Direction
Input
Output
Input
Library Name
CMRIT
Analoglib
Cell Name
cd_amplifier
Vsin
Analoglib
Properties
Symbol
Define pulse specification
as AC magnitude = 1; DC
voltage=0; Amplitude = 5m;
Frequency = 1k
Vbias =Vdd(Vdc)=2.5v,
Vss=(Vdc)=-2.5
121
SCHEMATIC:
TEST SCHEMATIC:
122
LAYOUT:
123
WAVEFORM:
ANALYSIS
Transient analysis : stop time = 5m
Choose moderate
124
DC analysis :
AC analysis :
ON frequency
Start = 150
Stop = 100M
Step size = logarithmic
Points per decade = 20
125
126
SPECIFICATIONS:
Library Name
Gpdk180
Gpdk180
Cell Name
Properties
Diff_amplifier Symbol
Cs_amplifier Symbol
Pin Name
Idc, Vin,Vnoninv
Vout
Vdd, Vss
Direction
Input
Output
Input
Library Name
CMRIT
Analoglib
Cell Name
op_amplifier
Vsin
Analoglib
Vdd, Vss
Analoglib
Idc
Properties
Symbol
Define pulse specification
as AC magnitude = 1;
Amplitude = 5u; Frequency
= 1k
Vdd(Vdc)=2.5v,
Vss=(-Vdc)=-2.5
DC current = 30u
SCHEMATIC:
127
TEST SCHEMATIC:
128
WAVEFORM:
ANALYSIS
129
AC analysis :
ON frequency
Start = 150
Stop = 100M
Step size = logarithmic
Points per decade = 20
130
131