Proceedings of the 8

th
National Conference on
Advances in Electronic Communications (ADELCO 12), 24
th
Feb, 2012,
National Engineering College, Kovilpatti, Tamil Nadu.

58

DESIGN AND IMPLEMENTATION OF 2-BIT LOADED LINE
PHASE SHIFTER

MERCY.J
1
MUTHUKUMARAN.P
2

1
M.E Communication Systems, Sri Venkateswara College of Engineering, Sriprembudur, Chennai, India.
mercy.j89@gmailcom
2
Assistant Professor, Department of ECE, Sri Venkateswara College of Engineering, Sriprembudur,
Chennai, India
muthu3nava@gmail.com



Abstract - This paper proposes a newly designed 2-bit
loaded line phase shifter for 2.4 GHz applications.
The design use Koch fractal curves to reduce the size
of the loaded line phase shifter. The concept is to be
tested at 2.4 GHz using FR-4 dielectric material
using microstrip technology. The reflection loss of
the loaded line phase shifter is measured and its
found to be less than -20dB. The measured phase
shift of 17.003 is obtained as against 16.875. The
insertion loss can be further improved by using
lower loss dielectric material.

Keywords - Bluetooth, FR4, Koch fractal, loaded line,
Microstrip, Phased array, Phase shifter, WLAN.

I. INTRODUCTION
The Phase shifters (PS) in a phased array antenna
shifts phase of the incoming RF signal depending on
control input [1], enabling antenna main beam to be
steered at a faster rate without rotating antenna
mechanically. Demand for high performance WLAN
system at low cost has necessitated development of a
miniaturized PS with reduced loss at low cost [2].
Design and development of various types of PSs
(switched line, reflective line, loaded line and high-pass
and low-pass types) are reported [3, 4]. Out of different
types of PSs, loaded line PS offers simplicity and low
insertion loss [5]. Miniaturized PSs have been reported
using MEMS technology [6]. In addition, fractal
technology has been used to reduce size of antenna [7].
Also, usage of Koch fractal in miniaturizing a branch
line coupler is reported [8].
This paper presents a reduced size Koch fractal
based 2-bit loaded line phase shifter, which was
simulated using ADS and its performance is to be tested
with conventional PS using Network Analyzer.
II. LOADED LINE PHASE SHIFTERS(PSS)
Each section of a loaded line PS (Fig.1) consists of a
/4 transmission line symmetrically loaded at its ends
by small susceptances for mutually cancelling
reflections due to /4 separation. Susceptance values are
controlled by semiconductor switches such as PIN
diodes. Desired PS is obtained by changing electrical
length through switching PIN diodes.




Loaded line PS has the advantages of simplicity and
low insertion loss for phase shifts of less than 45
0
. The
circuit consists of two equal two-state switchable
admittances Y
i
= G
i
+ jB
i
connected in shunt with a line
section of characteristic impedance Z
0
=1/Y
0
and
electrical length , where i =1, 2 refers to the two bias
states of the switching devices.


Fig. 1: Layout of a section of conventional loaded
line phase shifter

The loading admittance of these elements is
controlled with switching diodes to electrically shorten
or lengthen the transmission line. The transition
between the two admittance states produces a phase
change of ((
1
-
2
) these values are obtained from
two different values of Y
i
).
The circuit design of the loaded-line phase shifter
consists of the selection of values for the unknown
parameters , Z
0
, G
i
and B
i
(i= 1, 2). The conductance
G
i
results from ohmic losses in the loading elements Y
i
,
and is typically small when low-loss switching devices
are used. With low-loss loads, a good approximate
solution is obtained by assuming that G
i
is equal to zero.
The general expression for the electrical length and
the characteristic impedance Y
0
are given in (1) and
(2). Using these equations, the desired performance is
therefore set by specifying B, Y
0
, :

Proceedings of the 8
th
National Conference on
Advances in Electronic Communications (ADELCO 12), 24
th
Feb, 2012,
National Engineering College, Kovilpatti, Tamil Nadu.

59



( ) sin cos cos '
0
1
B Z =

(1)
2
1
0
2
0
0
'
0
cot 2 1
(

'

'

=
Y
B
Y
B
Y Y (2)

where Z
0
is the characteristic impedance of the
transmission line; is the electrical length of the
transmission line and B is the shunt susceptances of the
transmission lines.










Fig. 2 Biasing circuit

The design of loaded line phase shifter using micro
strip lines requires the following parameters:
1. The characteristic impedance (Z
T
) of the quarter
wave transformer (/4 line).
2. The electrical length (l) of the short stub.
Microwave Associates MA4P789-287T pin diodes
are used as a switch. Diode parameters for equivalent
diode model were C
r
=0.35 pf @ 20V reverse bias
voltage and Rf =1.5 @ 10mA forward current.
Switching between two susceptance values of each bit is
done by applying proper bias voltages to PIN diodes.
Co-simulation of 2-bit conventional loaded line circuit
(Fig.3) is to produce the phase shift of 16.875 (a
cascade of 5.625 and 11.25 bit sections). During
cascade of 2-bit sections, matching between sections is
taken care of for low insertion losses.
III. MINIATURIZATION USING KOCH CURVES
Fractals are fragmented space-filling containers used
to pack electrically large features efficiently into small
physical areas. Koch fractals are characterized by
iteration factor and iteration order. Iteration factor
represents construction law of fractal geometry, and
iteration order depicts how many iteration processes are
to be carried out. Fractal geometries were utilized as
reported [8]. For a straight microstrip line of /4
electrical length, the generation process of a Koch-
shaped microstrip line with iteration factor of 1/5 as
shown in (Figure.4).
Koch fractals are applied to shunt quarter wave
transmission line and bias line of conventional loaded
line PS with 0.2 iteration factor with iteration of one.
Layout of 11.25 section of Koch loaded line PS is
shown in (Figure.5). Conventional 2-bit loaded line PS
is miniaturized using Koch fractal technique (Fig.6).
A reduction in area is achieved by application of
Koch technique for 2-bit loaded line PS circuit



Fig 3: Co-sim of conventional loaded line phase
shifter



Fig. 4 Koch-Fractal-shaped microstrip lines whose
iteration factor is 1/5
Short circuit
stub of /4
Main transmission line
Bias voltage
supply
Open circuit
Stub of /4
Proceedings of the 8
th
National Conference on
Advances in Electronic Communications (ADELCO 12), 24
th
Feb, 2012,
National Engineering College, Kovilpatti, Tamil Nadu.

60




Fig. 5 Layout of 11.25 section of Koch Loaded line
Phase shifter


S_Param
SP1
Step=10MHz
Stop=2.5GHz
Start=2.3GHz
S-PARAMETERS
PIN_diode
PinDiode4
PIN_diode
PinDiode3
PIN_diode
PinDiode2
PIN_diode
PinDiode1
V_DC
SRC2
V_DC
SRC1
Term
Term2
Z=50 Ohm
Num=2
koch4
koch4_1
ModelType=RF
T L 1 0 T L 8
T L 1 1 T L 6 T e e 1 C r o s 1
T L 1
T L 19 T L 21
T L 1 2 T L 1 3
T ee 2 T L 14
T L 2 2
C r o s 2 TL 1 5 T L 5 T L2 0 T L 3
Term
Term1
Z=50Ohm
Num=1
C
C4
C
C3
C
C2
C
C1

Fig. 6 2-Bit Loaded line PS using Koch-Fractal
technique


IV. SIMULATION RESULTS
Both conventional and miniaturized loaded line
phase shifters are designed for single bit and 2-bit
sections on FR-4 substrate with 1.6 mm thick and
r
=
4.6. The design is simulated using Agilent-ADS
2008(Advanced Design System). Table. I shows the
simulated results for conventional 11.25 loaded line
phase shifter. Table. II shows the simulated results for
conventional 5.625 loaded line phase shifter. Table.III
shows simulation results for conventional 2-bit loaded
line phase shifter. Corresponding results are shown in
Figure.7 and Figure.8.


(a)


(b)

Fig. 7:Conventional circuit magnitude plot and
phase (11.25): a) Diode ON; b) Diode OFF









Proceedings of the 8
th
National Conference on
Advances in Electronic Communications (ADELCO 12), 24
th
Feb, 2012,
National Engineering College, Kovilpatti, Tamil Nadu.

61




(a)



(b)



(c)


(d)


Fig. 8: Conventional circuit magnitude plot and phase: a) Diodes (D1, D2-ON); b) Diodes (D1-OFF, D2-ON);
c) Diodes (D1-ON, D2-OFF); d) Diodes (D1, D2- OFF)



Proceedings of the 8
th
National Conference on
Advances in Electronic Communications (ADELCO 12), 24
th
Feb, 2012,
National Engineering College, Kovilpatti, Tamil Nadu.

62



TABLE I. CONVENTIONAL 11.25 LOADED LINE PHASE SHIFTER


Diode
State


S11
Magnitude

S21
Magnitude

S21
Phase

(on phase-off phase)

Simulated Desired

Phase
Error

ON

-26.566

-0.466

-69.332

OFF

-31.164

-0.440

-80.589

11.257 11.25

-0.007


TABLE II. CONVENTIONAL 5.625 LOADED LINE PHASE SHIFTER


Diode
State


S11
Magnitude

S21
Magnitude

S21
Phase

(on phase-off phase)

Simulated Desired

Phase
Error

ON

-27.988

-0.463

-72.235

OFF

-30.395

-0.435

-77.927

5.692 5.625

-0.067

TABLE III. CONVENTIONAL 2-BIT LOADED LINE PHASE SHIFTER


Bit
Input


S11
Magnitude

S21
Magnitude

S21
Phase

(on phase-off phase)
Obtained Desired

Phase
Error

00

-29.285

-0.789

-69.991

- -
-

01

-27.287

-0.800

-58.690

11.301 11.25
-0.051

10

-26.813

-0.818

-64.275

5.716 5.625

-0.091

11

-25.180

-0.830

-52.988

17.003 16.875

-0.128


V CONCLUSION
A 2-bit loaded line phase shifter is designed
using FR4 substrate at 2.4 GHz frequency. The ON
and OFF state (forward and reverse bias) of the PIN
diode is used to determine the phase shift of the
circuit. The schematic, layout and co-simulation of
2-bit loaded line phase shifter are designed and
simulated using ADS (Advanced Design System)
software. The results are obtained for the schematic,
layout and co-simulation 2-bit loaded line phase
shifter.
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