WIZ811MJ Datasheet

(Ver. 1.2)

2013 WIZnet Co., Ltd. All Rights Reserved. For more information, visit our website at www.wiznet.co.kr

WIZ811MJ Datasheet

Document History Information

Revision Ver. 1.0 Ver. 1.1 Ver. 1.2 Data March 11, 2008 January 28, 2009 January 25, 2013 Description Release with WIZ811MJ Launching Added temperature specification Hardware revision(Rev1.1) Changed operation temperature range, Partlist and schematic as H/W revision.

TOP
WIZ8 10M J Data shee t

WIZnets Online Technical Support

If you have something to ask about WIZnet Products, Write down your question on Q&A Board in WIZnet website (www.wiznet.co.kr). WIZnet Engineer will give an answer as soon as possible.

Copyright 2013 WIZnet Co., Ltd. All rights reserved

WIZ811MJ Datasheet

Table of Contents

1.

Introduction .............................................................................. 4 1.1. 1.2. 1.3. Features ............................................................................. 4 Block Diagram ...................................................................... 4 Difference between WIZ810MJ and WIZ811MJ .............................. 5 3

TOP
WIZ8 10M J Data shee t

2.

Pin Assignments & descriptions ................................................... 6 2.1. 2.2. 2.3. 2.4. Pin Assignments ................................................................... 6 Power & Ground ................................................................... 6 MCU Interfaces ..................................................................... 7 Miscellaneous Signals ............................................................ 8

3.

Timing Diagrams ....................................................................... 9 3.1. 3.2. 3.3. 3.4. Reset Timing ...................................................................... 9 Register/Memory READ Timing ................................................. 9 Register/Memory WRITE Timing .............................................. 10 SPI Timing......................................................................... 10

4. 5. 6.

Dimensions ............................................................................. 11 Schematic .............................................................................. 12 Partlist ................................................................................... 13

Copyright 2013 WIZnet Co., Ltd. All rights reserved

WIZ811MJ Datasheet

1. Introduction
WIZ811MJ is the network module that includes W5100 (TCP/IP hardwired chip, include PHY), MAG-JACK (RJ45 with XFMR) with other glue logics. It can be used as a component and no effort is required to interface W5100 and Transformer. The WIZ811MJ is an ideal option for users who want to develop their Internet enabling systems rapidly. For the detailed information on implementation of Hardware TCP/IP, refer to the W5100 Datasheet. WIZ811MJ consists of W5100 and MAG-JACK. TCP/IP, MAC protocol layer: W5100 Physical layer: Included in W5100 Connector: MAG-JACK(RJ45 with Transformer)

TOP
WIZ8 10M J Data shee t

1.1. Features
Supports 10/100 Base TX Supports half/full duplex operation Supports auto-negotiation and auto cross-over detection IEEE 802.3/802.3u Compliance Operates 3.3V with 5V I/O signal tolerance Supports network status indicator LEDs Includes Hardware Internet protocols: TCP, IP Ver.4, UDP, ICMP, ARP, PPPoE, IGMP Includes Hardware Ethernet protocols: DLC, MAC Supports 4 independent connections simultaneously Supports MCU bus Interface and SPI Interface Supports Direct/Indirect mode bus access Supports Socket API for easy application programming Interfaces with two 2.54mm pitch 2 x 10 header pin Temperature : [PCB rev1.0] : 0 ~ 70 (Operation), -40 ~ 85 (Storage) [PCB rev1.1] : -40 ~ 85 (Operation), -40 ~ 85 (Storage)

1.2. Block Diagram

Copyright 2013 WIZnet Co., Ltd. All rights reserved

WIZ811MJ Datasheet

1.3. Difference between WIZ810MJ and WIZ811MJ

WIZ810MJ WIZ811MJ

5 Two 2mm pitch 14x2 header Not has PCB through Hole 52 x 25 x 21mm (W x H x D) Two 2.54mm pitch 10x2 header Two PCB Through Hole( 3.00mm) 55.5 x 25 x 23.5mm (W x H x D)

TOP
WIZ8 10M J Data shee t

Share SPI and BUS signal pin (need to Separate SPI signal pin (SPI_EN control SPI_EN pin) controlled automatically by /SCS signal)

Copyright 2013 WIZnet Co., Ltd. All rights reserved

WIZ811MJ Datasheet

2. Pin Assignments & descriptions

2.1. Pin Assignments

TOP
WIZ8 10M J Data shee t

I : Input I/O : Bi-directional Input and output

O : Output P : Power

2.2. Power & Ground

Symbol VCC GND Type P P J1:12 , J1:11, J2:19, Pin No. J2:1 J2:9, J2:20 J2:10, Description Power : 3.3 V power supply Ground

Copyright 2013 WIZnet Co., Ltd. All rights reserved

WIZ811MJ Datasheet

2.3. MCU Interfaces

Symbol SCLK Type I J2:3 Pin No. Description SCLK(Serial Clock) This pin is used to SPI Clock Signal pin.

/SCS

J2:4

MOSI

J1:1

/SCS (Slave Select) * This pin is used to SPI Slave Select signal Pin. This pin controls SPI_EN signal of W5100. When /SCS signal assert low, W5100 drive SPI mode by SPI_EN signal toggled high. MOSI (Master Out Slave In) * This pin is used to SPI MOSI signal pin.

TOP
WIZ8 10M J Data shee t

MISO

I/O

J1:2

MISO (Master In Slave Out) * This pin is used to SPI MISO signal pin.

A14~A8

J1:13 ~ J1:19

Address Used as Address[14-8] pin Address Used as Address[7-0] pin Data 8 bit-wide data bus Module Select : Active low. /CS of W5100 Read Enable : Active low. /RD of W5100 Write Enable : Active low /WR of W5100 Interrupt : Active low After reception or transmission it indicates that the W5100 requires MCU attention. By writing values to the Interrupt Status Register of W5100 the interrupt will be cleared. All interrupts can be masked by writing values to the IMR of W5100 (Interrupt Mask Register). For more details refer to the W5100 Datasheet

A7~A0

J2:11 ~ J2:18

D7~D0

I/O

J1:3 ~ J1:10

/CS /RD /WR /INT

I I I O

J2:7 J2:6 J2:5 J2:8

Copyright 2013 WIZnet Co., Ltd. All rights reserved

WIZ811MJ Datasheet

2.4. Miscellaneous Signals

Symbol Type Pin No. Description Reset : This pin is active low input to initialize or re-initialize W5100. By asserting this pin low for at least 2us, all internal registers will be re-initialized to their default states. Not Connect

/RESET

J2:2

NC

J1 : 20

TOP
WIZ8 10M J Data shee t

Copyright 2013 WIZnet Co., Ltd. All rights reserved

WIZ811MJ Datasheet

3. Timing Diagrams
WIZ811MJ provides following interfaces of W5100. -. Direct/Indirect mode bus access -. SPI access

3.1.

Reset Timing
9

TOP
WIZ8 10M J Data shee t

1 2

Description Reset Cycle Time /RESET to internal PLOCK

Min 2 us -

Max 10 ms

3.2.

Register/Memory READ Timing

1 2 3 4 5 6

Description Read Cycle Time Valid Address to /CS low time /CS low to /RD low time /RD high to /CS high time /RD low to Valid Data Output time /RD high to Data High-Z Output time

Min 80 ns 8 ns -

Max 1 ns 1 ns 80 ns 1 ns

Copyright 2013 WIZnet Co., Ltd. All rights reserved

WIZ811MJ Datasheet

3.3.

Register/Memory WRITE Timing

10

TOP
WIZ8 10M J Data shee t

1 2 3 4 5 6

Description Write Cycle Time Valid Address to /CS low time /CS low to /WR high time /CS low to /WR low time /WR high to /CS high time /WR low to Valid Data time

Min 70 ns 7 ns 70 ns -

Max 1 ns 1 ns 14 ns

3.4.

SPI Timing

1 2 3 4 5 6

Description /SS low to SCLK Input setup time Input hold time Output setup time Output hold time SCLK time

Mode Slave Slave Slave Slave Slave Slave

Min 21 ns 7 ns 28 ns 7 ns 21 ns 70 ns

Max 14 ns -

Copyright 2013 WIZnet Co., Ltd. All rights reserved

WIZ811MJ Datasheet

4. Dimensions
D

B C

11

TOP
E F G

WIZ8 10M J Data shee t

Symbols A B C D E F G H I J K L M

Dimensions (mm) 25.00 22.46 17.00 3.00 4.00 52.00 3.20 9.00 2.54 2.54 15.90 13.50 6.00

Copyright 2013 WIZnet Co., Ltd. All rights reserved

C1 15pF
FDX_LED 1V8D

XTLP

Y1 0.1uF R4 R2 200 49.9 U2 TXOP TXON 49.9 3V3A 200 R3 R5

XTLP XTLN 1V8A

25MHz (SMD) C3

R1 1M 3V3D
LINK_LED

C2 15pF

XTLN

U1

3V3D 3V3A

R6 12K (1%) RXIP RXIN FDX_LED R8 3V3D L2L1+ CH_GND1 CH_GND2 BS-RB10005 13 14 49.9 49.9 0.1uF LINK_LED 11 12 R9 C4 L4L3+ 9 10

NC NC NC GNDA XTLP XTLN VCC1V8A TXLED RXLED COLLED FDXLED VCC1V8D GNDD SPDLED LINKLED OPMODE2 OPMODE1 OPMODE0 NC NC

RSET_BG 1 2 3 4 5 6 7 8 TD+ TDTCT NC1 NC2 NC3 RD+ RD-

RXIP RXIN 1V8A TXOP TXON

1V8_OUT

R7 300 (1%)

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

1V8D 1V8D A10 A11 C5 0.1uF CHGND

5. Schematic

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 MISO MOSI /SCS SCLK SEN GNDD VCC1V8D TEST_MODE3 TEST_MODE2 TEST_MODE1 TEST_MODE0 ADDR14 ADDR13 ADDR12

D7 D6

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 /RESET /RD /WR /INT /CS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9

RSET_BG VCC3V3A NC GNDA RXIP RXIN VCC1V8A TXOP TXON GNDA 1V8_OUT VCC3V3D GNDD GNDD VCC1V8D VCC1V8D GNDD VCC3V3D DATA7 DATA6

NC /RESET /RD /WR /INT /CS ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 VCC3V3D GNDD ADDR10 ADDR11

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

W5100 1V8D FB2 1V8_OUT 1uH 1V8A C20 10uF/16V C21 0.1uF C22 0.1uF C23 0.1uF C24 0.1uF C25 0.1uF C26 0.1uF 1V8A 1V8D

D5 D4 D3 D2 D1 D0 MISO MOSI /SCS SCLK SPI_EN

1 2 3 4 5 6 7 8 CON8 CHGND

1 2 3 4 5 6 7 8 CON8 CHGND

Title WIZ811MJ Size A3 Date: Document Number <Doc> Tuesday , Nov ember 27, 2012 Sheet 1 of 1 Rev 1.1

Copyright 2013 WIZnet Co., Ltd. All rights reserved

3V3A
1V8D A14 A13 A12

3V3D

3V3D

C18 3.3uF/16V

C19 10uF/16V

C12

C13

C14 C6

C11 10uF/16V

FB1

1uH

0.1uF

0.1uF

0.1uF

C7 10uF/16V 3V3D

C9 0.01uF CHGND

0.1uF C10

0.1uF 3V3D J2 3V3D U4 /SCS 1 2 3 NC A GND Vcc Y 5 4 SN74AHC1G04 3V3D SPI_EN C17 0.1uF VCC SCLK /WR /CS A0 A2 A4 A6 A1 A3 A5 A7 /RESET /SCS /RD /INT 3V3D R11 4.7K CHGND

3V3D

J1

MOSI D1 D3 D5 D7

MISO D0 D2 D4 D6

A8 A10 A12 A14

1 3 5 7 9 11 13 15 17 19

2 4 6 8 10 12 14 16 18 20

A9 A11 A13

1 3 5 7 9 11 13 15 17 19

2 4 6 8 10 12 14 16 18 20

GH1 HEADER 10X2 2.54 Pitch

GH2

HEADER 10X2 2.54 Pitch

WIZ811MJ Datasheet

GH3 CON1

12

WIZ8 10M J Data shee t

TOP

WIZ811MJ Datasheet

6. Partlist
Item 1 Q.ty 2 Reference C1,C2 C3,C4,C5,C6, C10,C12,C13 ,C14, C17,C21,C22, C23,C24,C25, C26 C7,C11,C19,C 20 C9 C18 FB1,FB2 J1,J2 R1 R2,R3,R8,R9 R4,R5 R6 R7 R11 U1 U2 U4 Y1 Part 15pF Tech. Characteristics 50V-20% Ceramic Package CASE 0603

15

0.1uF

50V-20% Ceramic

CASE 0603

3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

4 1 1 2 2 1 4 2 1 1 1 1 1 1 1 1

10uF/16V 0.01uF 3.3uF/16V 1uH Chip Ferrite Inductor 2X10 20PIN 2.54mm DIP STRAIGHT Header 1M 49.9 (1%) 200 12K (1%) 300 (1%)

16Vmin 10% 50V-20% Ceramic 16Vmin 10% 2 X 10 2.54mm pitch 1/10W-5% SMD 1/10W-1% SMD 1/10W-5% SMD 1/10W-1% SMD 1/10W-1% SMD 1/10W-5% SMD WIZnet Hardware TCP/IP Transformer + RJ45 Inverting Buffer SMD Type, CL=18pF, Industrial WIZ811MJ REV1.1 1.6T 4LAYER

EIA/IECQ 3216 CASE 0603 EIA/IECQ 3216 CASE 0805

13

TOP
WIZ8 10M J Data shee t

4.7K
W5100 BS-RB10005 74AHC1G04GW 25MHz (SMD) PCB

CASE 0603 CASE 0603 CASE 0603 CASE 0603 CASE 0603 CASE 0603 LQFP80 TSSOP5 SX-1

Copyright 2013 WIZnet Co., Ltd. All rights reserved