Distributed Packet Buffers for High-Bandwidth Switches and Routers

ABSTRACT: High-speed routers rely on well-designed packet buffers that support multiple queues, pro ide large capacity and short response times! Some researchers suggested combined SR"#$DR"# hierarchical buffer architectures to meet these challenges! Howe er, these architectures suffer from either large SR"# requirement or high time-comple%ity in the memory management! &n this paper, we present scalable, efficient, and no el distributed packet buffer architecture! 'wo fundamental issues need to be addressed to make this architecture feasible( )* how to minimi+e the o erhead of an indi idual packet buffer, and -* how to design scalable packet buffers using independent buffer subsystems! .e address these issues by first designing an efficient compact buffer that reduces the SR"# si+e requirement by /k - )*$k! 'hen, we introduce a feasible way of coordinating multiple subsystems with a load-balancing algorithm that ma%imi+es the o erall system performance! Both theoretical analysis and e%perimental results demonstrate that our load-balancing algorithm and the distributed packet buffer architecture can easily scale to meet the buffering needs of high bandwidth links and satisfy the requirements of scale and support for multiple queues! EXISTING SYSTEM 'he router buffer si+ing is still an open issue! 'he traditional rule of thumb for &nternet routers states that the routers should be capable of buffering R''0R data, where R'' is a roundtrip time for flows passing through the router, and R is the line rate! #any researchers claimed that the si+e of buffers in backbone routers can be made ery small at the e%pense of a small loss in throughput!

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Distributed Packet Buffers for High-Bandwidth Switches and Routers

1ocusing on the performance of indi idual '2P flows, researchers claimed that the output$input capacity ratio at a network link largely determines the required buffer si+e! &f the output$input capacity ratio is lower than one, the loss rate follows a power-law reduction with the buffer si+e and significant buffering is needed PROPOSED SYSTEM .e de ise a 3traffic-aware4 approach which aims to pro ide different ser ices for different types of data streams! 'his approach further reduces the system o erhead! Both mathematical analysis and simulation demonstrate that the proposed architecture together with its algorithm reduce the o erall SR"# requirement significantly while pro iding guaranteed performance in terms of low time comple%ity, upper bounded drop rate, and uniform allocation of resources! MODULES Source &t loads data and sends data to its router /source router*! Source Router Source router uses leaky bucket mechanism to maintain the buffer in a ailable bandwidth! Main Router #ain router sends the forward packets from source to destination and backward packets from destination to source! &t recei es empty packets from destination to calculate the bandwidth of destination and ack packets to send the ne%t packet to destination!

Destination Router &t sends empty, ack packets to centrali+ed router!

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Distributed Packet Buffers for High-Bandwidth Switches and Routers

Destination Destination recei es the data from destination router!

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