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Tutorial 18.

Microelectric packages - Compact models

Introduction: This tutorial is a case study of a board design. A card supplier is making two package type changes to an existing commercial board. The objective of the thermal simulation project is to see if the selected new packages are likely to function without overheating. In the event of over heating, what kind of thermal management should be recommended? In this tutorial, you will learn how to: Perform a board level simulation with appropriate package models. Determine if the selected new packages can function without overheating. Prerequisites: This tutorial assumes that you have worked on the sample session in the Users Guide and the rst two ANSYS Icepak tutorials of this guide. Problem Description: A designer is to select packages for a new design at the drawing board level. Available information about the board and packages is given. Determine cooling solutions in the event there is overheating.

Figure 18.1: Problem Specication

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Step 1: Create a New Project


1. Copy the le ICEPAK ROOT/tutorials/compact-package/compact-package-modeling.tzr to your working directory. You must replace ICEPAK ROOT by the full path name of the directory where ANSYS Icepak is installed on your computer system. 2. Start ANSYS Icepak, as described in Section 1.5 of the Users Guide. 3. Click Unpack in the New/existing panel. 4. In the File selection panel, select the packed project le compact-package-modeling.tzr and click Open. 5. In the Location for the unpacked project le selection dialog, select a directory where you would like to place the packed project le, enter a project name (i.e., compactpackage-modeling-b) in the New project text eld then click Unpack.

Step 2: Build the Model


This tutorial uses an existing model. ANSYS Icepak will display the model in the graphics window as shown in Figure 18.2. Available information about the board and packages is shown in Table 18.1. Table 18.1: Available Details for Objects in the Model Object PCB # of Occurrences in model 1 Available Power (w) information 1.6 mm thick, FR4 Material, six 1 oz. layers of Copper, 30% coverage for all layers Extruded Aluminum jc = 2.50 C/W None see Table 18.2 232 leads, 40 mm X 40 mm Footprint, 2 mm height 1.5 0.5 2.0 3.5

Heat Spreader for TO-220 packages TO-220 Packages DIP 400 BGA (new package type to the existing board) 232 PQFP (new package type to the existing board)

3 9 6 6 2

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Figure 18.2: Layout of the board to be analyzed

An ounce of Copper is actually the thickness of 1 ounce/sq.ft of plane copper sheet. Using copper density this translates to a thickness of 0.035 mm.

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Table 18.2: Available Information for 400 PBGA Feature Overall package Mold compound Die Die Flag Die Attach Substrate Substrate traces Size (mm) 26 x 26 x 2.15 0.8 18 x 18 x 0.4 Silicon material 80.0 (eective) Material/Cond (W/mK) Other info Where to input this info? Dimensions menu Die/Mold menu Die/Mold menu Die/Mold menu Die/Mold menu Substrate menu Substrate menu

18 x 18 x 0.035 (equivalent) 0.05 mm thick not mentioned 0.4 mm thick FR4 0.035 mm thick Copper

Vias Solder Balls Wire Bonds

Unknown Standard Not mentioned

Not mentioned Solder Usually Gold

4 layers, top and bottom 30% coverage intermediate layers are 100% (plane layers) Number of vias Substrate menu unknown (use 0 for vias) 20 x 20 count, full array Solder menu Die/Mold menu

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Microelectric packages - Compact models

Create the PCB Create a PCB object by clicking on the Create Printed Circuit Boards icon . Then edit the PCB by clicking the PCB object edit icon ( ). Enter the following coordinates: Object type Name Shape/ Type/ Plane XZ Global Coordinates (m) Other properties

PCB

pcb.1

XS YS ZS XE YE ZE 0.0 0.0 0.0 0.25 NA 0.2 see Table 18.1

Go to the Properties tab. Enter the PCB thickness of 1.6 mm for Substrate thickness. Toggle on Fix Values and change the default unit from micron to Cu-oz/f t2 for high and low surface thickness and for internal layer thickness under Tracing layers section. Material information for the PCB is in Table 18.1. This information can be entered for the selected PCB object as shown in Figure 18.3.

Figure 18.3: PCB Edit Form with input based on PCB information in Table 18.1

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Now, you should see the PCB object overlapping the block called PCB. There is no more need for this block. You recreated the PCB object geometry using coordinates of the imported PCB block. Deactivate the block named PCB. Heat spreader for TO-220 devices Since default solid material happens to be extruded aluminum, all three spreaders should have come into the model with correct material specication. Check this information by editing the objects. Modeling Packages This model has four dierent types of objects. Based on available information and our objectives, we shall use dierent compact package modeling capabilities in ANSYS Icepak. TO220 Type Packages There are 9 TO-220 device blocks. Select them all at once by drawing a window with shift+left mouse (see Figure 18.4). Press Shift-I for a 3-D view.

Figure 18.4: Window Selecting Multiple Objects for Simultaneous Edit

You should see all TO-220 devices highlighted in the tree. Please note that only TO-220 objects should be selected. If you see other objects highlighted, please reselect. You can simultaneously edit all of them at once by clicking your right mouse on any one of the selected TO-220 objects in the tree. Select Network under block type. Select Two Resistor under type.

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In order to assign the resistance, we need to identify a reference side. This is the purpose of board side input. We want the resistance to be applied from Junction to the side in contact with the spreader (Max Z side). We can accomplish this in two ways: Designate Min Z side as the Board side and assign the supplier provided resistance value (2.5 C/W from Table 18.1) to Rjc. OR Designate Max Z side as the Board side and assign the supplier provided resistance value to Rjb. Input 1.5 W for Junction power. Click Done to nish operation. You should see all TO-220 blocks turning to resistance type. See Figure 18.5 for inputs to edit frame.

Figure 18.5: Objects Edit Form

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DIP type packages As we did before for the TO 220s, edit the DIPs by right clicking one of the simultaneously selected DIP block objects in the tree. Use default solid material (any material will work, since we are not interested in DIP temperature). Input 0.5 W power in the Total Power eld. Click Done Dip is the package type for which we have the least information. So we are left with two options: Try to get information from supplier. OR Perform a tentative simulation with available information. The options are considered along with the following facts: The DIPs constitute a lower heat ux than the other components in the board. This is an existing design in which the DIPs have been known to run well below their specied temperature even at max power. Based on the above reasoning, it is easier to perform tentative simulation with the available power information. Note, in this context the purpose of DIP package modeling is appropriate accounting of air and PCB heating due to ow over the DIPs. Accurate prediction of DIP temperature is not an objective. PQFP package modeling Internal details are unavailable for the PQFP type package. But based on the exterior details such as lead count, foot print size, and package height information, it is possible to construct a compact model of a typical package for screening analysis. Expand Libraries by click into + sign left to it in the tree menu. Then select Libraries item. Right click to select Search packages. (Note: A package may also be created using either IC package macros or package object.) In the Search package library window enter all known information about the package (such as package type, lead count, package footprint etc.,) as search criteria. Clicking the Search button should return 1 a few of the closest matching packages from the library. Pick the package that is most similar in description to the 232-lead PQFP information available and select Create. Figure 18.6 depicts the package search procedure.
If search does not not return a relevant package, click on the package object icon to create a new package object. After entering the few known information, you may enter reasonable values or defaults for the remaining parameters.
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Figure 18.6: Package Search Procedure

Edit the package object created. Make sure the Package type is QFP. The Model type is Compact Conduction Model (CCM). CCM is a compact model based on geometric simplications that still preserve the original heat transfer pathways of the package. It has been demonstrated 2 that CCM are fairly accurate and boundary condition independent. Other options under Model type are: To model package in full detail. This option is meant for package level modeling. Using this in board or system design will unduly complicate the simulation. To characterize Junction-to-case and Junction-to-board network resistances for two resistance compact model. We will be doing this for the PBGA package. Symmetry is Full. Package thickness is 2.0 mm. Select the Die/Mold tab (The Substrate and Solder tabs show blank interface since QFP type packages do not have solder or substrate.). Enter 3.5 W for Power. Use all other defaults under Die/Mold tab. Click Done. The package thus created is in an arbitrary location. You may use align-face centers icon to position the base center of the created package object with that of the 232PQFP block.
Karimanal, K.V. and Refai-Ahmed, G., Validation of Compact Conduction Models of BGA Under An Expanded Boundary Condition Set, Proceedings of the ITHERM 2002, May 2002, San Diego, Ca, USA.
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There is no more need for the 232PQFP block. Deactivate it. There is another 232PQFP block (232PQFP.1). Create a copy of the rst package object and align with the remaining 232PQFP block. Then, deactivate the second 232PQFP block (232PQFP.1). PBGA package modeling We have fairly comprehensive information about the PBGA type package from the supplier (see Table 18.2). Using this information we can construct a CCM or characterize to determine jc and jb to model it as a 2-resistor network model. The procedure to determine resistance values for a 2-resistor model is described in another tutorial exercise (Microelectronic Package Characterization - Detailed Model). Select all the blocks named 400-PBGA. By right mouse button clicking on any of the selected blocks, you can edit all of them simultaneously. Select Network and Two Resistor options. The board side is the Min Y side of the blocks. Input estimated jc (1.4 C/W) and jb (6.75 C/W) values in the Rjc and Rjb elds respectively. Junction power is 2.0 W. Click Done to nish. Edit the cabinet. Under Properties tab, you have the option to dene the boundary condition (Wall type) for each side of the cabinet. Dene MinX and maxX sides as Openings.

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By editing the Min X side, assign X velocity = 1 m/s for the min X side opening. Click Done to close the opening edit window. The Max X side opening should have the default settings (free opening). All other cabinet boundaries should be Default. Click Done in the Cabinet edit window to conrm changes. You should see the openings on the min and max X sides of the cabinet.

Step 3: Generate a Mesh


Click the mesh icon Select Hexa Unstructured for Mesh Type and Normal for Mesh parameters (Defaults). Toggle on Accept change value checks. Click Generate mesh. Use mesh viewing tools to evaluate your mesh.

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(optional) Create non-conformal assemblies around each package set to reduce the mesh count. As a start, use 3 mm slack values for all sides of each assembly. Resize the assemblies if required. Without non-conformal assemblies, the number of elements is 161000. It is possible to reduce this number by more than half! Display and compare the conformal and non-conformal meshes.

Step 4: Physical and Numerical Settings


Let us solve the board model with a 1 m/s inlet velocity. Expand Problem setup branch in the tree and select Basic parameters and then set the Flow regime to Turbulent under General setup. Expand the Solutions settings branch. Open the Basic settings panel. Click Reset on the Basic settings panel. Then open the Advanced solver setup panel. Note that in the Advanced solver setup panel, under the Linear solver, the solver inputs for temperature have changed. It is advisable to always click the reset button in the Basic settings panel before starting the solver. Set the number of iterations to 200 in the Basic settings panel.

Step 5: Save the Model


Save the model after the model building and meshing is complete. FileSave project

Step 6: Calculate a Solution


Dene point monitors of temperature for 232-Lead PQFP package, DIP, TO-220 and 400-PBGA1 objects. A point monitor will be created to monitor the temperature change with iterations (Figure 18.7). Go to SolveRun solution and switch on the Enable sequential solve of ow and energy equations option under the Advanced tab. Click Start solution.

Step 7: Examine the Results

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Figure 18.7: Monitor Point Denition

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First we would like to get an idea of the general temperature distribution pattern on the board. Create object face contours of the PCB by clicking the Object face icon ( ). Note the higher temperatures in the parts of the PCB under the PQFP packages. Click on Report main menu and select Network block values. Message window will list all network block temperatures. Network junction temperatures can also be obtained from the overview report. The closeness of the PBGAs to each other is a cause for their overheating. How much is the problem due to the temperature of the air approaching these components? A picture of the thermal boundary layer over the PBGAs can be seen by taking XY cut plane of temperature contours over the PBGA blocks. What is the cause for the somewhat high temperatures of the TO-220 devices? Are the heat spreaders too close? If so, the air owing between the spreaders will overheat preventing further heat dissipation to the air. You can nd out if this is the case by creating XZ cut planes of vectors and contours that cut across the spreader blocks. The highest temperatures are in the 400-PBGA blocks. Eective cooling solutions can be designed by understanding heat ow pathways. Generate a summary report of heat ow for selected 400-PBGA blocks. By deactivating the button under Comb in the summary report panel, you can generate an itemization of heat ow through each of the sides of the object. ).

Probe temperatures values at desired location after clicking on probe icon (

Step 8: Summary
In this tutorial, you performed a board level simulation and determined cooling solutions in the event there is overheating.

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Step 9: Additional Exercise


Post-processing showed that the components of 400-PBGA are the most critical object since they are the hottest. Here are some cooling ideas to set up and perform ANSYS Icepak simulations: What if... 1. The ow is in the negative X direction? 2. The ow is in the negative X direction, and by judicious use of ow resistances, more ow if diverted toward the PBGAs (for the same overall ow rate)? 3. The bottom side of the PCB is not dissipating any heat as a result of lying on domain boundary. On the other hand, there seem to be plenty of space above the board. The main reason for the headroom above the PCB is the height of the spreader blocks. While there is room to move up the spreader by a little bit, more room can be gained if the spreader is longer in the X direction but shorter in Y height. What if both sides of the PCB are exposed to airow by moving it up? 4. A heatsink is mounted on the PBGA blocks? Will it be possible to use on heatsink in contact with all PBGAs? Are there any practical issues?

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