An Analog Decoder for Concatenated Magnetic Recording Schemes

A. Graell i Amat, G. Montorsi

Politecnico di Torino Corso Duca degli Abruzzi 24 10129 Torino, Italy

A. Neviani, A. Xotta
Universt` a di Padova Via Gradenigo 6A 35131 Padova, Italy

Abstract This paper presents an all-analog iterative decoding network for an EPR4 magnetic recording system. A powerful serially concatenated architecture is considered, consisting of a simple outer code, an interleaver with reasonable size and a rate 1 EPR4 channel as inner code. The analog chip design is based on analog 0.18m CMOS technology. Simulation results for both digital and analog implementations are shown. Practical implementation issues such as considerations of mismatch effects over performance are also discussed.

I. I NTRODUCTION Iterative decoding of high-performance error correcting codes is computationally demanding. Traditionally, decoding of such codes has always been implemented digitally. Recently, analog implementations of the decoder have been considered for their promises to outperform digital implementations in speed and power consumption. The principle of the iterative decoding of concatenated codes with interleavers (turbo codes) consists of exchanging probabilistic (soft) information between the constituent decoders [1]. The process is iterated several times to improve the decoding reliability, and bit decisions are made in the nal iteration. The constituent decoders operate with signals that represent probabilities or likelihood ratios, which are real numbers. Digital implementations of such decoders require sequential or pipelined operations with high accuracies, and are quite demanding in terms of hardware complexity and speed. Recently, some researchers have noticed that soft-input softoutput (SISO) algorithms such as BCJR, SOVA and the sumproduct algorithm in general, can be implemented using an analog VLSI network. The principle of these networks is based on the exploitation of the non linear characteristics of transistors and systems that can reach a global precision despite of the presence of rather inaccurate subsystems [2]. Prior related works include analog Viterbi decoders that are already employed in magnetic recording [3]. More recently, two groups have extended the implementation of analog VLSI decoders to the BCJR algorithm [4][5][6][7]. With two different, but essentially equivalent, approaches, their works suggest that analog decoders can offer higher performance in terms of speed and/or power consumption when compared to a digital implementation. This characteristic makes the analog approach very attractive for applications requiring high data rate
1 This work has been partially supported by ST Microelectronics and Qualcomm Inc.

and/or low power consumption such as optical networks, mobile receivers and magnetic recording systems. Although in [5] simulation results for more complex codes are reported, the implementation details of all previous works are limited to single, simple tail-biting trellis codes, with very short block lengths and thus not suitable for practical applications. Finally, in [8] a CMOS implementation of an (8,4) Hamming decoder is presented. To our knowledge, this is the rst CMOS implementation of an analog decoder. In this paper, we go a step beyond considering a complete turbo-like encoding system and a sufciently large block length. In particular, we consider a serially concatenated architecture where the inner encoder is the precoded partial response channel typical of actual magnetic recording systems and the outer encoder is a single convolutional encoder. Although we have focused on the magnetic recording application, where high speed and low power consumption are the major requirements for a suitable coding-decoding scheme, our results can obviously be applied to any concatenated encodingdecoding architecture. Following the philosophy of [7], we design a complete allanalog decoding network that implements two SISO modules joined by an interleaver. The network consists of a reduced number of different trellis modules that implement the fundamental computations of the SISO algorithm. The probability operations in a trellis section can be implemented using a modied version of the so-called Gilbert multiplier [2]. A complete turbo decoding network can be implemented exploiting the nonlinear behavior of subthreshold CMOS technology. II. F UNDAMENTALS OF THE A NALOG I MPLEMENTATION Iterative decoding algorithms, and probability propagation networks in general, can be implemented using analog transistor circuits. In such networks, probabilities are represented through current vectors, while voltages represent loglikelihood ratios. Thus, for the iterative decoding of turbo codes case, two approaches are possible, which correspond to the multiplicative and the additive version of the SISO algorithm, respectively. For the design of our analog decoding network we follow the construction principles pointed in [7], based on the use of currents, i.e., the decoder presented here is an analog implementation of the SISO algorithm in terms of probabilities.

0-7803-7400-2/02/$17.00 2002 IEEE

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AWGN nk

yk Channel SISO

uk

uk

Conv. code

ck

de-punct.

Outer SISO

xk

precoder

recording channel
2

Equalizer

yk

outer encoder precoded EPR4 channel: (1D )/(1+D-D -D ) inner encoder

2 3

punct.

Fig. 2. Decoding system.

Fig. 1. Encoding system the for magnetic channel. As shown in Fig. 1, the system to be considered can be viewed as a serially concatenated scheme where a convolutional code serves as outer encoder while the magnetic channel acts as the inner encoder. The input data sequence u is fed to a rate 1/2 convolutional encoder. A higher code rate is obtained by puncturing. The punctured sequence is then passed through a pseudo-random interleaver, , resulting in the channel input sequence x. An interleaver block dimension of N = 540 bits (corresponding to 480 user bits) is used, which showed to be a good trade-off between performance and decoding complexity. The corresponding decoder suitable for a digital implementation is reported in Fig. 2. It consists of two constituent softinput soft-output (SISO) decoders, one matched to the outer code and the second matched to the channel. Seeking a good trade-off between magnetic recording requirements (related to very low BER and a high rate) and the constraints of the decoder analog implementation (i.e., low complexity) we have decided to choose as outer encoder a rate 8/9 encoder obtained by puncturing a simple recursive systematic 4-state, rate 1/2, mother code. This code is described by the polynomials (in octal form) g1 (D) = 7, g2 (D) = 5, where g1 (D) is the feedback polynomial and g2 (D) is the feedforward polynomial. For the analog decoder network we have focused on the tailbiting termination of this code. In this case, the encoder in a form suitable for analog implementation consists of the four state tailbiting trellis concatenating 480 trellis sections. We assume that the channel is equalized to a target polynomial of the form (1 + D D2 D3 ) (EPR4 channel). As shown by Benedetto et al. [14], to achieve high coding gain a serial concatenated scheme should use a recursive encoder as the inner encoder. Here, the precoder 1/(1 D2 ) is employed to make the channel recursive. The precoded EPR4 channel lends itself naturally to a rate 1 inner recursive convolutional encoder in which the output alphabet differs from the input alphabet. The analog decoding network is now dened over the trellises of the two constituent encoders, i.e., the convolutional encoder and the magnetic recording channel. In Fig. 3 we show the analog network corresponding to the encoder. The whole turbo decoder is obtained by connecting via interleaverdeinterleaver structures the two constituent decoders. Each signal line in Fig. 3 represents a probability distribution while each module is an elementary module of the form (1). The overall networks are a direct implementation of the SISO algorithm. The type-A modules precompute the branch

The analog network consists of interconnected circuit modules that implement the fundamental computations of the SISO algorithm. Although the number of modules may be large, according to the trellis complexity and codeword block size, the number of different modules is very low. Each module is a device that accepts at the input the probability distributions pX (x), pY (y ), and outputs the probability distribution pZ (z ) according to pZ (z ) =
xX y Y

pX (x)pY (y )f (x, y, z )

z Z

(1)

where f is a function X Y Z {0, 1} dened through a trellis and is an appropriate scale factor that does not depend on z . Note that all basic computations of the SISO algorithm are in the form of (1). The multiplicative operation of (1) can be realized using a modied Gilbert cell, a well-known building block of analog VLSI that performs the multiplication of two currents [2]. The sum of partial products in (1) is then implemented adding the correspondent current signals. Thus, representing probabilities through currents we can implement the probability processing involved in the SISO algorithm using an analog network. The elementary devices of such network are CMOS transistors operating below threshold where they show the required exponential behavior with extremely low power consumption. III. T HE S YSTEM The original turbo codes were designed for memoryless AWGN channels, bringing the system performance very close to the Shannon Capacity limit [9]. Iterative decoding techniques have then been extended to cope with intersymbol interference (ISI) channels in the form of turbo equalizers [10]. Treating the channel as a rate-1 convolutional encoder, soft information on channel inputs can be estimated using SISO algorithms. Considerable work has been performed recently in [11][12], investigating the application of turbo decoding to partial response channels. A reduced complexity turbo equalization scheme [13] uses only a single convolutional encoder followed by the PR channel. The corresponding detector needs only two APP modules, which reduce signicantly the decoding complexity, and still retain the good performance of more complex schemes.

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00 k ,k +1

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Fig. 3. The outer analog decoder.

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metrics, the type-B and type-C modules perform the f orward and backward recursions on the trellis, respectively. The typeD modules perform the forward-backward metrics multiplications required in the decoding algorithm and, nally, the type-E and type-F modules complete this operation to obtain the extrinsic information passed to the other decoder and the a posteriori probabilities of the user bits, respectively. As opposed to the digital implementation, where the decoding process is iterated many times before making the nal decision, the analog network undergoes a transient depending on its time constants and settles to a steady state hopefully corresponding to the data sequence. A. The channel analog decoder The channel decoder is fed with the demodulator soft outputs, consisting of the probabilities p(yi |ai ) of symbols received from the channel, where y = [y0 , . . . , y539 ] is the channel output sequence. The partial response EPR4 is characterized as a ve level output alphabet and thus each ai can take values ai = {4, 2, 0, 2, 4}. The second input p (xi ; I ) corresponds to the a priori information of data symbols provided, after interleaving, by the outer decoder. The probabilities p(yi |ai ) are processed by the network, which provides the extrinsic probabilities of the information symbols of the inner encoder (i.e., the channel). These informations are passed through the inverse interleaver and the de-puncturer, whose outputs will be used as a priori information by the outer SISO. The interleaver is realized by hardware wiring between the VLSI sub-blocks, while the de-puncturer is implemented setting the corresponding SISO outer inputs to a suitable current value. B. The outer analog decoder The inputs to the type-A modules are the probabilities p (ci ; I ) corresponding to the two code symbols in a trellis section. The outer decoder computes the probabilities of both code and information symbols based on the code constraints. The type-F modules output the a posteriori probabilities of information symbols that will be used to recover the information

0010 dk 11 0100 dk 11 10 ~ 10 d 1001 k p c k ,k +1 ; I d 1111 k

( (

) )

module E(II)

module F

Fig. 4. The computational modules of the outer decoder.

bits. On the other hand, the type-E modules provide the outer code symbols probabilities, which, after interleaving, are fed back to the channel decoder. Note that the network is characterized by the presence of two closed loops due to the tailbiting termination of the code: now the codewords correspond to those paths through the trellis which start and end in the same state. The computational modules are specied in Fig. 4. For clarity, the type-E module has been divided into two modules, corresponding to the rst and second bits of the pair c = (ck , ck+1 ) (modules E(I) and E(II), respectively). IV. T RANSISTOR LEVEL DESIGN The circuit level design of the decoder was performed using a 0.18 m CMOS technology working with a single power supply of 1.8 V. A block diagram of the decoder implementation is shown in Fig. 5. The 540 5 demodulator soft outputs required to feed the decoder (see section III.A) are derived from the equalized channel output by the serial-to-parallel converter. This consists of an array of sample-and-hold plus an additional translinear block to convert each channel output sample into the corresponding probability p(yi |ai ). The decoder core includes the blocks shown in Fig. 3, except for the quantizer, which is realized as an array of 480 current comparators plus some additional logic to serialize the digital output in a sequence of 8-bit words. The high degree of parallelism of the decoder has an impact on the overall size of the peripheral circuitry (1080 elementary sample-and-hold and 480 current comparators are required), and, consequently, on the power consumption, which is comparable to that of the decoder core. Since the precision of the internal signals demanded by the application is limited to 5-6 bits, the design of the peripheral circuits, beside power optimization, resulted non-critical. The circuit corresponding to a B module of the outer SISO decoder is shown in Fig. 6. The bottom nMOS transistor gen-

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540x5

S/P

decoder core

480

Iy
digital NRZ output

Q S/P

1+
Ix
ideal module

analog domain

digital domain

Iz

I z = I z (1 + )

Fig. 5. The block diagram of the decoder implementation.

Fig. 7. Module-level mismatch model.

section V, an optimal value of W = 5.6 mm at IB = 22A was estimated. V. M ISMATCH EFFECTS ON PERFORMANCE The performance of the analog decoder are affected by circuit nonidealities, which are difcult to take into account using time-consuming circuit-level Monte-Carlo simulations. Among those nonidealities, the transistor mismatch is the main one limiting the decoder performance. To estimate the mismatch effect on the decoder error probability performance, we have rst derived and validated a simple statistical model based on extensive circuit-level simulations. That model has been then embedded into each block of the SISO decoders of Figs. 4 and 5, and then simulated using a faster high-level C++ program yielding bit error probability estimate. The model consists in lumping the effect of transistor mismatch into a deviation of the output module currents (i.e., the probabilities) from their ideal values according to the model reported in gure 7, where Iz = Iz (1 + ) (2)

Fig. 6. Schematic of module B.

erates the module bias current. The 8 nMOS transistors connected to the input terminals mirror the input current into the current steering transistors (the other 20 nMOS devices), implementing directly the B module trellis. The output currents are mirrored by the pMOS transistors to be processed by the following stages. Owing to the current-mode approach the various modules are easily cascaded without the need of additional interface circuitry. The total transistor count for the decoder core resulted to be 418,000, which is comparable to the complexity of a state-of-the-art 16-state Viterbi decoder for EPR4 detection [3]. Transistor sizing and biasing is complicated by the fact that the performance and the non idealities (i.e., device mismatch and deviation from pure exponential behavior) at transistor level are not related in a straightforward manner to the performance at system level. An additional problem comes from the difculties in simulating such a large circuit at transistor level. To keep the discussion simple, in this paper we consider only the optimization of the main design parameters, i.e., the module bias current, IB , and the width W of the current steering transistors. Each module consumes on average three times IB due to the fact that the output current is mirrored to more than one module. Increasing the ratio IB /W improves the transistor speed but moves the devices progressively out of the pure exponential regime which is required for a proper analog implementation of equation (1); on the other hand, a faster device response decreases the settling time of decoder loop, which translates into a faster transient towards the asymptotic BER of the analog decoder. Then, setting the value of IB based on the specications on power consumption, W can be chosen to minimize the time allocated to the decoding of each input frame for a given BER. With this procedure and the simulation approach described in

Iz is the output normalized current and Iz is the ideal output current. The parameter has been statistically characterized through circuit-level Monte-Carlo simulations of the most critical individual modules by varying both the input currents and the MOSFET electrical parameters (threshold voltages, current factors, etc.). Thus, turns out to be a random variable depending on both the data and the physical circuit parameters. We have then introduced the modied module into the digital simulator that reproduces the SISO decoders (See Fig. 3), and run extensive simulations. The results are described in next section. VI. S IMULATIONS AND RESULTS Both transistor-level and mixed structural-behavioral simulation based on VHDL-AMS models of the elementary modules proved to be impractical on such a large circuit, so a different approach, based on the simulation of reduced-size decoders (40, 80, 160 and 240 user bits instead of 480) was taken. The simulated 1 second long transient response of a 40-bit decoder to three different input frames is shown in Fig. 8. The rst input frame is decoded quickly without errors; the second frame requires a longer time to be decoded correctly; the third frame, nally, is decoded with 3 errors after 1 s of processing.

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1.00E+00

80 bit
0.7 0.6

240 bit 160 bit FER 40 bit

probability

1.00E-01

0.5 0.4 0.3 0.2 0.1 0

BER, FER

1.00E-02
0 1 2 3 4 5

40 bit

time (us)

80 bit BER 160 bit

Fig. 8. The transient response.

1.00E-03 0
40

240 bit 100 200 300 400 500 600 700 800 900 1000

TD (ns)

35

Fig. 10. BER and FER curves as a function of TD .

1.00E+00

30

wrong bit position

25

9.00E-01 8.00E-01

20

15

P(circuit BER)>abscissa
0 10 20 30 40 50 60 70 80 90 100

7.00E-01 6.00E-01 5.00E-01 4.00E-01 3.00E-01 2.00E-01

10

0
1.00E-01 0.00E+00 4.00E-06

frame

Fig. 9. Bit error position. (x)-Digital decoder (o)-Analog Decoder

5.00E-06

6.00E-06

7.00E-06

8.00E-06

9.00E-06

1.00E-05

1.10E-05

BER

Fig. 11. Complementary cumulative distribution of the bit error probability.

In principle, an ideal analog decoder should yield the same performance of a digital one after a very long number of iterations. In the impossibility to obtain reliable estimates of low bit error rates (BER) using circuit-level simulations (this will be done directly on the chip when available), we plot in Fig. 9 the wrong bit error positions within the frame for a sample of 100 frames decoded by the digital and analog decoders. This sample includes the only 45 frames (over a million simulated frames) that the digital decoder was not able to correct after 100 iterations. A block length of 40 bit, a Eb /N0 = 7 dB and no mismatch were considered. Although the analog decoder presents a slightly worse behavior (161 errors for the analog decoder against 118 for the digital one), a signicant correspondence is observed between the error positions of the two decoders. We also made a comparison using a sample of 100 frames correctly decoded by the digital decoder, and they were decoded without errors also by the analog one. The performance of the analog decoder can be conveniently evaluated in terms of BER and frame error rate (FER) achieved by the decoder as a function of the time TD allocated to the processing of each input frame. This relation determines: (i) the minimum BER achieved by the decoder for a given input SNR; (ii) the maximum channel data rate at which the decoder can work, given the maximum acceptable BER. Fig. 10 reports the BER and FER curves as a function of TD obtained by transistor-level simulations of decoders with frame length up to 240 user bits, which is the largest decoder size that could be simulated in an acceptable time by using thirty powerful work

stations in parallel. The curves refer to a signal-to-noise ratio Eb /N0 = 7 dB. The simulations show that: (i) the asymptotic BER decreases as the decoder size is increased; (ii) the decoding delay seems not to increase drastically as the decoder size is increased. An inverse proportion between the BER at TD = 1 s and the decoder size seems to roughly predict the BER trend. If this trend continues up to 480 bit, then a BER of 6 104 can be estimated. Then, part of the coding gain (3.4 dB with respect to uncoded EPR4) can be traded to further lower the BER to 105 , as required by the magnetic recording application. In this case the data rate would be 480 Mb/s. A TD value increased by 50% for a 480 user-bit decoder would correspond to a user bit rate of 320 Mb/s, with an estimated power consumption of about 500 mW at 1.8 V supply. The effects of transistor mismatch on the decoder performance are shown in Fig. 11. Applying the mismatch model explained in Section V to the digital decoder, we have simulated a set of 321 different decoder circuits and plotted the complementary cumulative distribution of the BER for a Eb /N0 = 7 dB and a block length of 480 bit. In the simulation the parameters of all modules were considered as independent random variables with the distribution derived from the circuitlevel Monte-Carlo analysis. Thus, circuit means a complete set of random variables that completely dene a single analog circuit. As a reference, the BER for the digital decoder is BER = 4.98 106 after 10 iterations. It can be seen from Figure 11 that the mismatch effects on

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performance are not critical. As an example, 90% of the circuits yield a performance degradation less than a factor 2 in the BER. These results are supported by those obtained introducing the mismatch into the analog decoder. For the mismatch simulations at transistor level, we assumed a temperature T = 50o C. Fig. 12 plots the BER as a function of the time TD for various Eb /N0 and with and without the presence of transistor mismatch. Due to complexity considerations, a reduced version of the turbo decoder (40 bit) is considered. It is observed that the mismatch causes a slight performance degradation with respect to the ideal analog decoder. Moreover, we do not expect a dramatic effect of the interleaver interconnects on the decoder performancee for the following reasons: (i) the decoder is a current-mode circuit, with reduced voltage swing in the internal nodes, and much less affected by parasitic capacitances than voltage-mode circuits; (ii) the interleaver is being designed using two metal levels, with a maximum interconnect length which should not exceed a few hundred microns. The corresponding parasitic capacitance should be well below 100 fF, which is not that much for a circuit operating at 1 MHz. VII. C ONCLUSIONS An all-analog iterative decoding network for an EPR4 magnetic channel has been presented. We consider a serially concatenated architecture where the outer encoder is a convolutional encoder and the inner encoder is the EPR4 magnetic channel. The basic components of the analog implementation are simple construction modules based on the encoder trellises. The overall network is realized by using a sequence of such trellis modules which implement the basic computations of the SISO algorithm. We have described the main aspects of the analog decoder design. The circuit level design was performed for a 0.18 m CMOS technology to work with a single power supply of 1.8 V. Both transistor-level and mixed structural-behavioral simulations based on VHDL-AMS have been performed. When compared to the simulation of the digital decoder, they show a good agreement between the two. Moreover, they show that the decoding delay does not increase substantially with the decoder size. To account for the effects of transistor mismatch over performance, we derived a model that characterizes the mismatch at single-module level. Introducing this model into a high-level simulation tool we generated 350 different decoding networks. The results obtained show that the mismatch produces acceptable performance degradations. The circuit design is in a very advanced stage, and the rst samples should be ready soon. The estimated power consumption of the 480 user-bit decoder core at 400 Mb/s (i.e. TD = 1s) is about 500 mW, with a 1.8 V power supply. An additional 150 mW comes from the peripheral circuitry.

1.00E+00

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BER

1.00E-02

Eb/N0=7 dB - Mism Eb/N0=8 dB - Mism

Eb/N0=6 dB - No Mism Eb/N0=7 dB - No Mism

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1.00E-04 0 100 200 300 400 500 600 700 800 900 1000

TD (ns)

Fig. 12. Mismatch effects over performance.

VIII. ACKNOWLEDGEMENTS The authors are very indebted to Prof. S. Benedetto for his discussions, comments and contributions to this paper. Also, the authors are grateful to Mirko Bruccoleri and Giorgio Betti from ST Microelectronics for their helpful assistance. R EFERENCES [1] S. Benedetto et al., Soft-input Soft-output Modules for the Construction and Iterative Decoding of Code Networks, European Trans. on Telecomm., vol.9, no. 2, pp. 155-172, March/April 1998. [2] C.Mead, Analog VLSI and Neural Systems, Addison-Wealey Publishing Company, 1989. [3] K. Fukahori, D. Hutchinson, R. Kuki, K. Saeki, H. Oshikubo, T. Hori and M Leung An analog EPR4 Viterbi detector in read channel IC for magnetic hard disks, 1998 IEEE Int. Solid-State Circ. Conf., pp. 380-381, 1998. [4] M. Moerz, T. Gabara, R. Yan and J. Hagenauer, An Analog 0.25m BiCMOS Tailbiting MAP Decoder, IEEE Proc. Int. Solid-State Circuits Conference, pp. 356-357, San Francisco, Feb. 2000. [5] J. Hagenauer, M. Moerz, and E. Offer, Analog Turbo-Networks in VLSI: The Next Step in Turbo Decoding and Equalization, Symposium on Turbo Codes & Related Topics, Brest, 2000. [6] H.A. Loeliger, F. Tarkoey, F. Lustenberger and M. Helfenstein, Probability Propagation and decoding in Analog VLSI, IEEE Trans. Inform. Theory, vol. 47, no. 2, pp. 837-843, Feb. 2001. [7] F. Lustenberger, M. Helfenstein, H.A. Loeliger, F. Tarkoey and G.S.Moschytz, An Analog VLSI Decoding Technique for Digital Codes, Proc. 1999 IEEE Int. Symp. on Circuits and Systems, vol. 2, pp. 424-427, 1999. [8] C. Winstead, J. Dai, S. Little, C. Myers, C. Schlegel, Y-B. Kim and W-J. Kim, Analog Map Decoder for (8, 4) Hamming Code in Subthreshold CMOS, Intl. Symp. on Inf. Theory, June 2001 [9] C. Berrou, A. Glavieux and P. Thitimajshima, Near Shannon Limit ErrorCorrecting Coding and Decoding: Turbo Codes, Proc. 1993 Inter. Conf. Commun., pp. 1064-1070, Geneva, May 1993. [10] A. Glavieux, C. Laot and J. Labat, Turbo Equalization over a Frequency Selective Channel, Proc. Intl. Symposium on Turbo Codes & Related Topics, Brest, 1997. [11] L. McPheters, S. McLaughlin and E. Hirsch, Turbo Codes for PR4 and EPR4 Magnetic Recording, Proc. 32nd Asilomar Conf. on Signals, Systems, and Computers, pp. 17781782, Pacic Grove, CA, Nov. 1998. [12] W. Ryan, L. McPheters and S. McLaughlin, Combined Turbo Coding and Turbo Equalization for PR4-equalized Lorentzian Channels, Proc. Conf. Information Sciences and Systems (CISS 98), pp. 489493, Princeton, NJ, Mar. 1998. [13] T. Souvignier, M. Oberg, P. H. Siegel, R. E. Swanson, and J. K. Wolf, Turbo Decoding for Partial Response Channels, IEEE Trans. Commun., vol. 48, no. 8, pp. 1297-1308, Aug. 2000. [14] S. Benedetto and G. Montorsi, Design of Parallel Concatenated Convolutional Codes, IEEE Trans. Commun., vol. 44, no. 5, pp. 591-600, 1996.

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