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Features
I Full-carry look-ahead across the four bits I Systems achieve partial look-ahead performance with the economy of ripple carry I Typical add times Two 8-bit words 25 ns Two 16-bit words 45 ns I Typical power dissipation per 4-bit adder 95 mW
Ordering Code:
Order Number DM74LS83AN Package Number N16E Package Description 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Connection Diagram
DS006378
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DM74LS83A
Truth Table
H = HIGH Level, L = LOW Level Input conditions at A1, B1, A2, B2, and C0 are used to determine outputs 1 and 2 and the value of the internal carry C2. The values at C2, A3, B3, A4, and B4 are then used to determine outputs 3, 4, and C4.
Logic Diagram
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DM74LS83A
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage II IIH IIL IOS ICC1 ICC2 Input Current @ Max Input Voltage HIGH Level Input Current LOW Level Input Current Short Circuit Output Current Supply Current Supply Current Conditions VCC = Min, II = 18 mA VCC = Min, IOH = Max VIL = Max, VIH = Min VCC = Min, IOL = Max VIL = Max, VIH = Min IOL = 4 mA, VCC = Min VCC = Max VI = 7V VCC = Max VI = 2.7V VCC = Max VI = 0.4V VCC = Max (Note 3) VCC = Max (Note 4) VCC = Max (Note 5) A or B C0 A or B C0 A or B C0 20 19 22 2.7 3.4 0.35 0.25 0.5 0.4 0.2 0.1 40 20 0.8 0.4 100 34 39 mA A mA mA mA mA Min Typ (Note 2) Max 1.5 Units V V
Note 2: All typicals are at VCC = 5V, TA = 25C. Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 4: ICC1 is measured with all outputs open, all B inputs LOW and all other inputs at 4.5V, or all inputs at 4.5V. Note 5: ICC2 is measured with all outputs OPEN and all inputs grounded.
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DM74LS83A
Switching Characteristics
at VCC = 5V and TA = 25C From (Input) Symbol Parameter To (Output) CL = 15 pF Min tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output C0 to 1 or 2 C0 to 1 or 2 C0 to 3 C0 to 3 C0 to 4 C0 to 4 Ai, Bi to i Ai, Bi to i C0 to C4 C0 to C4 Ai, Bi to C4 Ai, Bi to C4 Max 24 24 24 24 24 24 24 24 17 17 17 17 RL = 2 k CL = 50 pF Min Max 28 30 28 30 28 30 28 30 24 25 24 26 ns ns ns ns ns ns ns ns ns ns ns ns Units
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16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 5 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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