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Clustered Insulated Gate Bipolar Transistor in the Super Junction Concept: The SJ-TCIGBT
Ngwendson Luther-King, Member, IEEE, Mark Sweet, and Ekkanath Madathil Sankara Narayanan, Senior Member, IEEE

AbstractWe report results of comprehensive 2-D simulation evaluation of the rst MOS-controlled thyristor structure employing the super junction concept on a 1.2-kV eld stop structure. In comparison to a standard device, simultaneous reduction in Vc e (sat) and Eo can be achieved in a super junction trench clustered insulated gate bipolar transistor (SJ-TCIGBT). The simulation results show that up to 80% reduction in Eo is possible. Unlike the super junction insulated gate bipolar transistors, there is no signicant increase in the saturation current with the anode voltage or the depth of the pillars. SJ-TCIGBT is a highly promising next generation device concept with record-breaking Vc e (sat)-Eo tradeoff enhancement to improve converter efciency. Index TermsClustered insulated gate bipolar transistor (CIGBT), insulated gate bipolar transistor (IGBT), MOS-bipolar transistor, MOS-controlled thyristor, power semiconductor device, super junction IGBT (SJ-IGBT), Super Junction Trench CIGBT (SJ-TCIGBT), Trench CIGBT (TCIGBT).

I. INTRODUCTION ITH increasing demand for energy efciency in power electronic converters, there is a need to minimize the tradeoff between the ON-state Vce (sat) and the turn-OFF loss (Eo ) in MOS-bipolar devices. In devices such as the insulated gate bipolar transistors (IGBTs) and its variants, this is implemented by controlling anode injection efciency through the anode thickness, its doping, the buffer region design, and carrier life time. For example, the eld stop (FS) is a classic concept with thin silicon, a transparent anode, and buffer structure, which has greatly improved the Vce (sat)-Eo tradeoff in IGBTs and it is widely used in industry [1]. IGBTs are very suitable for low- and medium-voltage applications because of MOS-gate control, low conduction, and switching losses [2][4]. However, it has been shown that a well-designed MOS-controlled thyristor structure with current saturation characteristics and with a wide semiconductor optical amplier (SOA), such as the clustered insulated gate bipolar transistor (CIGBT), can be a more efcient drop-in solution to IGBTs [5][7]. The super junction (SJ) concept was originally invented in the 1980s and involves p and n columns or stripes within the drift

Manuscript received March 24, 2011; revised May 20, 2011; accepted June 23, 2011. Date of current version March 16, 2012. Recommended for publication by Associate Editor A. Lindemann. The authors are with the Electrical Machines and Drives Research Group, The University of Shefeld, Shefeld, S1 3JD, U.K. (e-mail: L.Ngwendson@shefeld.ac.uk; M.R.Sweet@shefeld.ac.uk; S.Madathil@ shefeld.ac.uk). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TPEL.2011.2162965

region of a power device [8][10]. Such structures are charge balanced, i.e., donor and acceptor net charges are equal to zero. It is possible to deplete the stripes at relatively low voltages. Upon depletion, the stripes appear to be an intrinsic layer with a near uniform electric eld distribution to result in a high breakdown voltage (BV) and at electric eld strength value along the SJ layer [11][13]. The SJ concept has been widely applied to achieve record low on-resistance in MOSFET structures with up to 1000 V commercially available devices [14]. In unipolar devices such as the n-channel MOSFETs, however, the p-pillars are not used for conduction and the key is to achieve very high concentration n-pillars to reduce the ON-state resistance. Moreover, fabrication still remains a technological challenge since the deviations from the zero net charge condition or charge balance (CB) allowed are not more than 10% for a given BV rating. Also the high BV demand of small cell pitch size means high aspect ratio for SJ cell design [15], [16]. More recently, the SJ concept has been extended to the IGBTs [17]. The proposed SJ-IGBTs are expected to improve Vce (sat)Eo tradeoff performance compared to the standard IGBTs due to increased drift region doping in the n-pillars and fast switching speed [17], [18]. However, there is a signicant increase in the saturation current with anode voltages which bring about issues associated with turn-OFF and short-circuit performances in planar gate SJ-IGBTs with deep pillars. This can be attributed to the fact that the p-pillars are connected to the grounded p-base. The unavoidable existence of a strong current gain of the vertical p-n-p (p-base and p-pillar/n-drift/p-anode) transistor due to its narrow base (distance from pillars, bottom to anode) causes poor current saturation behavior. This is the case even though the p-anode is designed to be a weak injector (i.e., a transparent anode). Attempts have also been to introduce an n-layer (carrier enhancement layer) underneath the p pillars at the cathode end to suppress the activation of the parasitic p-n-p transistor. To reduce the increase in saturation current with anode voltage, it is possible to locate the p-pillars just below trench gates in a trench IGBT, which will require precise location of ultra-ne pitch p-pillars underneath the trench gates [19]. The planar CIGBT and Trench gate CIGBT (TCIGBT) are a family of MOS-gate controlled thyristor structures experimentally proven at 1.2, 1.7, and 3.3 kV. They show current saturation characteristics and short-circuit performance similar to IGBTs [20][25]. In a conventional CIGBT, a low self-clamping voltage (Vscl ) is required for wide forward bias safe operating area (FBSOA), which necessitates careful control of the n-well implant dose. Recently, PMOS have been introduced into the device along with its NMOS gates to relax this tradeoff [26]. The

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Fig. 1. (a) Half-cell structure of the 1.2-kV SJ-TCIGBT. (b) Equivalent circuit representation of the SJ-TCIGBT. All the NMOS and PMOS gates are connected together to form the gate terminal.

Fig. 2. (a) Conventional TCIGBT with PMOS Turn-OFF gates. (b) Simulated potential distribution within the TCIGBT structure, showing self-clamping protection of the cathode cells from high anode voltages.

issues with SJ-IGBTs can be avoided in the CIGBT/TCIGBT structures because: 1) the p-pillars are wide and truly oating which is necessary for safe turn-OFF; and 2) the unique selfclamping of the cathode cell potential in the CIGBT can be used to control the saturation current density. In this paper we show, through 2-D simulations, that the SJ-TCIGBT concept can result in very low Vce (sat) and Eo simultaneously, while retaining all other desired properties of a MOS-bipolar power device, such as the current saturation, MOS control, snap-back free turn-ON and wide SOA. The Synopsys TCAD Package TMA Tsuprem4 and Medici have been used for process and device simulations [27]. II. SJ-TCIGBT STRUCTURE AND PHYSICS OF OPERATION Fig. 1(a) shows the half-cell of the SJ-TCIGBT and Fig. 1(b) shows its equivalent circuit. The conventional device is shown in Fig. 2(a). All the gates are connected together to form a three-terminal device and the PMOS channels turn ON only when the gate voltage becomes negative during the switching cycle. The TCIGBT structure consists of a number of trench gate cathode cells within a cluster of desired conguration (such as square, hexagon, etc.) surrounded by a common p-well, n-well, and p-base. A number of these clusters form the device active area. The turn-ON MOSFETs link individual clusters and allow

electron current into the drift region to enable turn-ON, while the control MOSFETs enable MOS-gate control over the thyristor forward current in the ON-state. In the SJ-TCIGBT, wide pillars in the range of 48 m can be used because having the PMOS trenches directly over the p-pillars for more efcient turn-OFF is desired. Additionally, the p-pillar width is made smaller than n-pillars to increase its doping level hence lower conductivity. For a given n-pillar doping (typical values range from 1e15 to 5e15 cm3 ), the corresponding p-pillar doping is chosen based on its width to achieve CB. It can be seen that the p-pillars are simply extensions of the oating p-well region to which they are connected, while the n-pillars are similar to the n-drift region under the SJ region. PMOS gates connect the p-well to the pbase. The threshold voltage Vth of the NMOS (Vth NM OS ) is positive while that of PMOS (Vth PM OS ) designed to be zero or a small negative number. The trench gates are all connected; hence, PMOS is activated only during turn-OFF, when Vg < Vth PM OS [26]. The deep p-well/n-drift junction is mainly used to support voltage in the blocking state. The ON-state operation principle of the SJ-CIGBT is the same as that of a conventional device [20][ 25]. For ON-state operation, a gate voltage Vg > Vth NM OS , the cathode is grounded and Vano de > 0.7 V is applied.

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Capacitive coupling between the p-well and p-anode ensures the device turns ON at 0.7 V. This means the main thyristor made up of Tpnp1 and Tnpn is triggered without any snap-back. With increase in anode voltage, when the depletion from the reverse-biased p- base/n-well junction reaches the p-well, the potential of the cathode cell does not increase further (it is said to be clamped or self-clamped) as shown in Fig. 2(b). This self-clamping of the cathode cell potential protects the cathode trenches from high anode voltages to realize wide FBSOA and fast switching. The advantages of PMOS turn-OFF trench gate in the TCIGBT/IGBT technology include: 1) elimination of tight tolerances in the n-well parameters to achieve selfclamping; 2) elimination of turn-OFF failure due to dynamic latch-up because the holes along the PMOS channels during turn-OFF (rather than under the n+ source); and 3) reduced Jsat leading to increased short-circuit endurance times [29]. The presence of the SJ pillars only inuences OFF-state blocking voltage and change the carrier dynamics during the turn-OFF. III. SIMULATION RESULTS Key parameters for simulation are kept identical for the proposed SJ-TCIGBT and the conventional device, such as the device thickness = 100 m, n-drift doping = 8.0 1013 cm3 , Vth NM OS = 5.5 V, PMOS (Vth PM OS ) = 1.0 V, trench pitch = 7 m, trench width = 2 m, and buffer depth and peak doping of 10 m and 2 1016 cm3 , respectively. For the SJ-TCIGBT, the p- and n-pillar widths are 6 and 7 m, respectively. Experimentally obtained cathode and anode diffusion proles have been used within the TCAD Sentaurus software [27] to obtain the results. A. Blocking Voltage For the SJ device to block maximum voltage, the charge Q in the n- and p-pillars should be exactly balanced, i.e., donor and acceptor net charges are equal to zero [see (1)]. The pillars parameters are chosen such that the pillars are completely depleted before breakdown [see (2) [15]. This ensures that the electric eld prole is at and breakdown is dependent on the drift region thickness and not on pillars doping in which case the BV can be expressed as in (3). In an SJ device, perfect CB between the n- and p-pillars is not always possible due to processing variations. The effect of charge imbalance on the device characteristics has been discussed in the literature [4]. The SJTCIGBT is designed such that XP = XN while still maintaining CB in order to align the p-pillars with the PMOS trenches to enhance the turn-OFF efciency. Since the critical charge in the pillars to generate the critical electric eld for breakdown is identical, higher doping densities in the pillars require reducing their widths Q = Nd XN = Na XP QC < si Ec q (1) (2) (3)

Fig. 3. (a) Typical simulated leakage current at Tj = 25 and 125 C. = 10 s. (b) 1-D electric proles just before breakdown occurs for different pillars depth.

BV = EC tpillars

where Ec is the critical electric eld strength, QC is the critical charge, tpillars is the depth or height of the pillars, Nd and Na are the doping concentration of the n- and p-pillar, while XN and XP are their widths, respectively. Fig. 3(a) shows that, prior to breakdown, the leakage current levels in the SJ and conventional devices are similar. At lower blocking voltages, the SJ leakage is slightly higher due to increased p-n junction perimeter within the device but due to lower peak electric eld in SJ device [see Fig. 3(b)], its leakage current does not increase drastically thereafter. The 1-D electric eld plots in Fig. 2(b) are taken just before breakdown occurs at Tj = 125 C for n-pillar doping of 1.5e15 cm3 : the pillars depths are 90, 70, 50 m and conventional device with corresponding BVs of 1420, 1355, 1250, and 1200 V, respectively. Fig. 2(b) shows the at electric eld distribution within the pillars with little peaks at their top (p-well/n-pillar junction) and bottom (p-pillar/n-drift junction) which is in contrast to the trapezoidal shape electric eld in conventional FS device. However, the peak electric eld in the SJ device can be tailored with pillars depth to be lower than in the conventional device, which is important to reduce Cosmic Ray failure rates [19]. Also, it can be seen that the advantage of deeper pillars is to lower electric elds within the bulk and increase in BV as shown in Fig. 3, because of more effective use of the wafer thickness to sustain high voltage. Fig. 4(a) shows the inuence of pillars doping and CB on BV for 90-m-deep pillars. It can be seen that for n-pillar doping of 1.0e15, 1.5e15,

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Fig. 4.

Inuence of pillars depth on BV at Tj = 25 and 125 C. = 10 s.

Fig. 6. (a) Simulated inuence of pillars depth on ON-state IV characteristics. (b) Saturation current density of 1.2-kV SJ-TIGBT in comparison with a conventional device. Vg = + 15 V and lifetime = 10 s.

can be reduced from 100 to 85 m in the SJ-TCIGBT. However, as shown in Fig. 4, the BV is dependent on the pillar depths into silicon; hence, this must be taken into consideration if wafer thickness reduction is considered. Fig. 5(b) shows potential contours in the blocking mode at 1200 V. As can be seen, the distance between two consecutive potential lines remains constant throughout the depleted SJ region, which indicates that the electric eld has a constant value. The lateral eld component perpendicular to the vertical p-n junctions is responsible for the depletion of the SJ pillars and generates the wave-like pattern of the equipotential contour lines. There are no indications that the blocking performance is limited by the second breakdown [28], [29].
Fig. 5. (a) Inuence of n-pillars doping on CB at Tj = 25 C. (b) Equipotential lines across the device during the blocking state while supporting 1200 V.

B. ON-State Performance Fig. 6(a) shows that for identical anode and buffer, the SJ pillars do not inuence the Vce (sat), while Fig. 6(b) shows that Jsat is only slightly inuenced. Depending on the anode doping, the pillars doping in the range of 1 to 5e15 cm3 is at least an order of magnitude lower than the ON-state excess carrier density due to thyristor mode of conduction [see Fig. 7(a)]; hence, the pillars do not affect Vce (sat) for anode doping greater than 5e17 cm3 . It is evident from Fig. 5(a) that a very low Vce (sat) of 1.1 and 1.25 V can be achieved at Tj = 25 and Tj = 125 C, respectively, at J = 100 Acm2 . The self-clamp phenomenon in the CIGBT/TCIGBT device concept enables the saturation current density of the SJ-TCIGBT to be kept low for a

and 2.0e15 cm3 , the BVs are 1525, 1420, and 1380 V, respectively, in comparison to only 1200 V for the conventional device with drift doping of 8e13 cm3 . CB is as dened in (4), where QN is the donor charge, QP is the acceptor charge, and Q0 is the balanced charge, which is equal to QN or QP at QN = QP : CB = QP QN . Q0 (4)

The results in Fig. 5(a) represent up to 15% higher BV compared to the standard device which means the wafer thickness

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Fig. 8.

Inductive switching circuit.

Fig. 7. (a) Comparison between background doping and excess carrier concentration in the ON-state of SJ-TCIGBT where the pillar depth is 80 m, anode doping is 5e17 cm3 at Tj = 25 C, and (b) current ow lines in the ON-state showing uniform distribution within the pillars and n-drift region. Vg = + 15 V.

trench device. More importantly, since the p-pillars connected to the p-well are oating, Jsat does not increase signicantly with anode voltage in contrast to the SJ-IGBT where Jsat is several thousand amperes with VGS = 15 V [17]. As shown in [17], the magnitude of Jsat can be further tailored with increased buffer doping because since the p-anode is only 1 m thick the peak buffer doping inuences the plasma distribution and Vce (sat). In Fig. 7(a), minority or majority carriers is with respect to the doping type of the pillars in the SJ area. It can be seen that outside the SJ region, i.e., the n-drift region, the hole and electron (or minority and majority carrier) densities are equal. The ON-state current ow-lines in Fig. 7(b) show that the SJ pillars are completely transparent to the carriers, and current ow is uniform. Again, this is unlike in the SJ-IGBT in which, at the cathode side, plasma tends to segregate and unipolar current ows in p- and n-pillars, resulting in higher Vce (sat) at same current density. C. Inuence of Pillars Depth on Inductive Switching Performance Fig. 8 shows the inductive switching circuit used in the simulations, while Fig. 9(a) and (b) shows the inuence of pillars depth on turn-OFF current waveforms and the Vce (sat)-Eo tradeoff, respectively. It can be seen that the Vce (sat)-Eo tradeoff is signicantly improved with deep pillars as a result of

Fig. 9. (a) Inuence of turn-OFF current waveforms on pillars depth for peak anode doping of 5e17 cm3 . (b) Inuence of pillars depth on Vc e (sat)-Eo tradeoff. J = 100 Acm2 (1 A = 1 Acm2 ). Each line is a variation of peak anode doping from 5e17 to 1e19 cm3 with xj = 1 m Va n o d e = 600 V, = 10 s, Vg = 15 V, Lp a ra = 150 nH, and Rg = 22 .

reduced tail current. Fig. 8(b) shows that deep pillars result in shorter current tails hence require increased anode doping (or anode injection) to avoid oscillations. Fig. 10 shows the inuence of pillars depth with respect to anode and buffer doping for the on-set of oscillations in the turn-OFF waveforms. It should be noted that if the buffer is increased, the anode also needs to be increased accordingly to avoid oscillations. The turn-OFF process of the SJ-TCIGBT can be understood by studying the inuence of the p-pillars on the carrier dynamics during turnOFF as shown in Fig. 11(a)(d). At low anode voltages such as 50 V, as shown Fig. 11(a), there is no electron ow from the

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Fig. 10. Example of the inuence of pillars depth with respect to buffer and anode doping for on-set of oscillations. Buffer depth is 10 m, anode junction 1 m, and Tj = 25 C.

MOS channels and a depletion layer begins to develop from the p-well/n-pillar and p-pillars/n-pillar junctions. Fig. 11(b) shows that at only 100 V, excess holes ow only within the p-pillars while at high anode voltage of 600 V, as shown in Fig. 11(c), all the pillars are fully depleted. Fig. 11(d) shows that holes from the p-pillars ow into the p-well then through the PMOS channels that are now inverted since Vg is negative, into the cathode contact. The switching speed is increased because within the SJ section, where the pillars are located, there is a vertical and lateral movement of the depletion layer from the p-well/n-pillar and p-pillar/n-pillar junctions, respectively. Hence, the n-pillar regions deplete fast as excess carriers are squeezed toward the bottom of the pillars. Therefore, the strength of the p-pillars in the SJ-TCIGBT device technology is that they act as extensions of the p-well region (i.e., like p-well ngers into the drift region) and increase the efciency of excess holes collection from within the n-drift region. The PMOS channel shorts the p-well/p-pillars to the cathode and kills off the activity of the parasitic p-well/n-well/p-base transistor, during turn-OFF. Between the bottom of the pillars and the anode, there is only a vertical movement of the depletion edge; hence, if the pillars are not sufciently deep, they will have less inuence on turn-OFF speed and Eo as shown in Fig. 9(b). In summary, the results in this section show that for very deep pillars and low anode doping (i.e., low anode injection and excess carrier concentration), the switching speed can be very fast, leading to oscillations. However, the switching speed can be slowed, and oscillations in the turn-OFF waveforms can be avoided, by increasing the anode doping without signicantly increasing the current tail [see Fig. 9(a) and (b)]. Increased anode doping means reduction in Vce (sat). D. Inuence of Temperature on Vce (sat)-Eo Tradeoff Performance Fig. 12 shows that with deep pillars and increased anode injection, a more competitive Vce (sat)-Eo tradeoff can be achieved. It can be seen that up to 80% lower Eo is possible with the SJ-TCIGBT compared with the conventional device. Each line is a variation of anode doping from 5e173 to 1e19 cm3 with junction depth = 1 m. Moreover, the combination of increased

Fig. 11. Carrier ow and depletion edge movement during different phases of turn-OFF with Vg = 15 V. (a) Beginning of turn-OFF, Va n o d e = 50 V. (b) Voltage rise phase, Va n o d e = 100 V. (c) Tail current phase, Va n o d e = 600 V. (d) Holes owing through the PMOS channels during the current tail phase.

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Fig. 12. Vc e (sat)-Eo tradeoff at J = 100 Acm2 and 175 Acm2 , 1 A = 1 Acm2 , Rg = 22 , pillars depth = 90 m, SJ trench width = 1 m, and = 10 s. Each line is a variation of anode doping from 5e17 to 1e19 cm3 .

anode doping and increased effectiveness of p-pillars in removing excess holes from within the drift region, mean a smaller increase in current tail with increasing junction temperature, resulting in reduced temperature coefcient of Vce (sat) and Eo as evident from very little change in the current and voltage waveforms at Tj = 25 and 125 C shown in Fig. 13(a) and (b), respectively. Therefore, since excess holes are efciently removed from the drift region through the p-pillars, the requirement of a highly transparent anode is not needed to achieve low Eo . The p-pillar doping corresponding to the maximum BV from Fig. 5(a) has been used in all Eo calculations but as will be shown in the next section, higher p-pillar doping can further reduce turn-OFF loss. E. Inuence of Pillars Doping and CB on Eo Fig. 14 shows the inuence of CB on the turn-OFF energy loss Eo . It shows that Eo decreases with increased p-pillar doping (more positive CB), while Eo increases with a decrease in p-pillar doping (more negative CB). It also shows that the magnitude of the change in Eo for negative CB increases with decreased p-pillar doping, while it is constant for positive values. Note that the p-pillar doping increases with that of n-pillar to satisfy CB conditions. The inuence of the p-pillar doping on Eo can be explained by taking another look at the turn-OFF process of the SJ-TCIGBT depicted by Fig. 11(a)(d). All the minority carriers (excess holes) leave the n-drift mainly by owing along the p-pillars. The conductivity of the p-pillars, therefore, becomes important in determining the turn-OFF speed, hence Eo , of the device. The conductivity of a strip of semiconductor is directly related to its doping as expressed as (5). Fig. 14 shows that the CB versus BV curves are slightly skewed toward the right and where there is less inuence of CB on Eo for different pillars doping. From the manufacturing point of view, this means to harness the full benets of the SJ-TCIGBT it is best to; 1) avoid very high n-pillar doping to increase manufacturing tolerance; and 2) dene the p-pillar doping slightly on the positive side of CB for maximum tolerances of BV, where change in Eo due to pillars doping is minimal as well. It should also be noted that using pillar doping of slightly
Fig. 13. (a) Inuence of peak anode doping on turn-OFF current waveform. (b) Inuence of peak anode doping on turn-OFF voltage waveforms. Anode doping variation is from 5e17 to 1e19 cm3 .

Fig. 14. Simulated inuence of CB on Eo for different n-pillar doping. Switching current = 100 A at J = 100 Acm2 and Vb u s = 600 V.

positive CB will further reduce Eo up to 25% compared to the results shown in Figs. 6(b) and 10. On the other hand, more negative CB will result in increased loss with reduced pillar doping performing worse.

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processing steps are IGBT-compatible processes. The SJ pillars suggested in this paper can be produced in a similar way to those for commercial SJ-MOSFETs. The layout of the TCIGBT or SJ-TCIGBT active area is also slightly different from that of the TIGBT or CSTBT; however, the trench densities within the active area are of the same order [25]. As discussed in [26], the PMOS gates have been included in the SJ-TCIGBT to eliminate tight control over the n-well parameters hence remove processing challenges to achieve the diffused layers without degrading device performance. V. CONCLUSION The results reported in this paper show that the SJ-TCIGBT is a device concept that can provide very low Vce (sat) and Eo simultaneously due to thyristor conduction and internal device physics. This is impossible in conventional transistorbased technologies such as the IGBTs. Turn-OFF loss can be reduced by more than 80% and a signicant reduction in the temperature coefcient of Vce (sat) and Eo at Tj = 125 C is possible. While there is a very weak dependence of Jsat on the pillars depth, Jsat and hence short-circuit withstand time can be controlled by the buffer doping. Therefore, the SJ-TCIGBT is a highly promising next generation device concept for the enhancement of converter efciency. REFERENCES
[1] T. Laska, M. Munzer, F. Prsch, C. Schaeffer, and T. Schmidt, The eld stop IGBTA new power device concept with a great improvement potential, in Proc. Int. Symp. Phys. Des., 2005, pp. 355358. [2] B. J. Baliga, M. S. Adler, P. V. Gray, R. P. Love, and N. Zommer, Insulated gate rectier (IGR): A new power switching device, in Proc. Tech. Dig. IEDM, 1982, pp. 264267. [3] M. Kitagawa, I. Omura, S. Hasegawa, T. Inoue, and A. Nakagawa, A 4500 V injection enhanced insulated gate bipolar transistor (IEGT) in a mode similar to a thyristor, in Proc. IEDM Tech. Dig., 1993, pp. 679682. [4] H. Takahashi, H Haruguchi, H. Hagino, and T. Yamada, Carrier stored trench-gate bipolar transistor -A novel power device for high voltage application, in Proc. Int. Symp. Power Semicond. Devices, 1996, pp. 349 352. [5] L. Ngwendson, M. R. Sweet, and E. M. S. Narayanan, An overview of the recent developments in high-voltage power semiconductor MOScontrolled bipolar devices, in Proc. IEEE Bipolar/BiCMOS Circuits Technol. Meeting, 2009, pp. 198205. [6] E. M. S Narayanan, O. Spulber, M. Sweet, J. V. S. C. Bose, K. Verchinine, N. Luther-King, N. Moguilnaia, and M. M. De Souza, Progress in MOS-controlled bipolar devices and edge termination technologies, Microelectron. J., vol. 35, no. 3, pp. 235248, Mar. 2004. [7] E. M. S. Narayanan, M. Sweet, O. Spulber, J. V. Subhas Chandra Base, and M. M. De Souza, Clustered insulated gate bipolar transistor (CIGBT): A new power semiconductor device, in Proc. of 10th Int. Workshop Phys. Semicond. Devices, 1999, pp. 13071312. [8] D. J. Coe, High voltage semiconductor devices, Europe Patent 0 053 854, 1982. [9] D. J. Coe, High voltage semiconductor device, U.S. Patent 4 754 310, 1988. [10] X. B. Chen, Semiconductor power devices with alternating conductivity, U.S. Patent 5 216 275, 1993. [11] J. Tinhanyi, Power MOSFET, U.S. Patent 5 438 215, 1995. [12] T. Fujihira, Semiconductor device with alternating conductivity type layer and method of making the same, Japan Patent 9701201.1, 1997. [13] S. Shirota and S. Kaneda, A new type of varactor diode consisting of multilayer PN junctions, J. Appl. Phys., vol. 49, no. 12, pp. 60126019, 1978. [14] G. Deboy, M. Marz, J.-P. Stengl, H. Strack, J. Tihanyi, and H. Weber, A new generation of high voltage MOSFETs breaks the limit-line of silicon, in IEDM-IEEE Tech. Dig., 1998, pp. 683685.

Fig. 15. Simulated inuence of buffer doping on the electro-thermal shortcircuit performance. The buffer doping are 1e16, 3e16, and 5e16 cm3 ; pillars depth is 80 m, peak anode doping is 5e17 cm3 , Va n o d e = 600 V, and Vg = + 15 V.

F. Short-Circuit Performance Under short-circuit condition, the device is expected to withstand high power dissipation for a given time typically 10 s. A short-circuit endurance time of 10 s at Vg = 15 V is the industry standard for MOS-controlled devices. The short-circuit endurance time before failure is directly related to the saturation current that is a function of the internal physics of the particular device. The self-clamping feature in the T-CIGBT technology ensures controlled current saturation levels and is the main reason for a short-circuit performance in the technology. Fig. 15 shows more than 15 s short-circuit performance of the SJTCIGBT with deep pillars of 80 m. It can be seen that the saturation current hence short-circuit performance can be controlled by the buffer doping. The room temperature Vce (sat) for increasing peak buffer doping of 1e16, 3e16, and 5e16 cm3 are 1.45, 1.50, and 1.65 V, respectively, at J = 100 Acm2 . More importantly, it can be seen that the SJ-TCIGBT can successfully turn-OFF more than six times the rated current at very high temperatures. The simulation study does not take into account the inuence of 3-D effects due to the layout of the SJ-TCIGBT structure. These factors are unknowns and have the potential to affect thermal dissipation under short-circuit condition especially at high power dissipation levels [29]. The actual SOA and limitations under short-circuit condition can only be fully assessed after experimental testing of real devices. Additionally, the key to achieving a short-circuit performance >10 s in the SJ-TCIGBT is low saturation current density achieved through a low selfclamping voltage usually designed to be <20 V [30]. IV. FURTHER DISCUSSIONS In terms of device processing, compared to a conventional Trench gate IGBT (TIGBT), the TCIGBT structure requires two additional photolithographic masking stages and temperature cycles, whereas compared to advanced IGBTs, such as Carrier Stored Trench Bipolar Transistor (CSTBT) [4], it is only one. Once the p-well and n-well are formed, the remaining

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[15] T. Fujihira and Y. Miyasaka, Simulated superior performances of semiconductor super junction devices, in Proc. Int. Symp. Power Semicond. Devices, 1998, pp. 423426. [16] P. M. Shenoy, A. Bhalla, and G. M. Dolny, Analysis of the effect of charge imbalance on the static and dynamic characteristics of the super junction MOSFET, in Proc. Int. Symp. Power Semicond. Devices, 1999, pp. 99102. [17] F. D Bauer, The super junction bipolar transistor: A new silicon power device concept for ultra low loss switching applications at medium to high voltages, Solid-State Electron., vol. 48, pp. 705714, 2004. [18] M. Antonious, F. Udrea, and F. Bauer, The SJ-IGBT optimization and modelling, IEEE Trans. Electron Devices, vol. 57, no. 3, pp. 594600, Mar. 2010. [19] M. Antonious, F. Udrea, and F. Bauer, The 3.3 kV semi-super junction IGBT for increased cosmic ray induced breakdown immunity, in Proc. Int. Symp. Power Semicond. Devices, 2009, pp. 168171. [20] N. Luther-King, M. Sweet, O. Spulber, M. M. De Souza, and E. M. S. Narayanan, Anode-gated MOS-controlled thyristor with ultra-fast switching capability, in Proc. Int. Symp. Power Semicond. Devices, 2003, pp. 299302. [21] K. Vershinin, M. Sweet, O. Spulber, S. Hardikar, N. Luther-King, M. M. De Souza, S. Sverdloff, and E. M. S. Narayanan, Inuence of the design parameters on the performance of 1.7 kV, NPT, planar clustered insulated gate bipolar transistor (CIGBT), in Proc. Int. Symp. Power Semicond. Devices, 2004, pp. 269272. [22] N. Luther-King, M. Sweet, O. Spulber, K. Vershinin, M. M. De Souza, and E. M. S. Narayanan, MOS control device concepts for ACAC matrix converter applications: The HCD concept for high-efciency anode-gated devices, IEEE Trans. Electron Devices, vol. 52, no. 9, pp. 20752080, Sep. 2005. [23] M. Sweet, N. Luther-King, E. M. S. Narayanan, and K. Kong, Experimental demonstration of 3.3kV planar CIGBT in the NPT technology, in Proc. Int. Symp. Power Semicond. Devices, 2008, pp. 4851. [24] O. Spulber, M. Sweet, K. Vershinin, N. Luther-King, M. M. De Souza, and E. M. S. Narayanan, A novel, 1.2 kV trench clustered IGBT with ultra high performance, in Proc. Int. Symp. Power Semicond. Devices, 2001, pp. 323326. [25] K. Vershinin, M. Sweet, L. Ngwendson, J. Thomson, P. Waind, J. Bruce, and E. M. S. Narayanan, Experimental demonstration of a 1.2 kV trench clustered insulated gate bipolar transistor in non-punch-through technology, in Proc. Int. Symp. Power Semicond. Devices, 2006, pp. 181184. [26] N. Luther-King, M. Sweet, and E. M. S. Narayanan, Performance of a trench PMOS gated, planar, 1.2 kV CIGBT in NPT technology, in Proc. Int. Symp. Power Semicond. Devices, 2008, pp. 164167. [27] Synopsys TCAD Sentaurus Device Package, 2007. [28] B. Zhang, Z. Xu, and A. Q. Huang, Analysis of the forward biased safe operating area of the super junction MOSFET, in Proc. Int. Symp. Power Semicond. Devices, 2000, pp. 6164. [29] A. Hefner, Analytical modelling of device-circuit interactions for the power insulated gate bipolar transistor (IGBT), IEEE Trans. Ind. Appl., vol. 26, no. 6, pp. 9951005, Dec. 1990. [30] N. Luther-King, E. M. S. Narayanan, L. Coulbeck, A. Crane, and R. Dudley, Comparison of Trench Gate IGBT and CIGBT devices for increasing the power density from high power modules, IEEE Trans. Power Electron., vol. 25, no. 3, pp. 583591, Mar. 2010.

Mark Sweet received the B.Sc. (Hons.) degree in electronics engineering and the Ph.D. degree in highvoltage microelectronics from De Montfort University, Leicester, U.K., in 1998 and 2004, respectively. From 2001 to 2007, he was a Research Fellow in the Emerging Technologies Research Centre, De Montfort University, where he was engaged in the eld of vertical power semiconductor devices, which involved designing and characterizing vertical and lateral power semiconductor devices for a wide range of voltage ratings. In 2007, he joined the University of Shefeld, Shefeld, U.K., as a Research Fellow, and worked in the eld of converter power density. His current research interests include highvoltage power semiconductor device technologies, power microelectronics, and test/characterization techniques. Dr. Sweet is a member of the Institution of Engineering and Technology (IET).

Ekkanath Madathil Sankara Narayanan (M87 SM00) was born in India, in 1962. He received the B.Sc. and M.Sc. degrees from PSG College of Technology, Coimbatore, India, the M.Tech. degree from the Indian Institute of Science, Bangalore, India, and the Ph.D. degree from the University of Cambridge, Cambridge, U.K. He was a Maudslay Engineering Research Fellow with Pembroke College, Cambridge and Research Associate with Engineering Department, Cambridge University during 19921994. He was the Head of the Emerging Technologies Research Center, Cambridge University, during 1994 2007. He is currently with the Electrical Machines and Drives Research Group, The University of Shefeld, Shefeld, where he holds the Rolls Royce/Royal Academy of Engineering Chair in Power Electronics Systems. His research interests include integrated and discrete power device technologies, design for manufacturability and compact power converters for automotive/aerospace applications, functional materials, thin lm transistors, RF technologies, and technology strategies in microelectronics. He is the author of more than 200 articles and holds seven patents, approved or pending approval. He is a Member of the technical program committees of ISPSD, ISPS, IWPD and other international conferences. Dr. Narayanan is an ex-ofcio Member of the IEEE Ad Com. Committee in the area of compact modelling and an editor of the IEEE TDMR. He is a Fellow of Institution of Engineering and Technology and IOP.

Ngwendson Luther-King (M11) was born in Cameroon. He received the B.Sc. degree in physics from Obafemi Awolowo University, Ile-Ife, Nigeria, in 1997, the M.Phil. degree in semiconductor physics and microelectronics engineering from Wolfson College, University of Cambridge, Cambridge, U.K., in 1999, and the Ph.D. degree in MetalOxide Semiconductor (MOS) controlled high-voltage devices from De Montfort University (DMU), Leicester, U.K., in 2004. He was with the Emerging Technologies Research Center, DMU, as a Research Fellow from 2001 to 2007. He is currently a Research Fellow with the Electrical Machines and Drives Research Group, The University of Shefeld, Shefeld, U.K. His research interests include high voltage ICs and high-performance high-voltage Trench and Planar MOS controlled power devices up to 6.5 kV, novel techniques to achieve advanced fast turn-off and low loss in power semiconductor devices. He is the author or co-author of more than 30 articles in journals and conferences.