Assignment: CO6 Instructions: a) Answer all questions correctly b) Write your answer neatly on A4-sized paper c) On the cover

page, write down: (i) Your name (ii) Your ID (iii) Assignment CO6 (iv) Date submitted d) Submit the assignment latest by 11th May 2012.

Question 1 a) b) Draw the symbol and characteristic table for JK flip-flop and write its characteristic equation. Design a synchronous 3-bit Gray code counter using positive edge triggered T flip-flops. Minimize the number of gates used in your circuit. Provide the required design procedures as listed. i. ii. iii. iv. v. Question 2 A sequential circuit has three flip-flops A, B and C; one input x and one output y. The state diagram is shown in Figure 4 below. The circuit is to be designed by treating the unused states as dont care condition. i) Design and realize the circuit using D flip-flops. 0/0 000 0/0 1/1 0/0 001 0/0 1/1 110 00 0/0 111 00 Table for binary to Gray conversion State diagram State table Flip-flop input equations Circuit diagram

100 10 1/1

1/1

1/1

Figure 4

Question 3 The diagram in Figure-2 shows a synchronous sequential circuit. Analyse the circuit by deriving the following items: (i) (ii) (iii) (iv) (v) Output equation Flip-flop input equations Next state equations State table State diagram

Question 4

Registers often used to store operands and result of arithmetic operations within a micro-controller. A register is essentially made-up of flip flops. A universal shift register has both serial and parallel input and output capability. A logic block symbol of a 4-bit universal shift register is as below:
D0 D1 D2 D3

CLR S0 S1 SR SL CLK

SRG 4

Q0

Q1

Q2

Q3

S0 and S1 are inputs that set the mode of operation (load, shift etc). SR and SL are inputs to be loaded into the register during the shift operation (SR for shift to right, SL for shift to left).

The number of bits a register can handle determine the number of flip flop in the module. The 4 bit shift register above will has 4 flip-flops to hold every data (Di). a) Design a 4-bit universal shift register that has the operation mode as in table 1 below. Use four D flip-flops (with asynchronous reset) and four 4-to-1 MUXes in your design:
Inputs Operation

Reset 1 0 0

S1 X 0 0

S0 X 0 1 Clear Output No operation Parallel Load

0 0

1 1

0 1

Shift Right Shift Left

Table 1
Hints: S1 and S0 are to be connected to MUX selector inputs. MUXs output to be connected to corresponding D flip flop input

b) What is the next state equation for each D flip flop? c) If the parallel input is 0001 and shift right (SR) input is 1, what will the output after parallel
input followed by one shift right operation?

Figure- 2