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8086/8088 - CPU Architecture

The 8 8!"8 88 architecture can be broad#$ di%ided into two &roups' (i) E*ecution Unit (EU) (ii) +us ,nterface Unit (+,U)
20
A dder

ES C S SS D S IP

B u s In te r fa c e U n it
In s t r u c ti o n qu eue

A B C D S B D S

X X X X P P I I

A H (8 ) B H (8 ) C H (8 ) D H (8 )

A L (8 ) B L (8 ) C L (8 ) D L (8 )

G e n e ra l R e g is te r s

C o n tr o l U n it

C o n tro l lin e s

A LU
F la g s

E x e c u tio n U n it

-i& 1.. 8 8! /rchitecture

The e*ecution unit contains the 0ata and /ddress re&isters1 the /rithmetic and 2o&ic Unit and the 3ontro# Unit. The +us ,nterface Unit contains +us ,nterface 2o&ic1 Se&ment re&isters1 4emor$ addressin& #o&ic and a Si* b$te instruction ob5ect code 6ueue (78b$te instruction ob5ect8code 6ueue in case of 8 88 microprocessor). The e*ecution unit and the +us ,nterface unit operate as$nchronous#$. The EU waits for the instruction ob5ect code to be fetched from the memor$ b$ the +,U. The +,U fetches or pre8fetches the ob5ect code (1!8bits at a time) and #oads it into the si* b$tes 6ueue. Whene%er the EU is read$ to e*ecute a new instruction1 it fetches the instruction ob5ect code from the front of the instruction 6ueue and e*ecutes the instruction in specified number of c#ock periods. ,f memor$ or ,nput"output de%ices must be accessed in the course of e*ecutin& an instruction1 then the EU informs the +,U of its needs. The +,U comp#etes its operation code (opcode) fetch c$c#e1 if in pro&ress1 and e*ecutes an appropriate e*terna# access machine c$c#e in response to the EU demand. The +,U is independent of the EU and attempts to keep the si*8b$tes 6ueue fi##ed with instruction ob5ect codes. ,f two or more of these si* b$tes are empt$1 then the +,U e*ecutes instruction fetch machine c$c#es as #on& as the EU does not ha%e an acti%e re6uest for the bus access pendin&. ,f the EU issues a re6uest for the bus access whi#e the +,U is in the midd#e of an instruction fetch machine c$c#e1 then the +,U wi## comp#ete the instruction fetch machine c$c#e before honorin& the EU bus access re6uest. The EU does not use machine c$c#es9 it e*ecutes instructions in some number of c#ock periods that are not sub5ected to an$ t$pe of machine c$c#es. The on#$ time c#ock periods are &rouped is c#ock when the bus contro# #o&ic wishes to access memor$ or ,"O de%ices.

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Execution Unit (EU) The e*ecution unit consists of ;enera# <e&isters /rithmetic 2o&ic Unit 3ontro# unit -#a& <e&isters General Registers The 3=U has ei&ht 1!8bit &enera# re&isters. The$ are di%ided into two fi#es of four re&isters each. The$ are' (a) The data re&ister fi#e and (b) The pointer and inde* re&ister fi#e
A " B " C " " A ! B ! C ! ! A X B X C X X

-i&. 1.7 0ata <e&ister -i#e

/>1 +>1 3> and 0> re&isters are the data re&isters. The upper and #ower ha#%es of the data re&isters are indi%idua##$ addressab#e. /> re&ister can be addressed as /2 and /? re&isters1 +> re&ister can be addressed as +2 and +? re&ister1 3> re&ister can be addressed as 32 and 3? re&ister1 0> re&ister can be addressed as 02 and 0?. The data re&isters can be used in most arithmetic and #o&ic operations. Some instructions howe%er re6uire these re&isters for specific use. This imp#icit re&ister usa&e a##ows a more compact instruction encodin&. -i&.1.7 shows the data re&isters specific one. The inde* re&ister fi#e consists of the Stack =ointer (S=)1 the +ase =ointer (+=)1 Source ,nde* (S,) and 0estination ,nde* (0,) re&isters a## are of 1!8bits. The$ can a#so be used in most arithmetic and #o&ic operations. These re&isters are usua##$ used to ho#d offset addresses for addressin& within a se&ment. Offset addressin& reduces pro&ram si@e b$ e#iminatin& the need for each instruction to specif$ fre6uent#$ used addresses. The pointer and inde* re&ister fi#es are further di%ided into the pointer sub8fi#e (containin& the Stack =ointer and the +ase =ointer re&isters) and the inde* sub8fi#e (containin& the Source inde* and 0estination inde* re&isters). The =ointer re&isters are used to access the current stack se&ment. The inde* re&isters are used to access the current data. (Stack se&ment and data se&ment are specific areas of memor$. Their app#ication wi## be e*p#ained in #ater chapters). Un#ess otherwise specified in the instruction1 stack pointer re&isters refer to the current stack se&ment whi#e inde* re&ister refers to the current data se&ment. The += and S= re&isters are both used to point to the stack1 a #inear arra$ in the memor$ used for subroutine parameters1 subroutine return addresses1 and the data temporari#$ sa%ed durin& e*ecution of a pro&ram The imp#icit re&ister usa&e is as fo##ows' /> <e&ister /2 <e&ister Word 4u#tip#ication Word 0i%ision and Word ,"O Operation. +$te 4u#tip#ication +$te 0i%ision +$te ,"O Trans#ate1 and 0ecima# /rithmetic

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/? <e&ister +> <e&ister 3> <e&ister 32 <e&ister 0> <e&ister +$te 4u#tip#ication +$te 0i%ision. +ase <e&ister Trans#ate Strin& Operations Variab#e Shift and <otate Word 4u#tip#ication1 Word 0i%ision1 ,ndirect ,"O.
-i&. 1.A

4ost microprocessors ha%e a sin&#e stack pointer re&ister ca##ed the S=. 8 8! " 8 88 has an additiona# pointer into the stack ca##ed the += re&ister. Whi#e the S= is used simi#ar to the stack pointer in other machine (for pointin& to subroutine and interrupt return addresses)1 the += re&ister is used to ho#d an o#d stack pointer %a#ue1 or it can mark a p#ace in the subroutine stack independent of the S= re&ister. Usin& the += re&ister to mark the stack sa%es the 5u&&#in& of a sin&#e stack pointer to reference subroutine parameters and addresses. S, and 0, are both 1!8bits wide and are used b$ strin& manipu#ation instructions and in bui#din& some of the more powerfu# 8 8!"8 88 data structures and addressin& modes. +oth the S, and the 0, re&isters ha%e auto incrementin& and auto8decrementin& capabi#ities. Arith#etic !ogic Unit (A!U) /2U is 1!8bits wide. ,t can do the fo##owin& 1!8bits arithmetic operations (i) /ddition (ii) Subtraction (iii) 4u#tip#ication (i%) 0i%ision /rithmetic operations ma$ be performed on four t$pes of numbers Unsi&ned binar$ numbers Si&ned binar$ numbers (,nte&ers) Unsi&ned packed decima# numbers Unsi&ned unpacked decima# numbers The /2U can a#so perform #o&ica# operations such as (i) NOT (ii) /N0 (iii) O< (i%) E>32US,VE O< (%) TEST $lag Register The E*ecution Unit has a 1!8bit f#a& re&ister which indicates some conditions affected b$ the e*ecution of an instruction. Some bits of the f#a& re&ister contro# certain operations of the EU. The f#a& re&ister in the EU contains nine acti%e f#a&s shown in fi&.1.!
01A 017 01. 01: 011 01 0B 08 0C 0! 0A 07 0. 0: 01 0

/-

=-

3-

-i&1 1.! -#a& <e&ister

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Si* of the nine f#a&s are used to indicate some condition produced b$ an instruction. These condition f#a&s are a#so ca##ed status f#a&s of 8 8!"8 88 microprocessor. These are the 3arr$ f#a&1 =arit$ f#a&1 /u*i#iar$ carr$ f#a&1 Dero f#a&1 and Si&n f#a&. The other three 3ontro# f#a&s are Trap -#a&1 0irection -#a& and ,nterrupt f#a&. Con%ition $lags Carr& $lag (C$)

This f#a& wi## be set to one if the addition of two 1!8bit binar$ numbers produces a carr$ out of the most si&nificant bit position or if there is a borrow to the 4S+ after subtraction. This f#a& is a#so affected when other arithmetic and #o&ica# instruction are e*ecuted.
Parit& $lag (P$) This f#a& is set1 if the resu#t of the operation has an e%en number of 1Es (in the #ower 8 bits of the resu#t). This f#a& can be used to check for data transmission error. Auxiliar& Carr& $lag (A$) This f#a& is set1 when there is a carr$ out of the #ower nibb#e to the hi&her nibb#e or a borrow from the hi&her nibb#e to the #ower. The au*i#iar$ carr$ f#a& is used for decima# ad5ust operation. The /- f#a& is of si&nificance on#$ for b$te operations durin& which the #ower order b$te of the 1!8bit word is used. 'ero $lag (') This f#a& is set when the resu#t of an operation is @ero. The f#a& is reset when the resu#t is not @ero. ()er*lo+ $lag (() This f#a& is set1 when an arithmetic o%erf#ow occurres. O%erf#ow means that the si@e of the resu#t e*ceeded the stora&e capacit$ of the destination1 and a si&nificant di&it has been #ost. ,ign *lag (,) This f#a& is set1 when an 4S+ bit of the resu#t is hi&h after an arithmetic operation. When this f#a& is set the data in assumed to be ne&ati%e and when this f#a& is @ero it is assumed to be positi%e. Control $lags 3ontro# f#a&s are used to contro# certain operations of the processor. The app#ication of these f#a&s are different from that of si* conditiona# f#a&s. The conditiona# f#a&s are set or reset b$ the EU on the basis of the resu#t of some arithmetic or #o&ic operations. The contro# f#a&s are de#iberate#$ set or reset with specific instructions inc#uded in the pro&ram. -ra. *lag (-) This is used for sin&#e steppin& throu&h a pro&ram. ,t is used for debu&&in& the pro&rams. (0iscusses with interrupts). /nterru.t $lag (/)

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,t is used to a##ow " prohibit the interruption of a pro&ram. When the f#a& set1 it enab#es the interrupt from ,NT<. When the f#a& is reset ( )1 it disab#es the interrupt. irection $lag ( ) ,t is used for strin& instructiion (0iscussed with the specific instructions #ater in the book). ,f the direction f#a& is set1 the pointers are decremented e#se the pointers are incremented. 01213 Bus /nter*ace Unit (B/U) The +,U sends out addresses1 fetches instructions from memor$1 reads data from memor$ and ports1 and writes data to ports and memor$. ,n other words the +,U hand#es a## transfers of data and addresses on the buses for the e*ecution unit. The +,U has 1. /n instruction 6ueue :. /n ,nstruction pointer .. Se&ment re&isters /nstruction 4ueue To speed up pro&ram e*ecution1 the +,U fetches as man$ as ! insturction b$tes ahead of time from memor$. The prefetched instruction b$tes are he#d for the EU in a first8in8first8out &roup of re&ister ca##ed a 6ueue. The EU decodes an instruction or e*ecutes an instruction which does not re6uire the buses. When the EU is read$ for its ne*t instruction1 it simp#$ reads the instruction from the 6ueue in the +,U. -etchin& the ne*t instruction whi#e the current instruction e*ecutes1 is ca##ed pipe#inin&. Note: The 8 88 microprocessor has on#$ a 78b$te 6ueue. /nstruction Pointer (/P) The ,nstruction =ointer is a 1!8bit re&ister. This re&ister is a#wa$s used as the effecti%e memor$ address1 and is added to the 3ode se&ment with a disp#acement of four bits to obtain the ph$sica# address of the opcode. The code se&ment cannot be chan&ed b$ the mo%e instruction. The instruction pointer is incremented after each opcode fetch to point to the ne*t instruction. ,eg#ent Registers The 8 8! " 8 88 microprocessor has : 8bit address #ines. /## the re&isters in 8 8! " 8 88 are 1!8bits in #en&th. ?ence to obtain : 8bit addresses from the a%ai#ab#e 1!8bit re&isters1 a## 8 8! " 8 88 memor$ addresses are computed b$ summin& the contents of a se&ment re&ister and a effecti%e memor$ address. The effecti%e memor$ address is computed %ia a %ariet$ of addressin& modes. The process of addin&1 to obtain : 8bit address is as fo##ows' The se#ected se&ment re&ister contents are shifted8#eft four bits (i.e.1 the contents are mu#tip#ied b$ 1! decima#)1 and then added to the effecti%e memor$ address to &enerate the actua# ph$sica# address output.
Se&ment <e&ister %a#ue ( 3S1 0S1 ES or SS) Effecti%e 4emor$ /ddress =h$sica# /ddress * * * * * * * * * * * * * * * *? $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $? wwwwwwwwwwwwwwwwwwww? Tab#e 1.1

The tab#e 1.1 shows 1!8bits of the se&ment re&isters 3S1 0S1 ES or SS disp#aced b$ 78bits to the #eft. The effecti%e address is ca#cu#ated dependin& on the t$pe of addressin& mode. The

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effecti%e address is shown as F$$$$$$$$$$$$$$$$G. The : 8bit ph$sica# address FwwwwwwwwwwwwwwwwwwwwG is obtained after addin& the se&ment re&ister %a#ue and effecti%e address. The ph$sica# address is : 8bits wide. To understand how the se&mentation is used1 it is re6uired to know the memor$ structure of the 8 8! " 8 88 microprocessor. The memor$ in an 8 8!"8 88 s$stem is a se6uence of up to : : H one mi##ion b$tes. / word is an$ two consecuti%e b$tes in memor$ (word a#i&nment is not re6uired). Words are stored in memor$ with the most si&nificant b$te at the hi&her memor$ address. These b$tes are stored se6uentia##$ from b$te to b$te ----- he*. =ro&rams %iew memor$ space as a &roup of se&ments defined b$ the app#ication. / se&ment is a #o&ica# unit of memor$ that ma$ be up to !7I b$tes #on&. Each se&ment is made up of conti&uous memor$ #ocations and is an independent1 separate#$ addressab#e unit. Each se&ment is assi&ned a base address1 which is its startin& #ocation in the memor$ space. /## se&ments start on 1!8bit memor$ boundaries. Se&ments ma$ be ad5acent1 dis5oint1 partia##$ o%er#apped1 or fu##$ o%er#apped. ,t is as shown in fi&. 1.C The se&ment re&isters point to the four immediate#$ addressab#e se&ments. The four se&ment re&isters are 3ode Se&ment re&ister Jpoints to the instruction opcodeK 0ata Se&ment re&ister Jpoints to the data memor$K Stack Se&ment re&ister Jpoints to the Stack memor$K E*tra Se&ment re&ister Jpoints to the data memor$K
0 10000 20000 !0000

Segm ent A

Segm ent B

# a r t ia l o e r la ! e $

C o n tig u o u s m e m o r y F u lly o e r la !

S egm ent C S egm ent E S egm ent D

D is " o in t

-i& 1.C
FFFFFH A

B C C S D D S E SS F ES % H

& '''''H

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-i&81.8

-i& 1.8 shows the se&ment re&isters pointin& to the %arious memor$ se&ments. Since #o&ica# addresses are 1!8bits wide1 up to !7I (!AA.!) b$tes in a &i%en se&ment can be addressed. Each time the 3=U need to &enerate a memor$ address1 one of the se&ment re&isters is automatica##$ chosen and its contents added to a #o&ica# address. -or an instruction fetch1 the code se&ment re&ister is automatica##$ added to the #o&ica# address (in this case1 the contents of the instruction pointer) to compute the %a#ue of the instruction address. -or stack referencin& the stack se&ment re&ister is automatica##$ added to the #o&ica# address (the S= or += re&ister contents) to compute the %a#ue of the stack address. -or data reference operations1 where either the data or e*tra se&ment re&ister is chosen as the base1 the #o&ica# address can be made up of man$ different t$pes of %a#ues' it can be simp#$ the immediate data %a#ue contained in the instruction1 or it can be the sum of an immediate data %a#ue and a base re&ister1 p#us an inde* re&ister. ;enera##$1 the se#ection of the 0S or ES re&ister is made automatica##$1 thou&h pro%isions do e*ist to o%erride this se#ection. Thus an$ memor$ #ocation ma$ be addressed without chan&in& the %a#ue of the se&ment base re&ister. ,n s$stems that use !7I or fewer b$tes of memor$ for each memor$ area (code1 stack1 data and e*tra)1 the se&ment re&isters can be initia#i@ed to @ero at the be&innin& of the pro&ram and then i&nored1 since @ero p#us a 1!8bit offset $ie#ds a 1!8bit address. ,n a s$stem where the tota# amount of memor$ is !7I b$tes or #ess1 it is possib#e to set a## se&ments e6ua# and ha%e fu##$ o%er#appin& se&ments. Se&ment re&isters are a#so %er$ usefu# for #ar&e pro&rammin& tasks1 which re6uire iso#ation of pro&ram code from the data area1 or iso#ation of modu#e data from the stack information etc. Se&mentation makes it eas$ to bui#d re8#ocatab#e and reentrant pro&rams. ,n man$ cases1 the task of re#ocatin& a pro&ram (re#ocation means ha%in& the abi#it$ to run the same pro&ram in se%era# different areas of memor$ without chan&in& addresses in the pro&ram itse#f) simp#$ re6uires mo%in& the pro&ram code and then ad5ustin& the code se&ment re&ister to point to the base of the new code area. Since pro&rams can be written for the 8 8! " 8 88 in which a## branches and 5umps are re#ati%e to the instruction pointer1 it does not matter what %a#ue is kept in the code se&ment re&ister. E%er$ app#ication wi## define and use se&ments different#$. The current#$ addressab#e se&ment o%erride pro%ide1 a &enerous workspace' !7I b$tes for code1 !7I b$tes stack and 1:8I b$tes of data stora&e. ,ol)e% Pro5le#s 1. ,f a ph$sica# branch address is A/:. ? when (3S) H A: the (3S) are chan&ed to C8 ?. 3S' A: Offset' >>>> =h$sica# add. A/: . ? ?ence Offset H =h$sica# add 8 (Se&ment address disp#aced b$ 78bits) Offset H A/:. 8 A: H 8:. ? ? the =h$sica# address wi## be ,f the 3S is chan&ed to C8 :. ?1 what wi## it be if

C8 L 8:. H 8 :. ;i%en that the E/ of a datum is :.AB ? and the 0S H 7B + ?1 what is the

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ph$sica# address of the datumM E/' 0S' 7B + ? :.AB ? =h$sica# add. 7+7 B

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8086 6e#or& A%%ressing The 8 8! memor$ address space can be %iewed as a se6uence of one mi##ion b$tes in which an$ b$te ma$ contain an 88bit data e#ement and an$ two consecuti%e b$tes ma$ contain a 1!8bit data e#ement. There is no constraint on b$te or word address boundaries. The address space is ph$sica##$ connected to a 1!8bit data bus b$ di%idin& the address space into two 88bit banks of up to A1:I b$tes each. One bank is connected to the #ower ha#f of the 1!8bit data bus (0 N 0C) and contains e%en address b$tes. i.e., when / bit is #ow1 the bank is se#ected. The other bank is connected to the upper ha#f of the data bus (08 8 01A) and contains odd address b$tes. i.e., when / is hi&h and +?E (+us ?i&h Enab#e) is #ow1 the odd bank is se#ected. / specific b$te within each bank is se#ected b$ address #ines /18/1B.

H ig ( e r A $ $ re s s Ban) (* + , - x 8 ) .DD A + 2A + 3 A $ $ re s s B u s D a ta B u s ( D ' 2 D + * ) D 8 2D + *

BHE

Lo/ er A $ $ re s s Ban) (* + , - x 8 ) E0E1 D ' 2D 4

A'

-i&. A
0ata can be accessed from the memor$ in four different wa$s. The$ are' 8 8 bit data from 2ower (E%en) address +ank. 8 8 bit data from ?i&her (Odd) address +ank. 1! 8 bit data startin& from E%en /ddress. 1! 8 bit data startin& from Odd /ddress.
. $$ B an) E en B an)

8-5it %ata *ro# E)en a%%ress Ban7

x 6 + x 6 8 x 6 *

x x 6 , x 6 7

B H E 5 + A + 2A + 3 D 8 2D + * D ' 2D 4

A ' 5 '

D ' 2D + *

-i&. ! 88bit 0ata /ccess from E%en /ddress

To access memor$ b$tes from E%en address1 information is transferred o%er the #ower ha#f of the data bus (0 8 0C). The / is output 2OW and +?E is output ?,;? enab#in& on#$ the e%en address bank. ,t is i##ustrated in fi&. !.

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Example: 3onsider #oadin& a b$te of data into 3? re&ister (hi&her order 88bits of 3> re&ister) from the memor$ #ocation with an e%en address. The data wi## be accessed from the e%en bank %ia the (0 8 0C) 0/T/ +US. /#thou&h this data is transferred into the 8 8! o%er the #ower 88bit #ines1 the 8 8! automatica##$ redirects the data to the hi&her 88bits of its interna# 1!8 bit data path and hence to the 3?8re&ister. This capabi#it$ a##ows b$tes input 8 output transfer %ia the /2 re&ister to access ,"O de%ice connected to either the upper ha#f of the data bus or the #ower ha#f of the 1!8bit data bus. 8-5it ata *ro# (%% A%%ress Ban7 To access memor$ b$te from an odd address information1 is transferred o%er the hi&her ha#f of the data bus (08 8 01A). The +?E output #ow enab#es the upper memor$ bank. / is output hi&h to disab#e the #ower memor$ bank. ,t is i##ustrated in fi&. C
. $$ B a n ) E e n B a n )

x 6 + x 6 8

x x 6 ,

B H E 5 ' A + 2A + 3 8 D ' 2D + * 0 2 0 8

A ' 5 +

-i&. C
06-5it ata Access starting *ro# E)en - A%%ress
. $$ B an) E en Ban)

x 6 + x 6 8

x x 6 ,

A + 2A + 3

D 8 2D + *

B H E 5' D ' 2D 4

A' 5 '

D ' 2D + *

-i&. 8
1!8bit data from an e%en address is accessed in a sin&#e bus c$c#e. /ddress #ines /1 8 /1B se#ect the appropriate b$te within each bank. / #ow and +?E #ow enab#es both banks simu#taneous#$. This is i##ustrated in fi&. 8. 06-5it ata Access starting *ro# (%% A%%ress / 1!8bits word #ocated at an odd address (two consecuti%e b$tes with the #east si&nificant b$te at an odd b$te address) is accessed usin& two bus c$c#es. 0urin& the first bus c$c#e the #ower b$te (with the odd address A as shown in fi&. B (a)) is accessed.

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. $$ B an) E en Ban) '''7 '''9 '''8 '''* '''4 '''3 . $$ B an) E en Ban) '''7 '''9 '''8

'''* '''4 '''3

A + 2A + 3 A + 2A 3 D 8 2D + * D ' 2D 4

A + 2A + 3 A + 2A 3 D 8 2D + * D ' 2D 4

( a ) F ir s t A c c e s s f r o m . $ $ A $ $ r e s s

(: ) 1 e x t A c c e s s fro m E e n A $ $ re s s

-i&.

B
0urin& the second bus c$c#e1 the upper b$te (with the e%en address !? as in fi&. B (b)) is accessed. 0urin& the first bus c$c#e1 /1 8 /1B address bus specifies the address and / as 1 and +?E is #ow. Therefore the e%en memor$ bank is disab#ed and odd memor$ bank is enab#ed. 0urin& the second bus c$c#e1 the address is incremented. Therefore / is @ero and +?E is made hi&h. The e%en memor$ bank is enab#ed and the odd memor$ bank is disab#ed. 8086 Basic ,&ste# Conce.ts 8 8! can be used either in a minimum mode s$stem or a ma*imum mode s$stem. The fi&. 1 and fi&. 11 shows minimum and ma*imum modes with &roups of ,3s to &enerate address bus1 data bus and contro# bus si&na#s. Usin& these buses1 the 3=U can be connected to <O41 </41 =O<TS and other de%ices to form a comp#ete s$stem. BA,/C 8086 6ini#u# #o%e ,&ste# 8:8: ,"O ports are used to #atch the addresses from the 8 8! 4icroprocessor 0ata"/ddress bus. +$ usin& three 8:8:1 / 8/1A1 +?E 1 /1!8/1B #ines are #atched durin& T1 state. OE (Output Enab#e) input of the 8:88 ,"O ports are &rounded9 the bus wi## therefore1 ne%er be f#oated. /2E si&na# from 8:8! is used to strobe the addresses into the 8:8: ,"O #atches.

Since the 0ata +us is bi8directiona#1 8:8! bi8directiona# bus transcei%ers are used1 in order to create a separate 0ata +us from the 8 8! /ddress"data +us. The 0T" < and 0EN outputs from 8 8! are used for 8:8! OTO si&na# and OE inputs respecti%e#$.
6axi#u# 6o%e Con*iguration When 4N" 4> pin is strapped to ;N01 the 8 8! treats pin :7 throu&h .1 to be in ma*imum mode. /n 8:88 bus contro##er interprets status information coded into S 1 S1 and S: to &enerate bus timin& and contro# si&na#s compatib#e. 0EN1 0T" < and /2E contro# outputs1 are now &enerated b$ the 8:88 bus contro##er. The 0EN from 8:88 is in%erted and &i%en to 8:8! transcei%er to enab#e the output. The output enab#e of 8:8: #atch is &rounded. /s in minimum mode the address8data #ines are #atched throu&h 8:8: #atch. The /2E si&na# from the 8:88 bus contro##er #atches the address durin& the T1 state of the microprocessor. The 0EN si&na# is used to enab#e the transcei%er either to transmit or recei%e data from ,"O de%ices and memor$. The 0T" R si&na# is used to transmit or recei%e the data as the need ma$ be.

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# C L -

6 * 0 < E S
C lo c ) g e n e ra to r
A E 1 , A E 1 + F ;C

C L < E A D > < E S E ?

@ ;I. I1 ? A < D = < @ 1 ;@ A 6 * 0

C o n tr o l B u s

= a it 2 S t a t e % e n e ra to r

A L E

S ? B . E

A ' 2 A + 3 A $ $ re s s B u s

8'89 C #U

A D ' 2A D + * A + 9 2A + 3 B H E

8 , 8 , L a tc (

B H E

D ' 2 D + * 8 , 8 9 D ? ;< D E 1 ? . E + 9

-i&. 1
6*0
CL-

8 8! 4inimum 4ode S$stem

% n$ S' S+ S, D E1 D ? ;< C L-

8,88 B u s C o n tr o lle r

<ES

C lo c ) g e n e r a to r

<EAD > <ESE?

@ 1 ;@ A S' S+ S,

@ < D C @ = ?C A@ = C I. < C I. = C A I. = C I1 ? A

= a it 2 S t a t e % e n e ra to r

ALE

8'89 C #U

S?B . E

A' 2 A+3 A $ $ re s s B u s BHE

A D ' 2A D + * A + 9 2A + 3

8,8, L a tc (

? . E
8,89 ? ra n s c e i e r

D A?A

-i&. 11 8 8! 4a*imum 4ode 3onfi&uration

2 Bus Rea% 6achine C&cle -i&8 1: shows the timin& dia&ram of 8 8! read machine c$c#e with W/,T state. The c#ock (32I) si&na# is obtained from the c#ock8&enerator 8:87. Each c$c#e of the c#ock is referred to as a state. 4inimum number of states to access a data is four. The$ are T11 T:1 T.1 and T7 states. 0urin& T1 state of a read machine c$c#e an 8 8! first asserts the 4" ,O si&na#. ,t wi## assert this si&na# hi&h if it is &oin& to read from memor$ durin& memor$ read c$c#e and it wi## assert 4" ,O #ow if it is &oin& to do a read from an ,nput port durin& its read c$c#e. The timin& dia&ram in fi&. 1: shows two #ines for the 4" ,O si&na#1 because the si&na# ma$ be &oin& 2OW or &oin& ?,;? for a read c$c#e. The point where the two #ines cross indicate the time at which the si&na# becomes %a#id for this machine c$c#e. /fter assertin& 4" ,O 1 the 8 8! sends out a hi&h on the address #atch enab#e si&na#1 /2E. The microprocessor sends out on /0 8/01A1 /1! throu&h /1B and +?E #ines1 the address of the memor$ #ocation that it wants to read. Since the #atches are enab#ed b$ /2E bein&

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hi&h1 this address information passes throu&h the #atches to their outputs. The 8 8! then makes the /2E output #ow. This disab#es the #atches (8:8:) and ho#ds the address information #atched on the #atch outputs. The address information #atched on the #atch outputs can now be used to se#ect the desired memor$ or port #ocation. ,n the timin& dia&ram1 the first point at which the two (/0 N /01A) cross represents the time at which the 8 8! has put a %a#id address on these #ines. Two #ines 0O NOT indicate that a## 1! #ines are &oin& hi&h or &oin& #ow at this point. The crossed #ines indicate the time at which a %a#id address is on the bus.
?+ C L?, ?8 ? / a it ?7

A D ' 2A D + * BH E

ALE

S , 2S '

@ ;I. < D < EA D > D ? ;< D E1 = <

-i&. 1: <ead Timin& 0ia&ram

Since the address information is now he#d on the #atch1 the 8 8! does not need to send it out an$ more. /s shown in fi&. 1: the 8 8! f#oats the /0 8 /01A #ines so that the$ can be used to input data from memor$ or from a port. /t about the same time the 8 8! a#so remo%e the +?E and /1!8/1B information from the upper #ines and sends out some status information on these #ines. The 8 8! is now read$ to read data from the addressed memor$ #ocations or port. 0urin& T:8state the 8 8! asserts its <0 si&na# #ow. This si&na# is used to enab#e the addressed memor$ de%ice or port de%ice. /t the end of T. state the microprocessor makes the <0 si&na# hi&h and reads the data a%ai#ab#e on the data bus1 pro%ided the <E/0P input si&na# is hi&h. ,t is the dut$ of the e*terna# circuit to see that %a#id data is made a%ai#ab#e on the data bus. ,f the <E/0P input pin is not hi&h at the samp#ed time in a machine c$c#e1 the 8 8! wi## insert one or more W/,T states between T. and T7 states in that machine c$c#e. /n e*terna# hardware de%ice is set up to pu#se <E/0P #ow before the risin& ed&e of the c#ock in T: state. /fter the 8 8! finishes T. of the machine c$c#e1 it enters a W/,T state. ,f the <E/0P input is sti## #ow at the end of a W/,T state1 then the 8 8! wi## insert another W/,T state. The 8 8! wi## continue insertin& W/,T states unti# the <E/0P input is samp#ed hi&h a&ain. ,f the <E/0P input is samp#ed hi&h a&ain durin& T. or durin& the W/,T state1 the microprocessor comes out of the W/,T state and wi## initiate T7 of the machine c$c#e. The 0EN si&na# is used to enab#e bi8directiona# buffers on the data bus. The data enab#e si&na#1 0EN1 from the 8 8! wi## enab#e the data buffer when it is asserted 2OW. The data transmit " recei%e si&na# 0T" < from the 8 8! is used to specif$ the direction in which the

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www.bookspar.com | Website for students | VTU NOTES 17

buffers are enab#ed. When 0T" < is asserted hi&h1 the buffers wi##1 if enab#ed b$ 0EN1 transmit data from the 8 8! to 4emor$ or ,"O ports. When 0T" < is asserted #ow1 the buffers1 if enab#ed b$ 0EN1 wi## a##ow data to be recei%ed from 4emor$ or ,"O ports of the 8 8!. 0T" R is asserted durin& T1 of the machine c$c#e. The 0EN is asserted after the 8 8! finishes usin& the data bus to send the #ower 1! address bits. BU, 9rite 6achine C&cle The 8 8! write operation is %er$ simi#ar to the read c$c#e. 0urin& T1 of a write machine c$c#e the 8 8! asserts 4" ,O #ow if the write is &oin& to a port and it asserts 4" ,O hi&h if the write is &oin& to memor$. /t about the same time the 8 8! raises /2E hi&h to enab#e the address #atches. The 8 8! then assert +?E and on the #ines /0 8 /01B1 it output the address that it wi## be writin& to. When writin& to a port1 #ine /1! 8 /1B wi## a#wa$s be #ow1 because the 8 8! on#$ sends out 1!8bits port addresses. The 8 8! brin&s /2E #ow a&ain to #atch the address on the outputs of the #atches. ,n addition to ho#din& the address1 the #atches a#so function as buffers for the address #ines. /fter the address information is #atched1 the 8 8! remo%e the address information from /0 8 /01A and outputs the desired data on these #ines.

-i& 1. Write Timin& 0ia&ram

,f the <E/0P input is samp#ed 2OW b$ the 8 8! before or durin& T: of the machine c$c#e1 the 8 8! wi## insert a W/,T state after T.. ,f the <E/0P input is samp#ed hi&h before the end of the W/,T state1 the 8 8! wi## &o on with state T7 as soon as it comp#etes the W/,T state. The 8 8! wi## continue to insect wait states for as #on& as the <E/0P is samp#ed #ow 5ust before the end of each W/,T state. Co#.arison o* 8086 +ith the 8088 6icro.rocessor The 8 88 3=U is an 88bit processor desi&ned around the 8 8! interna# structure. 4ost interna# functions of the 8 88 are identica# to the e6ui%a#ent 8 8! functions. The 8 88 hand#es the e*terna# bus the same wa$ the 8 8! does1 one difference bein& hat the 8 88 hand#es on#$ 88bits at a time. 1!8bit operands are fetched or written in two

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www.bookspar.com | Website for students | VTU NOTES 1A

6 * 0 % n $ (, ) 1 @ I I1 ? < C l) A D ' 2A D 4 (8 ) A 8 2A + * (8 ) A + 9 ;S 8 (7 ) A + 3 ;S 9 ?e s t < e a $ y < e se t S S o (H ig ( ) @ 1 ;@ A < D H . L D (< % ;% ? ' ) H L D A (< B ;% ? + )

" 0 " "

= < (L . C - ) I. ;@ (S , )

D ? ;< (S + ) D E 1 (S ' ) A L E (B S ' ) I1 ? A (B S + )

-i& . 17 =in 3onfi&uration of 8 88 4icroprocessor

consecuti%e bus c$c#es. To an assemb#$ #an&ua&e pro&rammer both processors wi## appear identica# with the e*ception of e*ecution times. The interna# re&ister structure is identica# and a## instructions produce the same end resu#t. The pin confi&uration of 8 88 is i##ustrated in fi&. 17. The ma5or differences between 8 88 and 8 8! are out#ined be#ow' The 6ueue #en&th is 7 b$tes in the 8 881 where as the 8 8! 6ueue comprises of ! b$tes. The 8 88 +,U wi## fetch a new instruction to #oad into the 6ueue as soon as it finds a b$te ho#e (space a%ai#ab#e) in the 6ueue. The 8 8! waits unti# a : b$te space is a%ai#ab#e. The interna# e*ecution time of the instruction set is affected b$ the 88bit interface. /## 1!8bit fetches and writes from " to memor$ take an additiona# four c#ock c$c#es. The 3=U is a#so #imited b$ the speed of instruction fetch. When the more sophisticated instructions of the 8 88 are bein& used1 the 6ueue has time to fi## and the e*ecution proceeds as fast as the e*ecution unit wi## a##ow. The hardware interface of the 8 88 has some ma5or differences as compared to the 8 8!. The pin assi&nments are near#$ identica#1 howe%er1 with the fo##owin& functiona# chan&es. /88/1A' These pins are on#$ address outputs on the 8 88. These address #ines are #atched interna##$ and remain %a#id throu&hout a bus c$c#e in a manner simi#ar to the 8 8A upper address #ines. SS pro%ides the S status information in the minimum mode. This output occurs on pin .7 in minimum mode on#$. 0T" < 1 ,O" 4 and SS pro%ide the comp#ete bus status in minimum mode. This is shown in tab#e A

,O"4 0T"<
1 1 1 1 1 1

SSO
1 1 1

3?/</3TE<,ST,3S
3ode /ccess <ead 4emor$ Write 4emor$ =assi%e ,nterrupt /cknow#ed&e <ead ,"O port Write ,"O port ?a#t

1 1

Tab#e A

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+?E has no meanin& on the 8 88 and has been e#iminated. ,O" 4 has been in%erted. i.e., (,n 8 8!1 this pin as ,O "4) /2E is de#a$ed b$ one c#ock c$c#e in the minimum mode when enterin& ?/2T to a##ow the status to be #atched with /2E.

-i& 1A i##ustrates the 8 88 microprocessor s$stem confi&uration. The /ddress80ata #ines /0 8/0C are connected to the C72S.C. #atch. The address from the mu#tip#e*ed bus is #atched into the C72S.C. when an /2E (/ddress #atch enab#e) is acti%e durin& T1 state of the microprocessor. The address / 8/C is a%ai#ab#e on the output of C72S.C. and can be used for memor$ (a#on& with /1!8/1B)1 and ,"O de%ices. The address #ines /88/1A are not mu#tip#e*ed with data #ines or status #ines1 hence there is no need to #atch these address #ines. The data bus is connected to the C72S:7A transcei%er. The C72S:7A is contro##ed b$ 0T" < and 0EN to transmit and recei%e and 0ata respecti%e#$. Since C72S.C. and C72S:7A are a#so buffered chips1 it is not re6uired to add buffers to these chips. The address #ines /88/1A need to be buffered and hence the C72S :77 buffer is used for these #ines. The output of C72S:77 is a#wa$s enab#ed.

A + 3 ;S 9 2 A + 9 ;S 8

. E 47LS 848

A +3 2 A +9

A LE
A + * 2 A 8

% 47LS ,77 . E % . E

8'88
A D ' 2 A D 4

A ' 2 A 4

47LS 848

D ? ;<

D E 1 D ' 2 D 4 47LS ,77 % D ;<

-i&. 1A

1. 3ompare 8 8! and 8 88 microprocessors. ,n what wa$s are the$ simi#arM ,n what wa$s do the$ differM :. What is the purpose of the /2E si&na# in an 8 8! s$stemM .. What is the ma5or difference between an 8 8! operatin& in minimum mode and an 8 8! operatin& in ma*imum modeM 7. 0escribe the response of an 8 8! when its <ESET input is asserted hi&h. A. Wh$ are buffers often needed on the address1 data and contro# buses in a microprocessor s$stemM !. What are the function of the 8 8! 0T" < and 0EN si&na#sM C. E*p#ain the difference between a memor$ read c$c#e and an ,"O read c$c#e. 8. What are the main functions pro%ided b$ the 8:88 bus contro##er when used with the 8 8!"8 88 ma*imum mode operationM www.bookspar.com | Website for students | VTU NOTES

www.bookspar.com | Website for students | VTU NOTES 1C B. E*p#ain the operation of the 2O3I pin. 1 . What conditions do the QS1 and QS pins indicate about the 8 8!"8 88M 11. What three house keepin& chores are pro%ided b$ the 8:87 c#ock &eneratorsM 1:. E*p#ain the operation of the TEST pin and the W/,T instruction. 1.. What is the function of QS and QS1 si&na#sM 17. With a timin& dia&ram e*p#ain ,"O read machine c$c#e. 1A. With a timin& dia&ram e*p#ain , "O Output8Write machine c$c#e with two wait states. 1!. 4ention an affi#iation of the OS3 si&na# in 8:87M 1C. What is the app#ication of the =32I si&na#M 18. +rief#$ describe the purpose of each of the T8states T11 T:1 T. and T7. 1B. What is the purpose of the status bits S. and S7M

(5:ecti)e -&.e 4uestions

1. State true or fa#se (a) +oth the address and data bus are unidirectiona#. (b) +oth the 8 8! and 8 88 microprocessors address !7 I b$tes of memor$. (c) No difference e*its between the memor$ maps of 8 8! and 8 88. (d) The strin& source (S,) is #ocated in the 0ata Se&ment (0S) and the strin& destination is #ocated in the E*tra se&ment (ES) for strin& instructions. :. The ,NT< input is 88 sensiti%e. ... The 8:8! microprocessor has a 18bit data bus. ,ts memor$ is or&ani@ed into 88 banks1 each88bit wide. 7. / microprocessor with a :78bit address bus cou#d access 888 4+ of memor$. A. / bus c$c#e is e6ua# to c#ockin& 888 periods. !. ,f the read$ pin is &rounded1 it wi## introduce 888state into the bus c$c#e. C. The =32I output of the 8:87/ is 888 4?@ if the cr$sta# fre6uenc$ is 17 4?@. 8. The <ES input to the 8:87/ is p#aced at a #o&ic 888 #e%e# in order to reset the 8 8!"8 88. B. The 8 8! and 8 88 processor can be operated in either the minimum or ma*imum mode. The ma*imum mode is so named because the ma*imum mode (a) 2et $ou e*ecute the ma*imum number of instructions. (b) 2et $ou address the ma*imum number of memor$ #ocations (,4+) (c) <e6uires more support hardware than the minimum mode. (d) /## of the abo%e. 1 . The 8 8!"8 88 use a mu#tip#e*ed address and data bus because (a) 7 pins is a &ood si@e for the ,3. (b) 4u#tip#e*in& is supported b$ 8 8A 4icroprocessor. (c) 4u#tip#e*in& reduces the number of #ines between the microprocessor and the au*i#iar$ ,cs. (d) /## of the abo%e. The 0EN si&na# is acti%e 8888888 output from 8:88 bus contro##er. 1:. /n 8 8!"8 88 microprocessor re6uires 88888888 and 8888888 chips is ma*imum mode s$stems confi&uration.

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www.bookspar.com | Website for students | VTU NOTES 18 1..The 8:88 bus contro##er must be used in the 888888 mode to pro%ide 888888 si&na#s to the memor$ and ,"O. 17. 8 88 microprocessor does not re6uired #atch for a /8 N /1A #ines because 888888888. 1A. SSO of 8 88 microprocessor indicates 8888888.

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www.bookspar.com | Website for students | VTU NOTES 1B

Pin Con*iguration %1D AD+7 AD+8 AD+, A D ++ AD+' AD3 AD8 AD4 AD9 AD* AD7 AD8 AD, AD+ AD' 1@I I1 ? < CL%1D
+ , 8 7 * 9 4 8 3 +' ++ +, +8 +7 +* +9 +4 +8 +3 ,' 7' 83 88 84 89 8* 87 88 8, 8+ 8' ,3 ,8 ,4 ,9 ,* ,7 ,8 ,, ,+

"0"#

0cc AD+* A + 9 ;S 8 A + 4 ;S 7 A + 8 ;S * A + 3 ;S 9 B H E ;S 4 @ 1 ;@ A <D < % ;% ? ' ( H . L D ) < B ;% ? + ( H L D A ) L . C - (= < ) S , (@ ;I' ) S + (D ? ;< ) S ' (D E 1 ) B S ' (A L E ) B S + ( I1 ? A ) ?ES? <EAD> <ESE?

-i&. .1 =in 3onfi&uration

The fo##owin& pin function descriptions are for the microprocessor 8 8! in either minimum or ma*imum mode. The 8 8! pins si&na#s are TT2 compatib#e. A 0 - A 02 (//(); A%%ress ata Bus These #ines constitute the time mu#tip#e*ed memor$",O address durin& the first c#ock c$c#e (T1) and data durin& T:1 T. and T7 c#ock c$c#es. / is ana#o&ous to +?E for the #ower b$te of the data bus1 pins 0 80C. / bit is 2ow durin& T1 state when a b$te is to be transferred on the #ower portion of the bus in memor$ or ,"O operations. 88bit oriented de%ices tied to the #ower ha#f wou#d norma##$ use / to condition chip se#ect functions. These #ines are acti%e hi&h and f#oat to tri8state durin& interrupt acknow#ed&e and #oca# bus O?o#d acknow#ed&eO. -i&. : shows the timin& of /0 N /01A #ines to access data and address.
?7 ?+ ?, ?8 ?7

A D ' 2 A D +*

A $ $ re s s

D a ta

-i&. .:
A0</,6= A08/,2= A08/,>= A06/,? (0); A%%ress/,tatus 0urin& T1 state these #ines are the four most si&nificant address #ines for memor$ operations. 0urin& ,"O operations these #ines are #ow. 0urin& memor$ and ,"O operations1 status information is a%ai#ab#e on these #ines durin& T:1 T.1 and T7 states.

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www.bookspar.com | Website for students | VTU NOTES :

,2; The status of the interrupt enab#e f#a& bit is updated at the be&innin& of each c$c#e. The status of the f#a& is indicated throu&h this bus. ,6; When 2ow1 it indicates that 8 8! is in contro# of the bus. 0urin& a O?o#d acknow#ed&eO c#ock period1 the 8 8! tri8states the S! pin and thus a##ows another bus master to take contro# of the status bus. ,? @ ,>; 2ines are decoded as fo##ows'

/1C"S7

/1!"S.
1

-unction
E*tra se&ment access Stack se&ment access 3ode se&ment access 0ata se&ment access

1 1

Tab#e 1
/fter the first c#ock c$c#e of an instruction e*ecution1 the /1C"S7 and /1!"S. pins specif$ which se&ment re&ister &enerates the se&ment portion of the 8 8! address. Thus b$ decodin& these #ines and usin& the decoder outputs as chip se#ects for memor$ chips1 up to 7 4e&ab$tes (one 4e&a per se&ment) of memor$ can be accesses. This feature a#so pro%ides a de&ree of protection b$ pre%entin& write operations to one se&ment from erroneous#$ o%er#appin& into another se&ment and destro$in& information in that se&ment.
+?E /,8 ((); Bus "igh Ena5le/,tatus

0urin& T1 state the +?E shou#d be used to enab#e data onto the most si&nificant ha#f of the data bus1 pins 01A 8 08. Ei&ht8bit oriented de%ices tied to the upper ha#f of the bus wou#d norma##$ use +?E to contro# chip se#ect functions. +?E is 2ow durin& T1 state of read1 write and interrupt acknow#ed&e c$c#es when a b$te is to be transferred on the hi&h portion of the bus. The SC status information is a%ai#ab#e durin& T:1 T. and T7 states. The si&na# is acti%e 2ow and f#oats to .8state durin& Oho#dO state. This pin is 2ow durin& T1 state for the first interrupt acknow#ed&e c$c#e. <0 ((); REA The <ead strobe indicates that the processor is performin& a memor$ or ,"O read c$c#e. This si&na# is acti%e #ow durin& T: and T. states and the Tw states of an$ read c$c#e. This si&na# f#oats to tri8state in Oho#d acknow#ed&e c$c#eO.
TEST (/) TEST pin is e*amined b$ the OW/,TO instruction. ,f the TEST pin is 2ow1 e*ecution

continues. Otherwise the processor waits in an Oid#eO state. This input is s$nchroni@ed interna##$ durin& each c#ock c$c#e on the #eadin& ed&e of 32I. /A-R (/); /nterru.t ReBuest ,t is a #e%e# tri&&ered input which is samp#ed durin& the #ast c#ock c$c#e of each instruction to determine if the processor shou#d enter into an interrupt acknow#ed&e operation. / subroutine is %ectored to %ia an interrupt %ector #ook up tab#e #ocated in s$stem memor$. ,t can be interna##$ masked b$ software resettin& the interrupt enab#e bit

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,NT< is interna##$ s$nchroni@ed. This si&na# is acti%e ?,;?.

A6/ (/); Aon-6us7a5le /nterru.t /n ed&e tri&&ered input1 causes a t$pe8: interrupt. / subroutine is %ectored to %ia the interrupt %ector #ook up tab#e #ocated in s$stem memor$. N4, is not maskab#e interna##$ b$ software. / transition from a 2OW to ?,;? on this pin initiates the interrupt at the end of the current instruction. This input is interna##$ s$nchroni@ed. Reset (/) <eset causes the processor to immediate#$ terminate its present acti%it$. To be reco&nised1 the si&na# must be acti%e hi&h for at #east four c#ock c$c#es1 e*cept after power8on which re6uires a A 4icro Sec. pu#se. ,t causes the 8 8! to initia#i@e re&isters 0S1 SS1 ES1 ,= and f#a&s to a## @eros. ,t a#so initia#i@es 3S to ---- ?. Upon remo%a# of the <ESET si&na# from the <ESET pin1 the 8 8! wi## fetch its ne*t instruction from the : bit ph$sica# address ---- ?. The reset si&na# to 8 8! can be &enerated b$ the 8:87. (3#ock &eneration chip). To &uarantee reset from power8up1 the reset input must remain be#ow 1.A %o#ts for A 4icro sec. after Vcc has reached the minimum supp#$ %o#ta&e of 7.AV. The <ES input of the 8:87 can be dri%en b$ a simp#e <3 circuit as shown in fi&...
A+ A, F ;C 6*0 < <ES 1 o rm a l < eset - ey C <ESE? CLCL-

8,87

8'89 !
<ESE?

S>S?E@ <ESE?

-i&. ..
The %a#ue of < and 3 can be se#ected as fo##ows' Vc (t) H V (1 8 e 8t "<3) t H A 4icro sec. V H 7.A %o#ts1 Vc H 1. AV and <3 H 188 4icro sec. 3 H .1 4icro -9 < H 1.88 I ohms.

3=U component 3ontents -#a&s 3#eared ,nstruction =ointer ? 3S re&ister ----? 0S re&ister ? SS re&ister ? ES re&ister ? Queue Empt$ Tab#e N .: S$stem <e&isters after <eset

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8 8!"88 <ESET #ine pro%ide an order#$ wa$ to start an e*ecutin& s$stem. When the processor detects the positi%e8&oin& ed&e of a pu#se on <ESET1 it terminates a## acti%ities unti# the si&na# &oes #ow1 at which time it initia#i@es the s$stem as shown in

tab#e .:.
Rea%& (/) <ead$ is the acknow#ed&ement from the addressed memor$ or ,"O de%ice that it wi## comp#ete the data transfer. The <E/0P si&na# from memor$ or ,"O is s$nchroni@ed b$ the 8:87 c#ock &enerator to form <E/0P. This si&na# is acti%e ?,;?. The 8 8! <E/0P input is not s$nchroni@ed. 3orrect operation is not &uaranteed if the setup and ho#d times are not met. C!C (/); Cloc7 3#ock pro%ides the basic timin& for the processor and bus contro##er. ,t is as$mmetric with ..R dut$ c$c#e to pro%ide optimi@ed interna# timin&. 4inimum fre6uenc$ of : 4?@ is re6uired1 since the desi&n of 8 8! processors incorporates d$namic ce##s. The ma*imum c#ock fre6uencies of the 8 8!871 8 8! and 8 8!8: are
A + A , F ;C C L< E A D >

8,87

C sync < D > + A E 1 + A E 1 , 0 cc < < D > ,

8 ' 8 9 !

< E S E ?

# C LS > S ? E @ < E S E ? . S C

-i&..7
74?@1 A4?@ and 84?@ respecti%e#$. Since the 8 8! does not ha%e on8chip c#ock &eneration circuitr$1 and 8:87 c#ock &enerator chip must be connected to the 8 8! c#ock pin. The cr$sta# connected to 8:87 must ha%e a fre6uenc$ . times the 8 8! interna# fre6uenc$. The 8:87 c#ock &eneration chip is used to &enerate <E/0P1 <ESET and 32I. ,t is as shown in fi&..7 6A/ 4> (/); 6axi#u# / 6ini#u# This pin indicates what mode the processor is to operate in. ,n minimum mode1 the 8 8! itse#f &enerates a## bus contro# si&na#s. ,n ma*imum mode the three status si&na#s are to be decoded to &enerate a## the bus contro# si&na#s. 6ini#u# 6o%e Pins The fo##owin& 8 pins function descriptions are for the 8 8! in minimum mode9 4N" 4> H 1. The correspondin& 8 pins function descriptions for ma*imum mode is e*p#ained #ater. 6/ ,O ((); ,tatus line This pin is used to distin&uish a memor$ access or an ,"O accesses. When this pin is 2ow1 it accesses ,"O and when hi&h it access memor$. 4 " ,O becomes %a#id in the T7 state precedin& a bus c$c#e and remains %a#id unti# the fina# T7 of the c$c#e. 4" ,O

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f#oats to . 8 state O-- durin& #oca# bus Oho#d acknow#ed&eO.
W< ((); 9rite

,ndicates that the processor is performin& a write memor$ or write ,O c$c#e1 dependin& on the state of the 4 " ,O si&na#. W< is acti%e for T:1 T. and Tw of an$ write c$c#e. ,t is acti%e 2OW1 and f#oats to .8state O-- durin& #oca# bus Oho#d acknow#ed&e O.
,NT/ ((); /nterru.t Ac7no+le%ge

,t is used as a read strobe for interrupt acknow#ed&e c$c#es. durin& T:1 T.1 and T7 of each interrupt acknow#ed&e c$c#e.

,t is acti%e 2OW

A!E ((); A%%ress !atch Ena5le /2E is pro%ided b$ the processor to #atch the address into the 8:8:"8:8. address #atch. ,t is an acti%e hi&h pu#se durin& T1 of an$ bus c$c#e. /2E si&na# is ne%er f#oated. -/ R ((); A-A -rans#it/Recei)e ,n minimum mode1 8:8!"8:8C transcei%er is used for the data bus. 0T" R is used to contro# the direction of data f#ow throu&h the transcei%er. This si&na# f#oats to tri8state off durin& #oca# bus Oho#d acknow#ed&eO. 0EN ((); ata Ena5le ,t is pro%ided as an output enab#e for the 8:8!"8:8C in a minimum s$stem which uses the transcei%er. 0EN is acti%e 2OW durin& each memor$ and ,O access. ,t wi## be #ow be&innin& with T: unti# the midd#e of T71 whi#e for a write c$c#e1 it is acti%e from the be&innin& of T: unti# the midd#e of T7. ,t f#oats to tri8state off durin& #oca# bus Oho#d acknow#ed&eO. "(! @ "! A (//(); "ol% an% "ol% Ac7no+le%ge ?o#d indicates that another master is re6uestin& a #oca# bus O?O20O. To be acknow#ed&ed1 ?O20 must be acti%e ?,;?. The processor recei%in& the O?O20 O re6uest wi## issue ?20/ (?,;?) as an acknow#ed&ement in the midd#e of the T18c#ock c$c#e. Simu#taneous with the issue of ?20/1 the processor wi## f#oat the #oca# bus and contro# #ines. /fter O?O20O is detected as bein& 2ow1 the processor wi## #ower the ?20/ and when the processor needs to run another c$c#e1 it wi## a&ain dri%e the #oca# bus and contro# #ines. 6axi#u# 6o%e The fo##owin& pins function descriptions are for the 8 8!"8 88 s$stems in ma*imum mode (i.e.. 4N" 4> H ). On#$ the pins which are uni6ue to ma*imum mode are described be#ow.

.
,3= ,0= ,0 ((); ,tatus Pins These pins are acti%e durin& T71 T1 and T: states and is returned to passi%e state (11111 durin& T. or Tw (when read$ is inacti%e). These are used b$ the 8:88 bus contro##er to &enerate a## memor$ and ,"O operation) access contro# si&na#s. /n$ chan&e b$ S:1 S11 S durin& T7 is used to indicate the be&innin& of a bus c$c#e. These status #ines are encoded as shown in tab#e .. S: S1 S 3haracteristics

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,nterrupt acknow#ed&e <ead ,"O port Write ,"O port ?a#t 3ode access <ead memor$ Write memor$ =assi%e State

1 1 1 1 1 1 1 1 1 1 1 1

Tab#e .
4,0= 4,0 ((); 4ueue D ,tatus Queue Status is %a#id durin& the c#ock c$c#e after which the 6ueue operation is performed. QS 1 QS1 pro%ide status to a##ow e*terna# trackin& of the interna# 8 8! instruction 6ueue. The condition of 6ueue status is shown in tab#e 7. Queue status a##ows e*terna# de%ices #ike ,n8circuit Emu#ators or specia# instruction set e*tension co8processors to track the 3=U instruction e*ecution. Since instructions are e*ecuted from the 8 8! interna# 6ueue1 the 6ueue status is presented each 3=U c#ock c$c#e and is not re#ated to the bus c$c#e acti%it$. This mechanism a##ows (1) / processor to detect e*ecution of a ES3/=E instruction which directs the co8 processor to perform a specific task and (:) /n in8circuit Emu#ator to trap e*ecution of a specific memor$ #ocation.

QS1

QS1
1

3haracteristics
No operation -irst b$te of opcode from 6ueue Empt$ the 6ueue Subse6uent b$te from 6ueue

1 1
2O3I (()

Tab#e 7
,t indicates to another s$stem bus master1 not to &ain contro# of the s$stem bus whi#e
2O3I is acti%e 2ow. The 2O3I si&na# is acti%ated b$ the O2O3IO prefi* instruction and

remains acti%e unti# the comp#etion of the instruction. This si&na# is acti%e 2ow and f#oats to tri8state O-- durin& Eho#d acknow#ed&eO. Example: 2O3I >3?; re&.1 4emor$ 9 <e&ister is an$ re&ister and memor$ GT 9 is the address of the semaphore.

/ ;T and <Q / ;T1 (//(); ReBuest/Grant These pins are used b$ other processors in a mu#ti processor or&ani@ation. 2oca# bus masters of other processors force the processor to re#ease the #oca# bus at the end of the processors current bus c$c#e. Each pin is bi8directiona# and has an interna# pu## up resistors. ?ence the$ ma$ be #eft un8connected.
<Q

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