Lecture 030 ECE4430 Review III (1/9/04)

Page 030-1

LECTURE 030 ECE 4430 REVIEW III

(READING: GHLM - Chaps. 3 and 4) Objective The objective of this presentation is: 1.) Identify the prerequisite material as taught in ECE 4430 2.) Insure that the students of ECE 6412 are adequately prepared Outline Models for Integrated-Circuit Active Devices Bipolar, MOS, and BiCMOS IC Technology Single-Transistor and Multiple-Transistor Amplifiers Transistor Current Sources and Active Loads

ECE 6412 - Analog Integrated Circuits and Systems II

P.E. Allen - 2002

Lecture 030 ECE4430 Review III (1/9/04)

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SINGLE-TRANSISTOR AND MULTIPLE-TRANSISTOR AMPLIFIERS Characterization of Amplifiers Amplifiers will be characterized by the following properties: Large-signal voltage transfer characteristics (.DC) Large-signal voltage swing limitations (.DC and .TRAN) Small-signal, frequency independent performance (.TF) Gain (.TF) Input resistance (.TF) Output resistance (.TF) Small-signal, frequency response (.AC) Other properties (.TEMP, .FOUR, etc.) Noise (.NOISE) Power dissipation (.OP) Slew rate (.TRAN) Etc.

ECE 6412 - Analog Integrated Circuits and Systems II

P.E. Allen - 2002

Lecture 030 ECE4430 Review III (1/9/04)

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Types of Single Transistor Amplifiers

VCC RC vOUT vIN vIN Common Emitter VDD RD vOUT vIN vIN Common Source Common Gate Common Drain RD vOUT RS RS Source Degeneration
Fig. 030-01

VCC RC vOUT RE vIN

VCC RC vOUT vIN

VCC vOUT

RE Common Collector VDD vIN vOUT vIN RD vOUT Emitter Degeneration VDD VDD

Common Base

ECE 6412 - Analog Integrated Circuits and Systems II

P.E. Allen - 2002

Lecture 030 ECE4430 Review III (1/9/04)

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Signal Flow in Transistors It is important to recognize that ac signals can only flow into and out of certain transistor terminals. Illustration:
C 180 B 0 E 0 G 0 S
Fig. 030-02

D 180 0

Rules: The collector or drain can never be an input terminal. The base or gate can never be an output terminal. In addition it is important to note polarity reversals on these signal paths. The base-collector or gate-drain path inverts. All other paths are noninverting. (This of course assumes that there are no reactive elements causing phase shifts)

ECE 6412 - Analog Integrated Circuits and Systems II

P.E. Allen - 2002

Lecture 030 ECE4430 Review III (1/9/04)

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Common Emitter Amplifer Large-Signal:

iC VCC RC vOUT vIN VCC RC VIN, IB vCE(sat) Common Emitter 0 0 VCC vCE 0 0 0.5V Saturation Region 1.0V vIN
Fig. 030-03

vOUT VCC Forward Active Region

Small-Signal:
B

Rin i in

iout gmvin ro RC

Rout + C

IC gm = V t

VA and ro = IC

+ vin -

r!

vout E
Fig. 030-04

"# roRC vout -gmroRC iout "oro Rin = r! = gm , Rout = ro + RC , and iin = ro + RC vin = ro + RC (One should also consider the case of a source resistance, RS, in series with the input)
ECE 6412 - Analog Integrated Circuits and Systems II P.E. Allen - 2002

Lecture 030 ECE4430 Review III (1/9/04)

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Common Source Amplifier Large-Signal:

iD VDD RD vOUT vIN VDD RD VIN vDS = VGS-VT vOUT Cutoff Region Saturation VDD Region
vO
U T=

Fig. 030-05

VDD

vDS

vI

Triode Region

N-

0 VT

VDD

VIN

Small-Signal:
Rin i in G + vin gmvin rds iout RD Rout + D

vout S Fig. 030-055

Rin = $,

rdsRD Rout = rds + RD ,

vout -gmrdsRD vin = rds + RD

iout and iin = $

P.E. Allen - 2002

ECE 6412 - Analog Integrated Circuits and Systems II

Lecture 030 ECE4430 Review III (1/9/04)

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Summary of Single BJT Transistor Amplifiers Small-Signal Performance Input Resistance Output Resistance Voltage Gain Current Gain Common Emitter r! (Medium) ro (High) -gmRL "o Common Common Collector Base r! r!+(1+"o)RE (Low) 1+"o (High) r!+RS ro(1+"o) (Very high) 1+"o (Very low) gmRL 1 -% -(1+"o)

ECE 6412 - Analog Integrated Circuits and Systems II

P.E. Allen - 2002

Lecture 030 ECE4430 Review III (1/9/04)

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Summary of Single MOSFET Transistor Amplifiers Small-Signal Performance Input Resistance Output Resistance Voltage Gain Current Gain Common Source Common Gate rds+RD 1+gmrds rdsRD rds+RD gmRD -1 Common Drain $ RS 1+gmRS 0.8 $

$
rdsRD rds + RD -gmrdsRD rds + RD $

ECE 6412 - Analog Integrated Circuits and Systems II

P.E. Allen - 2002

Lecture 030 ECE4430 Review III (1/9/04)

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BJT Cascode Amplifer Circuit and small-signal model:

va vin Q2 RL Q1 vout i B1 in + vin r!1 C1 = E2 gm1v!1 ro1 r!2 - + E1=B2 + va v!2 ro2 iout C2 + RL

VBias

VCC

gm2v!2

vout -

Fig. 030-06

If "1 & "2 and ro can be neglected, then: Rin = r!1 Rout & "2ro2 (not including RL)
) r ! 2 -" o 1 , vout ) v ,) v , ( out+ ( a + ( + & (g R ) (-1) = - g R = = ( g R ) ( + ( + m 2 L m2 L m2 L vin ' va *'vin* '1+"o2 r!1 *

iout iin = %2"1 The advantage of the cascode is that the gain of Q1 is -1 and therefore the Miller capacitor, C, is not translated to the base-emitter as a large capacitor.
ECE 6412 - Analog Integrated Circuits and Systems II P.E. Allen - 2002

Lecture 030 ECE4430 Review III (1/9/04)

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MOS Cascode Amplifier Circuit and smallgm2vgs2= -gm2v1 vout M2 signal model: D1=S2 G1 D2=D3 r ds 2 + + + Small-signal vin vin = v1 M1 VBias RL vout performance vgs1 gm1vgs1 rds1 S1=G2=G3 (assuming a load Fig. 030-07 resistance in the drain of RL): Rin = $ Using nodal analysis, we can write, [gds1 + gds2 + gm2]v1 - gds2vout = -gm1vin and -[gds2 + gm2]v1 + (gds2 + GL)vout = 0 Solving for vout/vin yields, vout -gm1(gds2 + gm2) -gm1 vin = gds1gds2 + gds1GL + gds2GL + GLgm2 . GL = -gm1RL Note that unlike the BJT cascode, the voltage gain, v1/vin is greater than -1. 1 ) rds2+RL , 4 ) v1 rds2+RL RL , 0 ( +3 ( + = g r || & = 1+ (RL < rds2 for the gain to be -1) 0 ( + 3 ( m1/ ds1 '1+gm2rds2*2 vin rds2 rds2+ ' * The small-signal output resistance is, rout = [rds1 + rds2 + gm2rds1rds2]50RL . RL, assuming that RL is small.
ECE 6412 - Analog Integrated Circuits and Systems II P.E. Allen - 2002

Lecture 030 ECE4430 Review III (1/9/04)

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Transconductance Characteristic of the BJT Differential Amplifier Consider the following NPN-BJT differential amplifier iC1 (sometimes called an emitter-coupled pair): Large-Signal Analysis: 1.) Input loop eq.: vI1 vI1-vBE1+vBE2-vI2 = vI1-vI2-vBE1+vBE2 = vID-vBE1+vBE2 = 0 2.) Forward-active region: ) iC 1 , ) iC 2 , ( + + vBE1= Vt ln( IS1 + and vBE2= Vt ln( (I + ' * ' S2 * ) v I1 -v I2, ) vID, iC 1 ( + ( + 3.) If IS1 = IS2 then = exp = exp ( + ( + iC 2 Vt * ' ' Vt *
Q1 + vBE1 Q2

iC2

+ vBE2 -

vI2

IEE

VEE

Fig. 030-08

1 4.) Nodal current equation at the emitters: -(iE1+iE2) = IEE = %F (iC1 + iC2) %FIEE %FIEE 5.) Combining the above equations gives: iC1 = and iC2 = ) -vID, ) vID, ( + + 1 + exp( Vt + 1 + exp( ( V + ' * ' t *

ECE 6412 - Analog Integrated Circuits and Systems II

P.E. Allen - 2002

Lecture 030 ECE4430 Review III (1/9/04)

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Differential and Common-mode Small-Signal BJT Amplifier Performance The small-signal performance of a differential amplifier can be separated into a differential mode and common mode analysis. This separation allows us to take advantage of the following simplifications.
Half-Circuit Concept:
VCC RC VCC RC
ic1 + vbe1 Q1 IEE + vo1 +vod + vo2 ic1 +vod + + vo1 vo2 -

VCC RC
ic2 Q2 + vbe2 -

RC
ic2 Q2 + vbe2 -

vid tial n e r 2 e Diff nalysis eA Mod vi2

+ vbe1

Q1 -

vid 2

VCC RC
ic1

VCC RC
+vod + + vo1 vo2 ic2 Q2 + vbe2 IEE 2

vi1

REE
C Mo omm de A on nal ysis

VEE

VEE

vic

+ vbe1 IEE 2

Q1 -

vic

VEE

2REE VEE

2REE VEE VEE

Fig. 030-09

Note: The half-circuit concept is valid as long as the resistance seen looking into each emitter is approximately the same.
ECE 6412 - Analog Integrated Circuits and Systems II P.E. Allen - 2002

Lecture 030 ECE4430 Review III (1/9/04)

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Transconductance Performance of the Differential Amplifier Consider the following n-channel differential amplifier:
VDD vG1 M1
IBias

iD1

iD2

vID

vGS1

M3 ISS

M2 v G2 + vGS2 VBulk

M4

Where should bulk be connected? Consider a p-well, CMOS technology,

D1 G1 S1 n+ S2 G2 D2 VDD n+

n-substrate

y ; ; y
n+ p+ n+ p-well

Fig. 030-10

n+

Fig. 030-11

1.) Bulks connected to the well: No modulation of VT but large common mode parasitic capacitance. 2.) Bulks connected to ground: Smaller common mode parasitic capacitors, but modulation of VT. If the technology is n-well CMOS, the bulks must be connected to ground.
ECE 6412 - Analog Integrated Circuits and Systems II P.E. Allen - 2002

Lecture 030 ECE4430 Review III (1/9/04)

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Transconductance Performance of the Differential Amplifier - Continued Defining equations (Assume that the MOSFETs are in saturation): ) 2iD1, 1/2 ) 2iD2, 1/2 ( + + vID = vGS1 - vGS2 = ' " * - ( and ISS = iD1 + iD2 ' " * Solution:
2 4 , ) 2 ( ISS ISS "vID " vID+1/2 iD 1 = 2 + 2 ( - 2 + ' ISS 4ISS *

and

2 4 , ) 2 ( ISS ISS "vID " vID+1/2 iD 2 = 2 - 2 ( - 2 + ' ISS 4ISS *

which are valid for vID < (2ISS/")1/2. Illustration of the result:
iD/ISS 1.0 0.8 0.6 0.4 0.2 -2.0 -1.414 0.0 1.414 2.0 vID (ISS/)0.5 Fig. 030-12 iD1 iD2

ECE 6412 - Analog Integrated Circuits and Systems II

P.E. Allen - 2002

Lecture 030 ECE4430 Review III (1/9/04)

Page 030-15

Differential and Common-mode Small-Signal Performance The small-signal performance of a differential amplifier can be separated into a differential mode and common mode analysis. This separation allows us to take advantage of the following simplifications.
Half-Circuit Concept:
VDD RD VDD RD
id1 + vgs1 M1 ISS +vod + + vo1 vo2 id1 +vod + + vo1 vo2 -

VDD RD
id2 M2 + vgs2 -

RD
id2 M2 + vgs2 RSS

vid al i t n e 2 er Diff nalysis eA Mod

+ vgs1

M1 -

vid 2

VDD RD

VDD RD
+vod + + vo1 vo2 id2 M2 + vgs2 ISS 2

vi1

vi2 id1
C Mo omm de A on nal ysis

VSS

VSS

vic

+ vgs1 ISS 2

M1 -

vic

VSS

2RSS VSS

2RSS VSS VSS

Fig. 030-13

Note: The half-circuit concept is valid as long as the resistance seen looking into each source is approximately the same.
ECE 6412 - Analog Integrated Circuits and Systems II P.E. Allen - 2002

Lecture 030 ECE4430 Review III (1/9/04)

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Other Characteristics of the Differential Amplifier Common-mode rejection ratio Input common-mode range Slew rate BJT: ICMR: The maximum and minimum input common mode range is: vic(max) = VCC - 0.5IEERC -vCE1(sat)+VBE1 vic(min) = VEE+vCE3(sat)+VBE1 SR: The differential amplifier has a slew rate limit of IEE/Ceq where Ceq is the capacitance seen to ground from either collector. MOSFET: ICMR: The maximum and minimum input common mode range is: vic(max) = VDD - 0.5ISSRD + VT1 vic(min) = VSS+vDS3(sat)+VGS1 SR: The differential amplifier has a slew rate limit of ISS/Ceq where Ceq is the equivalent capacitance seen from either of the drains to ground.

ECE 6412 - Analog Integrated Circuits and Systems II

P.E. Allen - 2002

Lecture 030 ECE4430 Review III (1/9/04)

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TRANSISTOR CURRENT SOURCES AND ACTIVE LOADS Summary of Current Sinks and Sources Current Sink/Source Simple MOS Current Sink Simple BJT Current Sink Cascode MOS Cascode BJT Minimum VMIN Cascode Current Sink Regulated Cascode Current Sink Minimum VMIN Regulated Cascode Current Sink rOUT 1 rds = 67D VA ro = 7C & gm2rds2rds1 & " F ro & gm2rds2rds1 & rds3gm3rds2gm4(rds4||rds5) & rds3gm3rds2gm4(rds4||rds5) VMIN VDS(sat) = VON VCE(sat) & 0.2V VT + 2VON 2VCE(sat) 2VON

& VT +VON
&VON

ECE 6412 - Analog Integrated Circuits and Systems II

P.E. Allen - 2002

Lecture 030 ECE4430 Review III (1/9/04)

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Summary of MOS Current Mirrors Current Mirror Simple Cascode Wide Output Swing Cascode Self-biased Cascode Wilson Regulated Cascode Accuracy Output Input Resistance Resistance rds gmrds2 gmrds2 gmrds2 gmrds2 gm2rds3 1 gm 2 gm 1 gm 1 R + gm 2 gm 1 gm Minimum Output Voltage VON VT+2VON 2VON 2VON 2(VT+VON) VT+2VON (min. is 2VON) Minimum Input Voltage VT+VON 2(VT+VON) VT+VON VT+2VON VT+2VON VT+VON (min. is VON)

Poor Excellent Excellent Excellent Poor GoodExcellent

ECE 6412 - Analog Integrated Circuits and Systems II

P.E. Allen - 2002

Lecture 030 ECE4430 Review III (1/9/04)

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Summary of BJT Current Mirrors Current Mirror Simple Cascode Wide Output Swing Cascode Self-biased Cascode Wilson Accuracy Output Input Resistance Resistance ro 1 gm 2 gm 1 gm Minimum Output Voltage VCE(sat) VCE(sat)+VBE 2VCE(sat) Minimum Input Voltage VBE 2VBE VBE

Poor Excellent Excellent Excellent Poor

" F ro " F ro " F ro " F ro

" F ro Regulated GoodCascode Excellent * One can design the regulated cascode so that effectively the minimum value of VMIN (out) is just VCE(sat).
ECE 6412 - Analog Integrated Circuits and Systems II P.E. Allen - 2002

1 2VCE(sat) VCE(sat)+VBE R + gm 2 VCE(sat)+VBE VCE(sat)+VBE gm 1 VCE(sat)* VCE(sat)* or less gm

Lecture 030 ECE4430 Review III (1/9/04)

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Active Load Amplifiers What is an active load amplifier?

VDD
+ V T+ 2VON + VT+VON -

VCC
+ VEB + VEB + VEC(sat) -

MOS Loads IBias IBias

BJT Loads

IBias

IBias

+ VT+ 2VON - V+ T+VON MOS Transconductors BJT Transconductors

+ VBE + VCE(sat) + VBE Fig. 030-14

It is a combination of any of the above transconductors and loads to form an amplifier. (Remember that the above are only some of the examples of transconductors and loads.)
ECE 6412 - Analog Integrated Circuits and Systems II P.E. Allen - 2002

Lecture 030 ECE4430 Review III (1/9/04)

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BJT Differential Amplifier with a Current Mirror Load Design Considerations: +5V Constraints Specifications 4.4V Q3 Q4 Power supply Small-signal gain iC3 iC4 Technology Frequency response (CL) vout iC1 iC2 Temperature ICMR CL Q1 Q2 Slew rate (CL) vOS Power dissipation IEE Relationships Q5 VBias Av = gm1Rout Fig. 030-15 -5V 8-3dB = 1/RoutCL vIC(max) = VCC - |VBE3| - VCE1(sat) + VBE1 & VCC - VCE1(sat) vIC(min) = VEE + VCE5(sat) + VBE1 SR = IEE/CL Pdiss = (VCC+|VEE|)All dc currents flowing from VCC or to VEE

ECE 6412 - Analog Integrated Circuits and Systems II

P.E. Allen - 2002

Lecture 030 ECE4430 Review III (1/9/04)

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CMOS Differential Amplifier with a Current Mirror Load Design Considerations: VDD Constraints Specifications Power supply Small-signal gain Technology Frequency response (CL) M3 M4 Temperature ICMR Slew rate (CL) + vin M1 Power dissipation Relationships I5 Av = gm1Rout M5 VBias 8-3dB = 1/RoutCL VSS VIC(max) = VDD - VSG3 + VTN1 VIC(min) = VDS5(sat) + VGS1 = VDS5(sat) + VGS2 SR = ISS/CL Pdiss = (VDD+|VSS|)All dc currents flowing from VDD or to VSS

vout

CL
M2

Fig. 030-16

ECE 6412 - Analog Integrated Circuits and Systems II

P.E. Allen - 2002

Lecture 030 ECE4430 Review III (1/9/04)

Page 030-23

Summary of Active Load Amplifiers Active load amplifier consists of a transconductor and a load There are a large number of combinations of loads and transconductors possible. We have not considered the many cascoded possibilities and other configurations. The BJT amplifier generally has more gain and wider signal swing than the MOS amplifier The voltage gain of the MOS transconductor with a current source or current mirror load is inversely proportional to the square root of the bias current. The current mirror load differential amplifier is a widely used input stage The frequency response is generally determined by the dominant pole which is found at points in the circuit that are high impedance to ac ground and large capacitance The active load amplifier is the primary gain stage in operational amplifiers and other applications and will be a fundamental building block in more complex circuits Performance not considered include slew rate and noise

ECE 6412 - Analog Integrated Circuits and Systems II

P.E. Allen - 2002

Lecture 030 ECE4430 Review III (1/9/04)

Page 030-24

SUMMARY Single and Multiple Transistor Amplifiers - Characterization - BJT: Common emitter, common-base, common-collector, general - MOSFET: Common source, common-gate, common-drain, general Cascode Amplifiers Differential Amplifiers - Differential mode analysis (balance requirements) 9 Half-circuit concept - Common mode analysis 9 Half-circuit concept - Input common mode range and slew rate Transistor Current Sources and Current Mirrors Active Load Amplifiers Other Material not Included in this Review - Voltage and Current References - Bandgap Voltage Reference - Simple two-stage op amps
ECE 6412 - Analog Integrated Circuits and Systems II P.E. Allen - 2002