L130 OpAmpCompII (2UP)

Lecture 130 Compensation of Op Amps-II (1/26/04) Page 130-1
ECE 6412 - Analog Integrated Circuits Design II P.E. Allen - 2002

LECTURE 130 COMPENSATION OF OP AMPS-II
(READING: GHLM 638-652, AH 260-269)
INTRODUCTION
The objective of this presentation is to continue the ideas of the last lecture on
compensation of op amps.
Outline
Compensation of Op Amps
General principles
Miller, Nulling Miller
Self-compensation
Feedforward
Summary
Conditions for Stability of the Two-Stage Op Amp (Assuming p
3
GB)
Unity-gainbandwith is given as:
GB = A
v
(0)|p
1
| =
\
|
|
[
)
j
j
g
mI
g
mII
R
I
R
II
g
mII
R
I
R
II
C
c
=
g
mI
C
c
=
\
|
|
[
)
j
j
g
m1
g
m2
R
1
R
2
g
m2
R
1
R
2
C
c
=
g
m1
C
c

The requirement for 45 phase margin is:
180 - Arg[AF] = 180 - tan
-1
\
|
[
)
j

|p
1
|

- tan
-1
\
|
[
)
j

|p
2
|

- tan
-1
\
|
[
)
j

z

= 45
Let = GB and assume that z 10GB, therefore we get,
180 - tan
-1
\
|
[
)
j
GB
|p
1
|

- tan
-1
\
|
[
)
j
GB
|p
2
|

- tan
-1
\
|
[
)
j
GB
z

= 45
135 tan
-1
(A
v
(0)) + tan
-1
\
|
[
)
j
GB
|p
2
|

+ tan
-1
(0.1) = 90 + tan
-1
\
|
[
)
j
GB
|p
2
|

+ 5.7
39.3 tan
-1
\
|
[
)
j
GB
|p
2
|

GB
|p
2
|
= 0.818 |p
2
| 1.22GB
The requirement for 60 phase margin:
|p
2
| 2.2GB if z 10GB
If 60 phase margin is required, then the following relationships apply:
g
m6
C
c
>
10g
m1
C
c
g
m6
> 10g
m1
and
g
m6
C
2
>
2.2g
m1
C
c
C
c
> 0.22C
2

Controlling the Right-Half Plane Zero
Why is the RHP zero a problem?
Because it boosts the magnitude but lags the phase - the worst possible combination for
stability.
j
j
1
j
2
j
3
3
Fig. 430-01
180 >
1
>
2
>
3
z
1
Solution of the problem:
If zeros are caused by two paths to the output, then eliminate one of the paths.
Use of Buffer to Eliminate the Feedforward Path through the Miller Capacitor
Model:
The transfer
function is given
by the following
equation,
V
o
(s)
V
in
(s)
=
(g
mI
)(g
mII
)(R
I
)(R
II
)
1 + s[R
I
C
I
+ R
II
C
II
+ R
I
C
c
+ g
mII
R
I
R
II
C
c
] + s
2
[R
I
R
II
C
II
(C
I
+ C
c
)]
Using the technique as before to approximate p
1
and p
2
results in the following
p
1

1
R
I
C
I
+ R
II
C
II
+ R
I
C
c
+ g
mII
R
I
R
II
C
c

1
g
mII
R
I
R
II
C
c
and
p
2

g
mII
C
c
C
II
(C
I
+ C
c
)
Comments:
Poles are approximately what they were before with the zero removed.
For 45 phase margin, |p
2
| must be greater than GB
For 60 phase margin, |p
2
| must be greater than 1.73GB
Fig. 430-02
Inverting
High-Gain
Stage
C
c
v
OUT g
mI
v
in
R
I
g
mII
V
I
R
II
C
II
V
I
C
c
+
-
V
ou
C
I
+
-
V
in
V
out
+1
Use of Buffer with Finite Output Resistance to Eliminate the RHP Zero
Assume that the unity-gain buffer has an output resistance of R
o
.
Model:
Inverting
High-Gain
Stage
+1
C
c
v
OUT g
mI
v
in
R
I
g
mII
V
I
R
II
C
II
V
I
C
c
+
-
V
out
C
I
+
-
V
in
R
o
R
o
V
out
Fig. 430-03
R
o
It can be shown that if the output resistance of the buffer amplifier, R
o
, is not neglected
that another pole occurs at,
p
4

1
R
o
[C
I
C
c
/(C
I
+ C
c
)]
and a LHP zero at
z
2

1
R
o
C
c
Closer examination shows that if a resistor, called a nulling resistor, is placed in series
with C
c
that the RHP zero can be eliminated or moved to the LHP.
Use of Nulling Resistor to Eliminate the RHP Zero (or turn it into a LHP zero)
Inverting
High-Gain
Stage
C
c
v
OUT
R
z
g
mI
v
in
R
I
g
mII
V
I
R
II
C
II
C
c
+
-
V
out
C
I
+
-
V
in
R
z
Fig. 430-04
V
I
Nodal equations:
g
mI
V
in
+
V
I
R
I
+ sC
I
V
I
+
\
|
|
[
)
j
j
sC
c
1 + sC
c
R
z
(V
I
V
out
) = 0
g
mII
V
I
+
V
o
R
II
+ sC
II
V
out
+
\
|
|
[
)
j
j
sC
c
1 + sC
c
R
z
(V
out
V
I
) = 0
Solution:
V
out
(s)
V
in
(s)
=
a{1 s[(C
c
/g
mII
) R
z
C
c
]}
1 + bs + cs
2
+ ds
3
where
a = g
mI
g
mII
R
I
R
II
b = (C
II
+ C
c
)R
II
+ (C
I
+ C
c
)R
I
+ g
mII
R
I
R
II
C
c
+ R
z
C
c
c = [R
I
R
II
(C
I
C
II
+ C
c
C
I
+ C
c
C
II
) + R
z
C
c
(R
I
C
I
+ R
II
C
II
)]
d = R
I
R
II
R
z
C
I
C
II
C
c

W.J. Parrish, "An Ion Implanted CMOS Amplifier for High Performance Active Filters", Ph.D. Dissertation, 1976, Univ. of CA., Santa Barbara.
Use of Nulling Resistor to Eliminate the RHP - Continued
If R
z
is assumed to be less than R
I
or R
II
and the poles widely spaced, then the roots of the
above transfer function can be approximated as
p
1

1
(1 + g
mII
R
II
)R
I
C
c

1
g
mII
R
II
R
I
C
c
p
2

g
mII
C
c
C
I
C
II
+ C
c
C
I
+ C
c
C
II

g
mII
C
II
p
4
=
1
R
z
C
I
(p
3
has been used previously for the mirror pole so we choose p
4
for the
nulling resistor pole)
and
z
1
=
1
C
c
(1/g
mII
R
z
)
Note that the zero can be placed anywhere on the real axis.
Conceptual Illustration of the Nulling Resistor Approach
V
DD
C
c
R
II
V
out
V
'
V
''
M6
R
z
Fig. Fig. 430-05
The output voltage, V
out
, can be written as
V
out
=
-g
m6
R
II
\
|
|
[
)
j
j
R
z
+
1
sC
c
R
II
+ R
z
+
1
sC
c
V +
R
II
R
II
+ R
z
+
1
sC
c
V =
-R
II
|
|
|
|
|
|
|
|
g
m6
R
z
+
g
m6
sC
c
- 1
R
II
+ R
z
+
1
sC
c
V
when V = V = V.
Setting the numerator equal to zero and assuming g
m6
= g
mII
gives,
z
1
=
1
C
c
(1/g
mII
R
z
)
A Design Procedure that Allows the RHP Zero to Cancel the Output Pole, p
2
We desire that z
1
= p
2
in terms of the previous notation.
Therefore,
1
C
c
(1/g
mII
R
z
)
=
g
mII
C
II
The value of R
z
can be found as
R
z
=
\
|
|
[
)
j
j
C
c
+ C
II
C
c
(1/g
mII
)
With p
2
canceled, the remaining roots are p
1
and p
4
(the pole due to R
z
) . For unity-gain
stability, all that is required is that
|p
4
| > A
v
(0)|p
1
| =
A
v
(0)
g
mII
R
II
R
I
C
c
=
g
mI
C
c

and
(1/R
z
C
I
) > (g
mI
/C
c
) = GB
Substituting R
z
into the above inequality and assuming C
II
>> C
c
results in
C
c
>
g
mI
g
mII
C
I
C
II
This procedure gives excellent stability for a fixed value of C
II
( C
L
).
Unfortunately, as C
L
changes, p
2
changes and the zero must be readjusted to cancel p
2
.
j
Fig. 430-06
-p
4
-p
2
-p
1
z
1
Increasing the Magnitude of the Output Pole
The magnitude of the output pole , p

2
, can be increased by introducing gain in the Miller
capacitor feedback path. For example,
V
DD
V
SS
V
Bias
C
c
M6
M7
M8
M9 M10
M4 M11
v
OUT
I
in
R
1
R
2
C
2
r
ds8
gm8Vs8
C
c
V
out
V
1
+
-
+
-
+
-
Vs8
I
in
R
1
R
2
C
2
g
m8
V
s8
V
out V
1
+
-
+
-
+
-
V
s8
1
gm8
C
c
g
m6
V
1
g
m6
V
1
Fig. 430-07
Ignore r
ds8

The resistors R
1
and R
2
are defined as
R
1
=
1
g
ds2
+ g
ds4
+ g
ds9
and R
2
=
1
g
ds6
+ g
ds7

where transistors M2 and M4 are the output transistors of the first stage.
Nodal equations:
I
in
= G
1
V
1
-g
m8
V
s8
= G
1
V
1
-
\
|
|
[
)
j
j
g
m8
sC
c
g
m8
+ sC
c
V
out
and 0 = g
m6
V
1
+
|
|
|
|
|
|
|
|
G
2
+sC
2
+
g
m8
sC
c
g
m8
+sC
c
V
out

B.K. Ahuja, An Improved Frequency Compensation Technique for CMOS Operational Amplifiers, IEEE J. of Solid-State Circuits, Vol. SC-18,
No. 6 (Dec. 1983) pp. 629-633.
Increasing the Magnitude of the Output Pole - Continued
Solving for the transfer function V
out
/I
in
gives,
V
out
I
in
=
\
|
|
[
)
j
j
-g
m6
G
1
G
2

|
|
|
|
|
|
|
|
|
|
\
|
|
[
)
j
j
1 +
sC
c
g
m8
1 + s
|
|
|
|
|
|
|
|

C
c
g
m8
+
C
2
G
2
+
C
c
G
2
+
g
m6
C
c
G
1
G
2
+ s
2

\
|
|
[
)
j
j
C
c
C
2
g
m8
G
2

Using the approximate method of solving for the roots of the denominator gives
p
1
=
-1
C
c
g
m8
+
C
c
G
2
+
C
2
G
2
+
g
m6
C
c
G
1
G
2

-6
g
m6
r
ds
2
C
c

and
p
2

-
g
m6
r
ds
2
C
c
6
C
c
C
2
g
m8
G
2
=
g
m8
r
ds
2
G
2
6

\
|
|
[
)
j
j
g
m6
C
2
=
\
|
|
[
)
j
j
g
m8
r
ds
3
|p
2
|
where all the various channel resistance have been assumed to equal r
ds
and p
2
is the
output pole for normal Miller compensation.
Result:
Dominant pole is approximately the same and the output pole is increased by g
m
r
ds
.
Concept Behind the Increasing of the Magnitude of the Output Pole
V
DD
C
c
r
ds7
v
out
M6
C
II
GBC
c
1
0
V
DD
v
out
M6
C
II
M8
g
m8
r
ds8
Fig. Fig. 430-08
r
ds7
3
R
out
= r
ds7
||
\
|
|
[
)
j
j
3
g
m6
g
m8
r
ds8

3
g
m6
g
m8
r
ds8

Therefore, the output pole is approximately,
|p
2
|
g
m6
g
m8
r
ds8
3C
II

Besides, the common gate amplifier stops the feedforward path preventing the RHP zero.
FEEDFORWARD COMPENSATION
Use two parallel paths to achieve a LHP zero for lead compensation purposes.
C
c
A
V
out
V
i
Inverting
High Gain
Amplifier
C
II
R
II
RHP Zero
C
c
-A
V
out
V
i
Inverting
High Gain
Amplifier
C
II
R
II
LHP Zero
A
C
II
R
II
V
i V
out
C
c
g
mII
V
i
+
-
+
-
Fig.430-09
C
c
V
out V
i
+1
LHP Zero using Follower
V
out
(s)
V
in
(s)
=
AC
c
C
c
+ C
II

\
|
|
[
)
j
j
s + g
mII
/AC
c
s + 1/[R
II
(C
c
+ C
II
)]
To use the LHP zero for compensation, a compromise must be observed.
Placing the zero below GB will lead to boosting of the loop gain that could deteriorate
the phase margin.
Placing the zero above GB will have less influence on the leading phase caused by the
zero.
Note that a source follower is a good candidate for the use of feedforward compensation.
SELF-COMPENSATED OP AMPS
Self compensation occurs when the load capacitor is the compensation capacitor (can
never be unstable for resistive feedback)
Fig. 430-10
-
+
v
in v
out
C
L
+
-
G
m
R
out
(must be large)
Increasing C
L
|dB|
A
v
(0) dB
0dB
R
out
-20dB/dec.
Voltage gain:
v
out
v
in
= A
v
(0) = G
m
R
out

Dominant pole:
p
1
=
-1
R
out
C
L

Unity-gainbandwidth:
GB = A
v
(0)|p
1
| =
G
m
C
L

Stability:
Large load capacitors simply reduce GB but the phase is still 90 at GB.
SUMMARY
Compensation
Designed so that the op amp with unity gain feedback (buffer) is stable
Types
- Miller
- Miller with nulling resistors
- Self Compensating
- Feedforward

L130 OpAmpCompII (2UP)

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Lecture 130 Compensation of Op Amps-II (1/26/04) Page 130-1

ECE 6412 - Analog Integrated Circuits Design II P.E. Allen - 2002

The magnitude of the output pole , p

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