CHAPTER DESIGN OF UART MODULE IN VERILOG A UART is a useful component for controlling asynchronous (without a separate clock line)

serial buses. It can be used via a level converter to talk to the R !"! serial port of a computer. This is not# however# the only application. It could also be used as a local chip bus# or with differential signalling to connect to peripherals over $uite long distances.

I/O Standards, Compatab ! t" This follows standard UART signalling methods with the following properties% & '(pects to send and receive data as ) data bits# no parity bits. & *efault baud rate is +,-- with a .-/01 clock. This is configurable. & amples values roughly in the middle of each bit (may drift slightly). & ends and receives least significant bit first. & '(pects to receive at least 2 stop bit. 3ill not check for more# but won4t fail either. & Transmits ! stop bits. D#s$r pt on o% np&ts and o&tp&ts

& 5clk5 is the master clock for this component. 6y default this will run at +,-- baud with a clock of .-/01# but this can be altered as described in the 5Ad7usting 8lock Rate 9 6aud Rate5 section below. & 5rst5 is a synchronous reset line (resets if high when the rising edge of clk arrives). Raising this high for one cycle of clk will interrupt any transmissions in progress and set it back to an idle state. *oing this unneccessarily is not recommended : the receive component could

become confused if reset halfway through a transmission. This can be unconnected if you don4t need to reset the component. & 5r(5 is the serial line which the component will receive data on. This would usually be connected to an outside pin. & 5t(5 is the serial line which the component will transmit data on. This would usually be connected to an outside pin. & The input flag 5transmit5 is a signal you use to indicate that the UART should start a transmission. If the transmit line is idle and this is raised for one clock cycle# the component will copy the content of the t(;byte input and start transmitting it. If raised while the line is busy# this signal will be ignored. The is;transmitting output mentioned later can be used to test this and avoid missing a byte. & The input 5t(;byte5 is an ):bit bus containing the byte to be transmitted when 5transmit5 is raised high. 3hen 5transmit5 is low# this may change without interrupting the transfer. & 5received5 is an output flag which is raised high for one cycle of clk when a byte is received. & The output 5r(;data5 is set to the value of the byte which has 7ust been received when 5received5 is raised. It is recommended that this be used immediately in the cycle when 5raised5 is high or saved in to a register for future use. 3hile this is likely to remain accurate until the start of the ne(t incoming byte arrives# this should not be relied on. & The output 5is;receiving5 indicates that we are currently receiving data on the r( line. This could be used for e(ample to provide an early warning that a byte may be about to be received. 3hen this signal is true# it will not become false again until either 5received5 or

5recv;error5 has been asserted. If you don4t need early warning# this can safely be left disconnected. & The output 5is;transmitting5 indicates that we are currently sending data on the t( line. This is often important to track# because we can only send one byte at once. If we need to send another byte and this is high# the code outside will have to wait until this goes low before it can begin. This can be ignored if you know that you will never try to transmit while another transmission is in progress# for e(ample when transmissions happen at fi(ed intervals longer than the time it takes to transmit a packet (22 bit periods : 7ust under 2.!ms at +,-- baud) . & recv;error is an output indicating that a malformed or incomplete byte was received. If you simply wish to ignore bad incoming bytes# you can safely leave this signal disconnected. 3ith 5rst5# 5is;receiving5 and 5recv;error5 disconnected# the invocation would look like% uart /yInstance<ame (clk# # r(# t(# transmit# t(;byte# received# r(;byte# # is;transmitting# )= >> Ad7usting 8lock Rate 9 6aud Rate >> The clock rate and baud rate can be altered by changing the 8?@8A;*IBI*' parameter passed in to the uart module. This value is calculated by taking the clock fre$uency in 01 (for e(ample# .-/01 is .-#---#--- 01)# dividing it by the baud rate times C (for e(ample +,--) 8?@8A;*IBI*' > Dre$uency(clk) 9 (C & 6aud) VERILOG CODE FOR UART' (t m#s$a!# )ns / )ps

mod&!# &art*

np&t $!+, np&t rst, np&t r,, o&tp&t t,, np&t transm t, np&t -.'/0 t,1b"t#, o&tp&t r#$# 2#d, o&tp&t -.'/0 r,1b"t#, o&tp&t s1r#$# 2 n3, o&tp&t s1transm tt n3, o&tp&t r#$21#rror 45

param#t#r CLOC61DIVIDE 7 )8/95

param#t#r R:1IDLE 7 /5 param#t#r R:1CHEC61START 7 )5 param#t#r R:1READ1;ITS 7 95 param#t#r R:1CHEC61STOP 7 85 param#t#r R:1DELA<1RESTART 7 =5

param#t#r R:1ERROR 7 >5 param#t#r R:1RECEIVED 7 ?5

param#t#r T:1IDLE 7 /5 param#t#r T:1SENDING 7 )5 param#t#r T:1DELA<1RESTART 7 95

r#3 -)/'/0 r,1$!+1d 2 d#r 7 CLOC61DIVIDE5 r#3 -)/'/0 t,1$!+1d 2 d#r 7 CLOC61DIVIDE5

r#3 -9'/0 r#$21stat# 7 R:1IDLE5 r#3 ->'/0 r,1$o&ntdo@n5 r#3 -8'/0 r,1b ts1r#ma n n35 r#3 -.'/0 r,1data5

r#3 t,1o&t 7 )Ab)5 r#3 -)'/0 t,1stat# 7 T:1IDLE5 r#3 ->'/0 t,1$o&ntdo@n5 r#3 -8'/0 t,1b ts1r#ma n n35 r#3 -.'/0 t,1data5

ass 3n r#$# 2#d 7 r#$21stat# 77 R:1RECEIVED5 ass 3n r#$21#rror 7 r#$21stat# 77 R:1ERROR5 ass 3n s1r#$# 2 n3 7 r#$21stat# B7 R:1IDLE5 ass 3n r,1b"t# 7 r,1data5

ass 3n t, 7 t,1o&t5 ass 3n s1transm tt n3 7 t,1stat# B7 T:1IDLE5

a!@a"s C*pos#d3# $!+4 b#3 n % *rst4 b#3 n r#$21stat# 7 R:1IDLE5 t,1stat# 7 T:1IDLE5 #nd

r,1$!+1d 2 d#r 7 r,1$!+1d 2 d#r D )5 % *Br,1$!+1d 2 d#r4 b#3 n r,1$!+1d 2 d#r 7 CLOC61DIVIDE5 r,1$o&ntdo@n 7 r,1$o&ntdo@n D )5 #nd t,1$!+1d 2 d#r 7 t,1$!+1d 2 d#r D )5 % *Bt,1$!+1d 2 d#r4 b#3 n

t,1$!+1d 2 d#r 7 CLOC61DIVIDE5 t,1$o&ntdo@n 7 t,1$o&ntdo@n D )5 #nd

// R#$# 2# stat# ma$E n# $as# *r#$21stat#4 R:1IDLE' b#3 n

% *Br,4 b#3 n

r,1$!+1d 2 d#r 7 CLOC61DIVIDE5 r,1$o&ntdo@n 7 95 r#$21stat# 7 R:1CHEC61START5 #nd #nd R:1CHEC61START' b#3 n % *Br,1$o&ntdo@n4 b#3 n

% *Br,4 b#3 n

r,1$o&ntdo@n 7 =5

r,1b ts1r#ma n n3 7 F5 r#$21stat# 7 R:1READ1;ITS5 #nd #!s# b#3 n

r#$21stat# 7 R:1ERROR5 #nd #nd #nd R:1READ1;ITS' b#3 n % *Br,1$o&ntdo@n4 b#3 n r,1data 7 Gr,, r,1data-.')0H5 r,1$o&ntdo@n 7 =5 r,1b ts1r#ma n n3 7 r,1b ts1r#ma n n3 D )5 r#$21stat# R:1CHEC61STOP5 #nd #nd R:1CHEC61STOP' b#3 n % *Br,1$o&ntdo@n4 b#3 n 7 r,1b ts1r#ma n n3 I R:1READ1;ITS '

r#$21stat# 7 r, I R:1RECEIVED ' R:1ERROR5 #nd #nd R:1DELA<1RESTART' b#3 n r#$21stat# R:1DELA<1RESTART ' R:1IDLE5 #nd R:1ERROR' b#3 n 7 r,1$o&ntdo@n I

r,1$o&ntdo@n 7 F5 r#$21stat# 7 R:1DELA<1RESTART5 #nd R:1RECEIVED' b#3 n

r#$21stat# 7 R:1IDLE5 #nd #nd$as#

// Transm t stat# ma$E n# $as# *t,1stat#4 T:1IDLE' b#3 n

% *transm t4 b#3 n

t,1data 7 t,1b"t#5 t,1$!+1d 2 d#r 7 CLOC61DIVIDE5 t,1$o&ntdo@n 7 =5 t,1o&t 7 /5 t,1b ts1r#ma n n3 7 F5 t,1stat# 7 T:1SENDING5 #nd #nd T:1SENDING' b#3 n % *Bt,1$o&ntdo@n4 b#3 n % *t,1b ts1r#ma n n34 b#3 n t,1b ts1r#ma n n3 7 t,1b ts1r#ma n n3 D )5 t,1o&t 7 t,1data-/05 t,1data 7 G)Ab/, t,1data-.')0H5 t,1$o&ntdo@n 7 =5 t,1stat# 7 T:1SENDING5 #nd #!s# b#3 n t,1o&t 7 )5 t,1$o&ntdo@n 7 F5

t,1stat# 7 T:1DELA<1RESTART5 #nd #nd #nd T:1DELA<1RESTART' b#3 n t,1stat# 7 t,1$o&ntdo@n I T:1DELA<1RESTART ' T:1IDLE5 #nd #nd$as# #nd

#ndmod&!#