25 nm CMOS Design Considerations

Yuan Taw, Clement H. Wann, and ]David J. Frank

IBM T. J. Watson Research Center, Yorktown Heights. New York

Abstract
This paper explores the limit of bulk (or partiallydepleted SOI) CMOS scaling. A feasible design for 25 nm (channel length) CMOS, without continued scaling of oxide thickness and power supply voltage, is presented. A highly 2-D nonuniform profile (super-halo) is shown to yield low off-currents while delivering a significant performance advantage for a 1.0 V power supply. Several key issues, including source-drain doping requirements, band-to-band tunneling, and poly depletion effects, are examined and quantified. It is projected, based on Monte-Carlo simulations, that the delay performance of 25 nm CMOS is 3x higher than 100 nm CMOS, and that the nFET f r exceeds 250 GHz.

edges with very restricted amount of diffusion, as shown in the examplle in Fig. 2. The highly nonuniform profile tends to offset short-channel effects, yielding ZO8 independent of channel length variations between 20 and 30 nm (Fig. 3). The superior short-channel effect obtained with the superhalo is slhown in Fig. 4, compared with a non-halo retrograde profile. Because of the flat 6 dependence on channel length, super-halo allows a nominal device to operate at a lower threshold voltage, thereby gaining significant performance benefit: 30-40% over non-halo devices as shown in Fig. 5. Note that DIBL, which is still present in super-halo devices, has only a minor effect on the delay performance.

Introduction
CMOS design options below 0.1 pm are severely constrained by fundamental issues of oxide tunneling and voltage nonscaling [l]. In this work. we explore the limit of CMOS scaling and present a feasible design for 25 nm (channel length) bulk CMOS, without continued scaling of oxide thickness and power supply voltage. Such channel lengths can be achieved at a lithography generation of 50 nm resolution, in year 2012 according to the SIA roadmap. Key issues, such as gate work function, channel and sourcedrain doping requirements, poly depletion effect, dopant fluctuations, and nonequilibrium carrier transport in 25 nm CMOS areaddressed.

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Short Channel Device Design

While straight 2-D scaling calls for a gate oxide thinner than 1 nm for 25 nm MOSFETs, direct tunneling leakage in oxidehitride gate insulators will limit the equivalent gate oxide thickness to 1.5 nm [2][3]. To maintain adequate off-currents for an integration level of 108-109devices per chip, the threshold voltage must be kept at a minimum value of 0.2 V under the worst-case conditions. A suitable choice of the power supply voltage is 1.0 V, as a reasonable trade-off among active power, device performance, and high field effects. With the nonscaled gate oxide and supply voltage, an optimized, vertically and laterally nonuniform doping profile, called the super-halo [I], is needed to control the short-channel effect. Fig. 1 shows such a doping profile, along with simulated potential contours for a 25 nm MOSFET. In principle, such a profile can be realized by ion implantation self-aligned to the gate

Fig. 1. Source, drain, and super-halo doping contours in a 25 nm W O S F E T design. The channel length is defined by the points
where the source-drain doping concentration falls to 2 x ~m-~. The dashed llines show the potential contours for zero gate voltage and a drain bias of 1.O V. \v = 0 references to the midgap energy level of the substrate.

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Source-Drain Doping Requirements

Another merit of super-halo is that it is more forgiving on the junction depth. Fig. 4 shows that the V, roll-off is rather insensitive to the vertical junction depth, with only a slight change when the junction depth is doubled from 25 nm to 50 nm for the same halo profile. This points to a way out of the high resistance problem. associated with very shallow extensions [4]. The lateral source-drain gradient, however, is much more critical, as can be seen in Fig. 6 which shows that the short-channel effect degrades rapidly once the profile is more graded than 4-5 nddecade. This is because the channel length is largely determined by the points of current injection from the surface layer into the bulk, which takes place at a source-drain doping concentration of about 2 x 1019 cm-3 [ 5 ] . Any source-drain doping that extends beyond this point into the channel tends to compensate or counter-dope the channel region and aggravate the short-channel effect. The abruptness requirements of both the source-drain and the halo doping profiles dictate absolutely minimum thermal cycles after the implants. Note that a raised source-drain structure may help making contacts, but does not by itself satisfy the abruptness requirement &scussed here.
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Fig. 3. Subthreshold currents for channel lengths from 30 to 15 nm. A/cm ( 1 nA/pm) for 20,25, and 30 nm devices.

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Fig. 4. Short-channel threshold roll-off for super-halo and retrograde (non-halo)doping profiles. Threshold voltage is defined as the gate voltage where Ids = 1 I*A/p.
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Fig 6. Effect of lateral source-drain doping gradient on shortchannel effect. One of the concerns with the high p-type doping level and narrow depletion regions in Fig. 1 is the band-toband tunneling through the high-field region between the phalo and the drain. Fig. 7 plots the calculated tunneling current density as a hnction of the electric field, along with published data on the reverse leakage current of n"/p+ diodes [6][7]. For the peak field intensity at high drain and zero gate biases shown in Fig. 1, the tunneling current density is on the order of I Alan2. This should not constitute a major component of the device leakage current, given the narrow width of the high-field region. If necessary, the peak field can be further reduced by trading off with a more graded source-drain profile, andlor by

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Fig. 5. CMOS delay (relative) versus high-drain threshold voltage. Non-halo devices must operate at a higher V, to ensure low of the worst-case device.

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applying a forward bias to the p-substrate to lower the potential difference across the drain junction.
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because although poly depletion causes a loss in the drive current, it i&O decreases the charge needed for the next stage. These two effects tend to cancel each other. For the heavily loaded case in which the devices drive a large fixed capacitance, the delay degradation approaches those of the on-currents in Fig. 8 (=15%0). This can be compensated to some extent by using wider devices. On the average, the performance: loss due to poly depletion effect is about 10% for partially-loaded 25 nm CMOS circuits with a 1.5 nm thick oxide.
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Fig. 7. Band-to-band tunneling current density (normalized to a junction voltage of 1 V) versus electric field. The arrow indicates the maximum field strength under the off condition in Fig. 1.

Polysilicon-Gate Depletion Effects

The threshold design in Fig. 4 assumes dual n+/pf Si work function gates for nMOS/pMOS, respectively. A midgap work function metal gate would clearly result in threshold voltage magnitudes far too high for both devices [SI. However, with doped poly gates, one must address the effect of poly depletion on CMOS performance. Since the capacitance of the poly depletion layer is not a constant, but depends on both the gate voltage and the quasi-Fenni potential along the channel, treating it as an equivalent oxide layer will substantially overestimate its effect [SI. We use a time-dependent (mixed mode) 2-D device model to simulate CMOS inverter delays with and without poly depletion. Fig. 8 compares the simulated on-currents between a poly-gated and a metal-gated device with the same channel doping profile. The threshold voltage is adjusted so that both devices have the same off-current. While typical C-V data of 1.5 nm oxides show about 40% less capacitance at inversion than that of the physical oxide, the currents are degraded by only 10-20%. One of the reasons is that part of the capacitance loss comes from quantum mechanical effect in the inversion layer, which is present regardless of the gate material [ 9 ] . Another factor is that not all the poly depletion charge is located at the far edge of the poly depletion layer that enters the small-signal C-V measurement. A third factor, more applicable to the less velocity-saturated PMOS in Fig. 8, is that while the inversion charge density is higher in metal-gate devices, carrier mobilities are lower because of the higher vertical field (like having a thinner oxide [lo]). The simulated delay degradation as a function of the load capacitance is shown in Fig. 9. The intrinsic, unloaded inverter delay is only slightly degraded (=5%)

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Fig. 8. nlpM0S currents with and without poly depletion effect. Poly doping ccincentrations assumed are 8x 10 ~ m - ~ .

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Fig. 9. CMOS delay degradation due to poly depletion effect as a

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Monte-Carlo Simulations of 25 nm CMOS

Extensive 3-D statistical simulations are carried out on the effects of dopant fluctuations on threshold voltage in 25 nm CMOS. For the doping profile in Fig. 1, dopant number fluctuations cause a l O / m mV-pm (lo) uncertainty in the threshold voltage [ll], where W is the device width. T h i s should be tolerable for logic circuits, but is a design (consideration in minimum width devices in SRAM cells.

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To evaluate the potential on-state performance of 25 nm CMOS, detailed Monte Carlo simulations were performed using the simulator DAMOCLES [ 121[131. Both n- and p-channel MOSFETs have been simulated, yielding low output conductance, high performance I-V characteristics for both device types, as are illustrated in Fig. 10. The transconductance exceeds 1500 mS/mm for t h s # E T , with an estimatedfT higher than 250 GHz. Transient Monte Carlo simulations were also done for a 3-stage chain of 25 nm CMOS inverters. Fig. 11 shows the output waveforms. The estimated delay time is 7-7.5 ps, about 3 times faster than 100 nm CMOS (1.5 V ) .
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Conclusion
In conclusion, we presented a feasible design for 25 nm bulk (including partially-depleted SOI) CMOS with super-halo. Low threshold-voltage requirements dictate gate work functions similar to those of n and p poly. It is shown that the poly depletion effect imposes only a =lo% performance penalty, even for 1.5 nm gate oxides. It is also shown that the vertical junction depth need not be scaled as aggressively as the lateral source-drain gradient. Transient Monte-Carlo simulations project the delay performance for 25 nm CMOS to be about 3x faster than todays 100 nm CMOS. The 25 nm design point is likely to be near the limit of CMOS scaling in view of both the oxide and the band-to-band tunneling currents. It should be noted that other alternative device structures, such as ultra-thin SO1 or double-gate MOSFETs, are also subject to similar limitations around 25 nm [14].

Acknowledgement
The authors would like to thank Kam Lee for many stimulating discussions.

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References
[ l ] Y. Taur and E. J. Nowak, CMOS Devices below 0.1 pm: How High Will Performance Go? 1997 IEDM Technical Digest, p. 21 5. [2] S.-H. Lo et al., Quantum-Mechanical Modeling of Electron Tunneling Current from the Inversion Layer of Ultra-Thin-Oxide nMOSFETs, IEEEElec. Dev. Lett. 18, pp. 209-21 1 (1997). [3] M. Khare et al., Ultra-Thin Silicon Nitride Gate Dielectric for Deep Submicron CMOS Devices, 1997 KlSI Tech. Symp., p. 51. [4]S. Thompson et al., Source-Drain Extension Scaling for 0.1 pm and below Channel Length MOSFETs, 1998 KLYI Tech. Symp., p . 132. [SIY.Taur, Y.J. Mii, R. Logan, and H. S. Wong, On Effective Channel Length in 0.1 pm MOSFETs, IEEEElec. Dev. Lett., 16,136 (1995). [6]R. B. Fair and H. W. Wivell, Zener and Avalanche Breakdown in As-Implanted Low-Voltage Silicon N-P Junctions, IEEE Trans. Electron Devices, ED-23, p. 512, (1976). [7] J. M. C. Stork and R. D. Isaac, Tunneling in Base-Emitter Junctions, IEEE Trans.Electron Devices, ED-30, p. 1527, (1983). [S] Y. Taur and T. H. Ning, Fundamentals o f Modem VLSl Devices, Cambridge University Press, New York, 1998. [9] Y. Taur et al., CMOS Scaling into the Nanometer Regime, IEEE Proceedings, (1997). [lo] K. Chen, C. Wann, P. KO, and C. Hu, The Impact of Device Scaling and Power Supply Change on CMOS Gate Performance, IEEE Elec. Dev. Lett., 17,202 (1996). [ l l ] D. J. Frank, unpublished. [12] S. E. Laux, M. V. Fischetti, and D. J. Frank, Monte Carlo analysis of semiconductor devices: The DAMOCLES program, IBM Journal o f Research and Development, 34,466 ( 1990). [13] S. E. Laux and M. V. Fischetti, Monte Carlo Study of Velocity Overshoot in Switching a 0.1 Micron CMOS Inverter, 1997 ZEDM TechnicalDigest, p. 877. [14] H.-S. P. Wong, D. J. Frank, and P. M. Solomon, Device Design Considerations for Double-Gate, Ground-Plane, and Single-Gate UltraThin SO1 MOSFETs at the 25 nm Gate Length Generation, 1998 IEDM Digest.

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Fig. 11. Monte Carlo simulation of 25 nm CMOS inverter delay. The pFET is twice the width of S E T . There is a third stage loading the output of the second stage.

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