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The interrupt I/O is a process of data transfer where-by an external device or a peripheral can inform the microprocessor that it is ready for communication The interrupt requests are classified in two categories: 1.Maskable interrupt request can be ignored or delayed by the microprocessor and used in telephone 2 .Non - Mask able interrupt request the microprocessor respond immediately and used in smoke detector. The interrupt process can be described by the following steps: 1.The interrupt should be enabled by writing the instruction EI in main program. 2 .When The microprocessor is executing a program , it check the INTR during executing of each instruction. 3 .If the line INTR is high , the microprocessor send INTA (acknowledge). 4.The Microprocessor can not accept any other interrupt request.

The 8085 Interrupts

The 8085 has five interrupt inputs )Fig.12.1) one is called INTR. Which is Identical with INT input in the 8080A.The other four are automatically vectored (transferred) to specific location on memory page 00H without any external hardware .They do not require the INTA signal or an input port ;the necessary hardware is already implemented inside the 8085.These interrupts and their call locations are as follows:

Priority Input 2

RST 7.5

Mask D CLR Q Q

Vector Locations 003C16

RST 7.5 Interrupt Recognized r






RST 4 5.5

003016 002C16 002816

D1 Reset Any Interrupt Recognized


002416 S R
Interrupt Enable

Q 002016 001816 001016

e Enable
Get RST Code from External Hardware

000816 000016


Figure (12.1) The 8085 Interrupts and Vector Locations.

Interrupts 1. TRAP 2. RST 7.5 3. RST 6.5 4. RST 5.5

Call Locations 0024H 003CH 0034H 002CH

The TRAP has the highest priority, followed by RST 7.5,6.5,5.5, and INTR , in that order

TARP: a non mask able interrupt known as NMI, it has the highest priority, it need not be
enabled ; and it cannot be disable.

RST: (Restart) Special Restart Instruction used with interrupts. It can be used as software
instruction in a program to transfer program execution to one of the eight Locations . The addresses are: Instruction RST 0 RST 1 RST 2 RST 3 RST 4 RST 5 RST 6 RST 7 Restart Address 0000H 0008H 0010H 0018H 0020H 0028H 0030H 0038H

SIM: (set interrupt mask) This is a multipurpose instruction and used to implement The 8085 interrupts 7.5, 6.5, 5.5, and serial data output. The instruction interrupts the accumulator contents as following:



5 Xxx

R 7.5 MSE M7.5

M 6.5 M5.5

RST 7.5 MASK 0= available RST 6.5 MASK RST 5.5 MASK Mask Set Enable -If 0,Bits 0-2 ignored If 1, mask is set RESET RST 7.5:if1 ,RST 7.5 flip-flop is reset OFF 1= masked

If 1, bit 7 is output to Serial Output Data Latch Serial Output Data : ignored if bit 6=0

Figure (12.2) Interpretation of the Accumulator Bit Example (12.1) . Instructions EI MVI A ,08H SIM ;Enable interrupts ;Load bit Pattern to enable RST 7.5 ,6.5 and 5.5 ;Enable RST 7.5,6.5,and 5.5 Enable all the interrupts in an 8085 system

Bit D3= 1 in the accumulator makes the instruction SIM functional , and bits D2, D1, and D0 =0 enable the interrupts 7.5 ,6.5 and 5.5 Example (12.2) Instructions MVI A, 18H SIM ; Set D4 = 1 ; Reset 7.5 interrupt flip-flop Reset the 7.5 interrupt from Example 12.1

RIM: (Read Interrupt Mask ) this is a multi purpose instruction used to read the Status of interrupts 7.5, 6.5 ,5.5 and read serial data input bit . The instruction loads eight bits in the accumulator with the following interpretations: 7 SID 6 17 5 16 4 15 3 1E 2 7.5 1 0

6.5 5.5

Interrupt Masks : 1= masked Interrupt Enable Flag : 1= enabled Pending Interrupts: 1= Pending Serial Input Data Bit , if any

Figure (12.3) Interpretation of the Accumulator Bit Pattern for the RIM Instruction

1.NOP: (No operation ) No operation to be performed. 2 . HLT: (Halt and enter wait state ) The CPU finishes executing the current instruction And halts any further execution . 3. DI: (Disable Interrupt System) The interrupt enable flip-flop is reset and all the Interrupts except the TRAP are disabled . No flags are affected . 4. EI: (Enable Interrupt System ) The interrupt enable flip-flop is set and all interrupts Are enabled . No flags are affected.

If INTR is activated , the 8085 responds with INTA Pulse , during the IINTA pulse , the 8085 expect to see an instruction applied to it is data bus
1k 1 1 1 0 0 1 7 1 1 kkk k E +5v


AD7 AD6 AD5 AD4 8085 AD3 AD2 AD1 AD0

INTA INTR A circuit that causes an RST4 instruction (E7)H to be executed in response to INTR. The RST4 instruction causes the subroutine stored beginning at OO20H to be executed. .